diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 778d9c9a1..3b8944506 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -362,7 +362,7 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = { .get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset, .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, - .set_pmu_options_boost_clock_frequencies = gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, + .set_pmu_options_boost_clock_frequencies = NULL, .hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_DEBUG_FS @@ -374,7 +374,7 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = { .hw_record_ts_timestamp = gm20b_ctxsw_prog_hw_record_ts_timestamp, .hw_get_ts_record_size_in_bytes = gm20b_ctxsw_prog_hw_get_ts_record_size_in_bytes, .is_ts_valid_record = gm20b_ctxsw_prog_is_ts_valid_record, - .get_ts_buffer_aperture_mask = gm20b_ctxsw_prog_get_ts_buffer_aperture_mask, + .get_ts_buffer_aperture_mask = NULL, .set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records, .set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr, #endif @@ -455,6 +455,8 @@ static const struct gops_gr_init gv11b_ops_gr_init = { .get_no_of_sm = nvgpu_gr_get_no_of_sm, .get_nonpes_aware_tpc = gv11b_gr_init_get_nonpes_aware_tpc, .ecc_scrub_reg = gv11b_gr_init_ecc_scrub_reg, + .lg_coalesce = NULL, + .su_coalesce = NULL, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, .gpc_mmu = gv11b_gr_init_gpc_mmu, .fifo_access = gm20b_gr_init_fifo_access, @@ -829,7 +831,7 @@ static const struct gops_fifo gv11b_ops_fifo = { .get_mmu_fault_desc = NULL, .get_mmu_fault_client_desc = NULL, .get_mmu_fault_gpc_desc = NULL, - .get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice, + .get_runlist_timeslice = NULL, .get_pb_timeslice = gk20a_fifo_get_pb_timeslice, .mmu_fault_id_to_pbdma_id = gv11b_fifo_mmu_fault_id_to_pbdma_id, .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h index 6d5dddb7e..aa77361c9 100644 --- a/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h @@ -42,7 +42,6 @@ void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index); -u32 gm20b_ltc_zbc_table_size(struct gk20a *g); #endif /* CONFIG_NVGPU_GRAPHICS */ #ifdef CONFIG_NVGPU_DEBUGGER bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr); diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index 01efd0b93..799010264 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -182,4 +182,26 @@ ((U32(v) & 0x3U) << 0U) #define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) #define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\ + ((U32(v) & 0xffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\ + (U32(0x1ffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\ + ((U32(v) & 0xffffffffU) << 0U) +#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U) +#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U) +#define ctxsw_prog_record_timestamp_magic_value_hi_o() (0x00000004U) +#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v() (0x600dbeefU) +#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v)\ + ((U32(v) & 0xffffffU) << 0U) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\ + (((r) >> 0U) & 0xffffffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v)\ + ((U32(v) & 0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index cb481742d..2a757e22e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -73,6 +73,8 @@ #define fb_mmu_ctrl_atomic_capability_mode_rmw_f() (0x2000000U) #define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m() (U32(0x1U) << 27U) #define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f() (0x0U) +#define fb_mmu_ctrl_use_full_comp_tag_line_v(r) (((r) >> 12U) & 0x1U) +#define fb_mmu_ctrl_use_full_comp_tag_line_true_f() (0x1000U) #define fb_hshub_num_active_ltcs_r() (0x001fbc20U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f() (0x0U) @@ -165,11 +167,21 @@ #define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) #define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) #define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_enabled_f() (0x10000U) #define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U) #define fb_mmu_vpr_info_r() (0x00100cd0U) #define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U) #define fb_mmu_vpr_info_fetch_false_v() (0x00000000U) #define fb_mmu_vpr_info_fetch_true_v() (0x00000001U) +#define fb_mmu_vpr_info_index_f(v) ((U32(v) & 0x3U) << 0U) +#define fb_mmu_vpr_info_index_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_vpr_info_index_addr_lo_v() (0x00000000U) +#define fb_mmu_wpr_info_r() (0x00100cd4U) +#define fb_mmu_wpr_info_index_f(v) ((U32(v) & 0xfU) << 0U) +#define fb_mmu_wpr_info_index_allow_read_v() (0x00000000U) +#define fb_mmu_wpr_info_index_wpr1_addr_lo_v() (0x00000002U) +#define fb_mmu_wpr_info_index_wpr1_addr_hi_v() (0x00000003U) #define fb_mmu_l2tlb_ecc_control_r() (0x00100e6cU) #define fb_mmu_l2tlb_ecc_control_inject_uncorrected_err_f(v)\ ((U32(v) & 0x1U) << 5U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index baac88432..152775cf4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -793,6 +793,9 @@ #define gr_fecs_new_ctx_target_f(v) ((U32(v) & 0x3U) << 28U) #define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_new_ctx_valid_s() (1U) #define gr_fecs_new_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U) #define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) @@ -806,6 +809,9 @@ #define gr_fecs_arb_ctx_ptr_target_f(v) ((U32(v) & 0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) #define gr_fecs_arb_ctx_cmd_cmd_s() (5U) #define gr_fecs_arb_ctx_cmd_cmd_f(v) ((U32(v) & 0x1fU) << 0U) @@ -1556,6 +1562,10 @@ #define gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) #define gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m()\ (U32(0x1U) << 27U) +#define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f() (0x10000U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f() (0x0U) #define gr_gpcs_pri_mmu_pm_unit_mask_r() (0x00418890U) #define gr_gpcs_pri_mmu_pm_req_mask_r() (0x00418894U) #define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 861ef45d1..80d12be07 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -73,6 +73,7 @@ #define mc_intr_ltc_pending_f() (0x2000000U) #define mc_intr_priv_ring_pending_f() (0x40000000U) #define mc_intr_pbus_pending_f() (0x10000000U) +#define mc_intr_pfb_pending_f() (0x2000U) #define mc_intr_en_r(i)\ (nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U))) #define mc_intr_en_set_r(i)\ diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index 8497b085d..b8668e8eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -101,6 +101,7 @@ #define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) #define top_device_info_entry_not_valid_v() (0x00000000U) #define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_engine_type_v() (0x00000003U) #define top_device_info_entry_data_v() (0x00000001U) #define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U) #define top_device_info_data_type_enum2_v() (0x00000000U)