gpu: nvgpu: init elcg idle filters just before gr init

- ENGINE_DELAY_BEFORE field value gets reset to 0x4 during
  nvgpu gr init path.
- Set the elcg_idle_filters just before nvgpu_gr_init_support
  so that till this point all the GR reset and hw init of GR
  has happened and we just have to do sw init of GR.
- This change helps to reatin the value of ENGINE_DELAY_BEFORE
  field to 0xA

Bug 4315638
Bug 3821730
Bug 4475968

Change-Id: Ieef38eb63e596f1f95f1c19a121fbbf5fca34ab7
Signed-off-by: Divya <dsinghatwari@nvidia.com>
(cherry picked from commit 5832c9884a079592beda7bb77c267903fda6d775)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/3015609
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/3097398
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Tested-by: Viresh Kumar <vireshk@nvidia.com>

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -969,12 +969,11 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 
 		NVGPU_INIT_TABLE_ENTRY(g->ops.mm.init_mm_support, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(g->ops.fifo.fifo_init_support, NO_FLAG),
-		NVGPU_INIT_TABLE_ENTRY(g->ops.therm.elcg_init_idle_filters,
-				       NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(&nvgpu_netlist_init_ctx_vars, NO_FLAG),
 		/* prepare portion of sw required for enable hw */
 		NVGPU_INIT_TABLE_ENTRY(&nvgpu_gr_alloc, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(&nvgpu_gr_enable_hw, NO_FLAG),
+
 		NVGPU_INIT_TABLE_ENTRY(g->ops.acr.acr_construct_execute,
 				       NVGPU_SEC_PRIVSECURITY),
 		/**
@@ -1015,6 +1014,9 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #ifdef CONFIG_NVGPU_LS_PMU
 		NVGPU_INIT_TABLE_ENTRY(g->ops.pmu.pmu_rtos_init, NO_FLAG),
 #endif
+		NVGPU_INIT_TABLE_ENTRY(g->ops.therm.elcg_init_idle_filters,
+				       NO_FLAG),
+
 		NVGPU_INIT_TABLE_ENTRY(g->ops.gr.gr_init_support, NO_FLAG),
 		/**
 		 * All units requiring ECC stats must initialize ECC counters