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nvgpu: linux: uapi: Add MIG new caps

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1) In MIG mode, 2D, 3D, I2M and ZBC classes are not supported by
GR engine. NvGpu shall expose the HWCaps through
"struct nvgpu_gpu_characteristics".

2) NvGpu shall expose the following MIG related new caps through
"struct nvgpu_gpu_characteristics".
 * mig_enabled - Flag to indicate whether MIG is enabled/disabled.
 * gpu_instance_id - GPU instaces Id.
 * gr_instance_id - graphics execution unit id.
 * gr_sys_pipe_id - Sys pipe id of GR engine.

3) populate num_ppc_per_gpc - Pixel Processing cluster per GPC

4) populate max_veid_count_per_tsg - Maximum veid count per TSG

5) populate num_sub_partition_per_fbpa - Sub partition per FBPA.

JIRA NVGPU-5762

Change-Id: I06b5bcd3f568eb0b9c78c8fc6ce155b39aaeaba5
Signed-off-by: lm <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352100
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
lm
2020-05-28 13:44:40 +05:30
committed by Alex Waterman
parent ec5ed9fd79
commit 83cb8be984
4 changed files with 75 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -258,7 +258,17 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
{NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION,
NVGPU_SUPPORT_POST_L2_COMPRESSION},
{NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE,
NVGPU_SUPPORT_MAP_ACCESS_TYPE}
NVGPU_SUPPORT_MAP_ACCESS_TYPE},
{NVGPU_GPU_FLAGS_SUPPORT_2D,
NVGPU_SUPPORT_2D},
{NVGPU_GPU_FLAGS_SUPPORT_3D,
NVGPU_SUPPORT_3D},
{NVGPU_GPU_FLAGS_SUPPORT_COMPUTE,
NVGPU_SUPPORT_COMPUTE},
{NVGPU_GPU_FLAGS_SUPPORT_I2M,
NVGPU_SUPPORT_I2M},
{NVGPU_GPU_FLAGS_SUPPORT_ZBC,
NVGPU_SUPPORT_ZBC}
};
static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
@@ -329,6 +339,10 @@ gk20a_ctrl_ioctl_gpu_characteristics(
gpu.num_tpc_per_gpc = nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config);
gpu.num_ppc_per_gpc = nvgpu_gr_config_get_pe_count_per_gpc(gr_config);
gpu.max_veid_count_per_tsg = g->fifo.max_subctx_count;
gpu.bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */
#ifdef CONFIG_NVGPU_COMPRESSION
@@ -396,6 +410,11 @@ gk20a_ctrl_ioctl_gpu_characteristics(
gpu.lts_per_ltc = nvgpu_ltc_get_slices_per_ltc(g);
gpu.cbc_cache_line_size = nvgpu_ltc_get_cacheline_size(g);
/* All nvgpu supported GPUs have 64 bit FBIO channel
* So number of Sub partition per FBPA is always 0x2.
*/
gpu.num_sub_partition_per_fbpa = 0x2;
if ((g->ops.clk.get_maxrate) && nvgpu_platform_is_silicon(g)) {
gpu.max_freq = g->ops.clk.get_maxrate(g,
CTRL_CLK_DOMAIN_GPCCLK);
@@ -416,6 +435,12 @@ gk20a_ctrl_ioctl_gpu_characteristics(
nvgpu_set_preemption_mode_flags(g, &gpu);
/* Default values for legacy mode (non MIG) */
gpu.mig_enabled = false;
gpu.gpu_instance_id = 0x0;
gpu.gr_sys_pipe_id = 0x0;
gpu.gr_instance_id = 0x0;
if (request->gpu_characteristics_buf_size > 0) {
size_t write_size = sizeof(gpu);