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nvgpu: linux: uapi: Add MIG new caps
1) In MIG mode, 2D, 3D, I2M and ZBC classes are not supported by GR engine. NvGpu shall expose the HWCaps through "struct nvgpu_gpu_characteristics". 2) NvGpu shall expose the following MIG related new caps through "struct nvgpu_gpu_characteristics". * mig_enabled - Flag to indicate whether MIG is enabled/disabled. * gpu_instance_id - GPU instaces Id. * gr_instance_id - graphics execution unit id. * gr_sys_pipe_id - Sys pipe id of GR engine. 3) populate num_ppc_per_gpc - Pixel Processing cluster per GPC 4) populate max_veid_count_per_tsg - Maximum veid count per TSG 5) populate num_sub_partition_per_fbpa - Sub partition per FBPA. JIRA NVGPU-5762 Change-Id: I06b5bcd3f568eb0b9c78c8fc6ce155b39aaeaba5 Signed-off-by: lm <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352100 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -181,6 +181,16 @@ struct nvgpu_gpu_zbc_query_table_args {
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#define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION (1ULL << 38)
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/** GMMU map access type available */
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#define NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE (1ULL << 39)
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/* Flag to indicate whether 2d operations are supported */
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#define NVGPU_GPU_FLAGS_SUPPORT_2D (1ULL << 40)
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/* Flag to indicate whether 3d graphics operations are supported */
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#define NVGPU_GPU_FLAGS_SUPPORT_3D (1ULL << 41)
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/* Flag to indicate whether compute operations are supported */
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#define NVGPU_GPU_FLAGS_SUPPORT_COMPUTE (1ULL << 42)
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/* Flag to indicate whether inline methods are supported */
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#define NVGPU_GPU_FLAGS_SUPPORT_I2M (1ULL << 43)
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/* Flag to indicate whether zbc classes are supported */
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#define NVGPU_GPU_FLAGS_SUPPORT_ZBC (1ULL << 44)
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/* SM LRF ECC is enabled */
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#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
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/* SM SHM ECC is enabled */
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@@ -303,6 +313,19 @@ struct nvgpu_gpu_characteristics {
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__u64 per_device_identifier;
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__u32 num_ppc_per_gpc;
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__u32 max_veid_count_per_tsg;
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__u32 num_sub_partition_per_fbpa;
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__u8 mig_enabled;
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__u8 reserved4[3];
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__u32 gpu_instance_id;
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__u32 gr_sys_pipe_id;
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__u32 gr_instance_id;
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__u32 reserved5;
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/* Notes:
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- This struct can be safely appended with new fields. However, always
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keep the structure size multiple of 8 and make sure that the binary
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