nvgpu: linux: uapi: Add MIG new caps

1) In MIG mode, 2D, 3D, I2M and ZBC classes are not supported by
GR engine. NvGpu shall expose the HWCaps through
"struct nvgpu_gpu_characteristics".

2) NvGpu shall expose the following MIG related new caps through
"struct nvgpu_gpu_characteristics".
 * mig_enabled - Flag to indicate whether MIG is enabled/disabled.
 * gpu_instance_id - GPU instaces Id.
 * gr_instance_id - graphics execution unit id.
 * gr_sys_pipe_id - Sys pipe id of GR engine.

3) populate num_ppc_per_gpc - Pixel Processing cluster per GPC

4) populate max_veid_count_per_tsg - Maximum veid count per TSG

5) populate num_sub_partition_per_fbpa - Sub partition per FBPA.

JIRA NVGPU-5762

Change-Id: I06b5bcd3f568eb0b9c78c8fc6ce155b39aaeaba5
Signed-off-by: lm <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352100
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
lm
2020-05-28 13:44:40 +05:30
committed by Alex Waterman
parent ec5ed9fd79
commit 83cb8be984
4 changed files with 75 additions and 2 deletions

View File

@@ -181,6 +181,16 @@ struct nvgpu_gpu_zbc_query_table_args {
#define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION (1ULL << 38)
/** GMMU map access type available */
#define NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE (1ULL << 39)
/* Flag to indicate whether 2d operations are supported */
#define NVGPU_GPU_FLAGS_SUPPORT_2D (1ULL << 40)
/* Flag to indicate whether 3d graphics operations are supported */
#define NVGPU_GPU_FLAGS_SUPPORT_3D (1ULL << 41)
/* Flag to indicate whether compute operations are supported */
#define NVGPU_GPU_FLAGS_SUPPORT_COMPUTE (1ULL << 42)
/* Flag to indicate whether inline methods are supported */
#define NVGPU_GPU_FLAGS_SUPPORT_I2M (1ULL << 43)
/* Flag to indicate whether zbc classes are supported */
#define NVGPU_GPU_FLAGS_SUPPORT_ZBC (1ULL << 44)
/* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
/* SM SHM ECC is enabled */
@@ -303,6 +313,19 @@ struct nvgpu_gpu_characteristics {
__u64 per_device_identifier;
__u32 num_ppc_per_gpc;
__u32 max_veid_count_per_tsg;
__u32 num_sub_partition_per_fbpa;
__u8 mig_enabled;
__u8 reserved4[3];
__u32 gpu_instance_id;
__u32 gr_sys_pipe_id;
__u32 gr_instance_id;
__u32 reserved5;
/* Notes:
- This struct can be safely appended with new fields. However, always
keep the structure size multiple of 8 and make sure that the binary