nvgpu: linux: uapi: Add MIG new caps

1) In MIG mode, 2D, 3D, I2M and ZBC classes are not supported by
GR engine. NvGpu shall expose the HWCaps through
"struct nvgpu_gpu_characteristics".

2) NvGpu shall expose the following MIG related new caps through
"struct nvgpu_gpu_characteristics".
 * mig_enabled - Flag to indicate whether MIG is enabled/disabled.
 * gpu_instance_id - GPU instaces Id.
 * gr_instance_id - graphics execution unit id.
 * gr_sys_pipe_id - Sys pipe id of GR engine.

3) populate num_ppc_per_gpc - Pixel Processing cluster per GPC

4) populate max_veid_count_per_tsg - Maximum veid count per TSG

5) populate num_sub_partition_per_fbpa - Sub partition per FBPA.

JIRA NVGPU-5762

Change-Id: I06b5bcd3f568eb0b9c78c8fc6ce155b39aaeaba5
Signed-off-by: lm <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352100
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -824,6 +824,16 @@ int nvgpu_init_gpu_characteristics(struct gk20a *g)
 	}
 #endif
 
+	/*
+	 * In MIG mode, 2D, 3D, I2M and ZBC classes are not supported by
+	 * GR engine. Default values for legacy mode (non MIG).
+	 */
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_2D, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_3D, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPUTE, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_I2M, true);
+	nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC, true);
+
 	return 0;
 }
 

drivers/gpu/nvgpu/include/nvgpu/enabled.h

@@ -264,10 +264,25 @@ struct gk20a;
 /** GMMU map access type support */
 #define NVGPU_SUPPORT_MAP_ACCESS_TYPE		90U
 
+/** 2d operations support */
+#define NVGPU_SUPPORT_2D			91U
+
+/** 3d graphics operations support */
+#define NVGPU_SUPPORT_3D			92U
+
+/** compute operations support */
+#define NVGPU_SUPPORT_COMPUTE			93U
+
+/** inline methods support */
+#define NVGPU_SUPPORT_I2M			94U
+
+/** zbc classes support */
+#define NVGPU_SUPPORT_ZBC			95U
+
 /*
  * Must be greater than the largest bit offset in the above list.
  */
-#define NVGPU_MAX_ENABLED_BITS			91U
+#define NVGPU_MAX_ENABLED_BITS			96U
 
 /**
  * @brief Check if the passed flag is enabled.

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -258,7 +258,17 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
 	{NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION,
 		NVGPU_SUPPORT_POST_L2_COMPRESSION},
 	{NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE,
-		NVGPU_SUPPORT_MAP_ACCESS_TYPE}
+		NVGPU_SUPPORT_MAP_ACCESS_TYPE},
+	{NVGPU_GPU_FLAGS_SUPPORT_2D,
+		NVGPU_SUPPORT_2D},
+	{NVGPU_GPU_FLAGS_SUPPORT_3D,
+		NVGPU_SUPPORT_3D},
+	{NVGPU_GPU_FLAGS_SUPPORT_COMPUTE,
+		NVGPU_SUPPORT_COMPUTE},
+	{NVGPU_GPU_FLAGS_SUPPORT_I2M,
+		NVGPU_SUPPORT_I2M},
+	{NVGPU_GPU_FLAGS_SUPPORT_ZBC,
+		NVGPU_SUPPORT_ZBC}
 };
 
 static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
@@ -329,6 +339,10 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 
 	gpu.num_tpc_per_gpc = nvgpu_gr_config_get_max_tpc_per_gpc_count(gr_config);
 
+	gpu.num_ppc_per_gpc = nvgpu_gr_config_get_pe_count_per_gpc(gr_config);
+
+	gpu.max_veid_count_per_tsg = g->fifo.max_subctx_count;
+
 	gpu.bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */
 
 #ifdef CONFIG_NVGPU_COMPRESSION
@@ -396,6 +410,11 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.lts_per_ltc = nvgpu_ltc_get_slices_per_ltc(g);
 	gpu.cbc_cache_line_size = nvgpu_ltc_get_cacheline_size(g);
 
+	/* All nvgpu supported GPUs have 64 bit FBIO channel
+	 * So number of Sub partition per FBPA is always 0x2.
+	 */
+	gpu.num_sub_partition_per_fbpa = 0x2;
+
 	if ((g->ops.clk.get_maxrate) && nvgpu_platform_is_silicon(g)) {
 		gpu.max_freq = g->ops.clk.get_maxrate(g,
 				CTRL_CLK_DOMAIN_GPCCLK);
@@ -416,6 +435,12 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 
 	nvgpu_set_preemption_mode_flags(g, &gpu);
 
+	/* Default values for legacy mode (non MIG) */
+	gpu.mig_enabled = false;
+	gpu.gpu_instance_id = 0x0;
+	gpu.gr_sys_pipe_id = 0x0;
+	gpu.gr_instance_id = 0x0;
+
 	if (request->gpu_characteristics_buf_size > 0) {
 		size_t write_size = sizeof(gpu);
 

include/uapi/linux/nvgpu.h

@@ -181,6 +181,16 @@ struct nvgpu_gpu_zbc_query_table_args {
 #define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION	(1ULL << 38)
 /** GMMU map access type available */
 #define NVGPU_GPU_FLAGS_SUPPORT_MAP_ACCESS_TYPE		(1ULL << 39)
+/* Flag to indicate whether 2d operations are supported */
+#define NVGPU_GPU_FLAGS_SUPPORT_2D			(1ULL << 40)
+/* Flag to indicate whether 3d graphics operations are supported */
+#define NVGPU_GPU_FLAGS_SUPPORT_3D			(1ULL << 41)
+/* Flag to indicate whether compute operations are supported */
+#define NVGPU_GPU_FLAGS_SUPPORT_COMPUTE			(1ULL << 42)
+/* Flag to indicate whether inline methods are supported */
+#define NVGPU_GPU_FLAGS_SUPPORT_I2M			(1ULL << 43)
+/* Flag to indicate whether zbc classes are supported */
+#define NVGPU_GPU_FLAGS_SUPPORT_ZBC			(1ULL << 44)
 /* SM LRF ECC is enabled */
 #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF	(1ULL << 60)
 /* SM SHM ECC is enabled */
@@ -303,6 +313,19 @@ struct nvgpu_gpu_characteristics {
 
 	__u64 per_device_identifier;
 
+	__u32 num_ppc_per_gpc;
+	__u32 max_veid_count_per_tsg;
+
+	__u32 num_sub_partition_per_fbpa;
+	__u8 mig_enabled;
+	__u8 reserved4[3];
+
+	__u32 gpu_instance_id;
+	__u32 gr_sys_pipe_id;
+
+	__u32 gr_instance_id;
+	__u32 reserved5;
+
 	/* Notes:
 	   - This struct can be safely appended with new fields. However, always
 	     keep the structure size multiple of 8 and make sure that the binary