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gpu: nvgpu: Add function to set falcon dmactl register

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Add nvgpu_utf_falcon_set_dmactl() function in falcon UTF
to set the falcon dmactl register with desired value
required for pmu reset test

Also, update the register size for falcon from 0x300 to 0x400
for including pmu reset register.

Rename userspace/units/facon/falcon folder to
userspace/units/facon/falcon_tests

JIRA NVGPU-2159

Change-Id: I0b22cff4699af6947e87019751aa85508dfdb185
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155124
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2019-07-17 14:11:31 +05:30
committed by mobile promotions
parent b1a11e71bf
commit 83e28e54eb
9 changed files with 18 additions and 3 deletions
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13
userspace/units/falcon/falcon_utf.c
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@@ -307,3 +307,16 @@ void nvgpu_utf_falcon_free(struct gk20a *g, u32 flcn_id)
nvgpu_falcon_sw_free(g, flcn_id);
utf_flcn->flcn = NULL;
}
void nvgpu_utf_falcon_set_dmactl(struct gk20a *g, u32 flcn_id, u32 reg_data)
{
struct utf_falcon *utf_flcn;
u32 flcn_base;
utf_flcn = &utf_falcons[flcn_id];
flcn_base = utf_flcn->flcn->flcn_base;
nvgpu_posix_io_writel_reg_space(g,
flcn_base + falcon_falcon_dmactl_r(), reg_data);
}