gpu: nvgpu: Add function to set falcon dmactl register

Add nvgpu_utf_falcon_set_dmactl() function in falcon UTF
to set the falcon dmactl register with desired value
required for pmu reset test

Also, update the register size for falcon from 0x300 to 0x400
for including pmu reset register.

Rename userspace/units/facon/falcon folder to
userspace/units/facon/falcon_tests

JIRA NVGPU-2159

Change-Id: I0b22cff4699af6947e87019751aa85508dfdb185
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155124
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2019-07-17 14:11:31 +05:30
committed by mobile promotions
parent b1a11e71bf
commit 83e28e54eb
9 changed files with 18 additions and 3 deletions

View File

@@ -65,7 +65,7 @@ endif
NV_REPOSITORY_COMPONENTS += userspace/units/list NV_REPOSITORY_COMPONENTS += userspace/units/list
NV_REPOSITORY_COMPONENTS += userspace/units/enabled NV_REPOSITORY_COMPONENTS += userspace/units/enabled
NV_REPOSITORY_COMPONENTS += userspace/units/falcon NV_REPOSITORY_COMPONENTS += userspace/units/falcon
NV_REPOSITORY_COMPONENTS += userspace/units/falcon/falcon NV_REPOSITORY_COMPONENTS += userspace/units/falcon/falcon_tests
endif endif
# Local Variables: # Local Variables:

View File

@@ -70,7 +70,7 @@ UNITS := \
$(UNIT_SRC)/list \ $(UNIT_SRC)/list \
$(UNIT_SRC)/enabled \ $(UNIT_SRC)/enabled \
$(UNIT_SRC)/falcon \ $(UNIT_SRC)/falcon \
$(UNIT_SRC)/falcon/falcon $(UNIT_SRC)/falcon/falcon_tests
ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1) ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
UNITS += $(UNIT_SRC)/fuse UNITS += $(UNIT_SRC)/fuse

View File

@@ -307,3 +307,16 @@ void nvgpu_utf_falcon_free(struct gk20a *g, u32 flcn_id)
nvgpu_falcon_sw_free(g, flcn_id); nvgpu_falcon_sw_free(g, flcn_id);
utf_flcn->flcn = NULL; utf_flcn->flcn = NULL;
} }
void nvgpu_utf_falcon_set_dmactl(struct gk20a *g, u32 flcn_id, u32 reg_data)
{
struct utf_falcon *utf_flcn;
u32 flcn_base;
utf_flcn = &utf_falcons[flcn_id];
flcn_base = utf_flcn->flcn->flcn_base;
nvgpu_posix_io_writel_reg_space(g,
flcn_base + falcon_falcon_dmactl_r(), reg_data);
}

View File

@@ -26,7 +26,7 @@
#include <nvgpu/posix/types.h> #include <nvgpu/posix/types.h>
#include <nvgpu/posix/io.h> #include <nvgpu/posix/io.h>
#define UTF_FALCON_MAX_REG_OFFSET 0x300 #define UTF_FALCON_MAX_REG_OFFSET 0x400
#define UTF_FALCON_IMEM_DMEM_SIZE (127 * 1024) #define UTF_FALCON_IMEM_DMEM_SIZE (127 * 1024)
struct gk20a; struct gk20a;
@@ -40,6 +40,7 @@ struct utf_falcon {
void nvgpu_utf_falcon_register_io(struct gk20a *g); void nvgpu_utf_falcon_register_io(struct gk20a *g);
int nvgpu_utf_falcon_init(struct unit_module *m, struct gk20a *g, u32 flcn_id); int nvgpu_utf_falcon_init(struct unit_module *m, struct gk20a *g, u32 flcn_id);
void nvgpu_utf_falcon_set_dmactl(struct gk20a *g, u32 flcn_id, u32 reg_data);
void nvgpu_utf_falcon_free(struct gk20a *g, u32 flcn_id); void nvgpu_utf_falcon_free(struct gk20a *g, u32 flcn_id);
#endif #endif

View File

@@ -23,3 +23,4 @@
nvgpu_utf_falcon_free nvgpu_utf_falcon_free
nvgpu_utf_falcon_init nvgpu_utf_falcon_init
nvgpu_utf_falcon_register_io nvgpu_utf_falcon_register_io
nvgpu_utf_falcon_set_dmactl