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gpu: nvgpu: Add function to set falcon dmactl register
Add nvgpu_utf_falcon_set_dmactl() function in falcon UTF to set the falcon dmactl register with desired value required for pmu reset test Also, update the register size for falcon from 0x300 to 0x400 for including pmu reset register. Rename userspace/units/facon/falcon folder to userspace/units/facon/falcon_tests JIRA NVGPU-2159 Change-Id: I0b22cff4699af6947e87019751aa85508dfdb185 Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2155124 Reviewed-by: Sagar Kamble <skamble@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -65,7 +65,7 @@ endif
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NV_REPOSITORY_COMPONENTS += userspace/units/list
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NV_REPOSITORY_COMPONENTS += userspace/units/list
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NV_REPOSITORY_COMPONENTS += userspace/units/enabled
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NV_REPOSITORY_COMPONENTS += userspace/units/enabled
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NV_REPOSITORY_COMPONENTS += userspace/units/falcon
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NV_REPOSITORY_COMPONENTS += userspace/units/falcon
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NV_REPOSITORY_COMPONENTS += userspace/units/falcon/falcon
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NV_REPOSITORY_COMPONENTS += userspace/units/falcon/falcon_tests
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endif
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endif
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# Local Variables:
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# Local Variables:
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@@ -70,7 +70,7 @@ UNITS := \
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$(UNIT_SRC)/list \
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$(UNIT_SRC)/list \
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$(UNIT_SRC)/enabled \
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$(UNIT_SRC)/enabled \
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$(UNIT_SRC)/falcon \
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$(UNIT_SRC)/falcon \
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$(UNIT_SRC)/falcon/falcon
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$(UNIT_SRC)/falcon/falcon_tests
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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UNITS += $(UNIT_SRC)/fuse
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UNITS += $(UNIT_SRC)/fuse
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@@ -307,3 +307,16 @@ void nvgpu_utf_falcon_free(struct gk20a *g, u32 flcn_id)
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nvgpu_falcon_sw_free(g, flcn_id);
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nvgpu_falcon_sw_free(g, flcn_id);
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utf_flcn->flcn = NULL;
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utf_flcn->flcn = NULL;
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}
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}
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void nvgpu_utf_falcon_set_dmactl(struct gk20a *g, u32 flcn_id, u32 reg_data)
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{
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struct utf_falcon *utf_flcn;
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u32 flcn_base;
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utf_flcn = &utf_falcons[flcn_id];
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flcn_base = utf_flcn->flcn->flcn_base;
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nvgpu_posix_io_writel_reg_space(g,
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flcn_base + falcon_falcon_dmactl_r(), reg_data);
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}
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@@ -26,7 +26,7 @@
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#include <nvgpu/posix/types.h>
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#include <nvgpu/posix/types.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/posix/io.h>
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#define UTF_FALCON_MAX_REG_OFFSET 0x300
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#define UTF_FALCON_MAX_REG_OFFSET 0x400
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#define UTF_FALCON_IMEM_DMEM_SIZE (127 * 1024)
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#define UTF_FALCON_IMEM_DMEM_SIZE (127 * 1024)
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struct gk20a;
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struct gk20a;
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@@ -40,6 +40,7 @@ struct utf_falcon {
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void nvgpu_utf_falcon_register_io(struct gk20a *g);
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void nvgpu_utf_falcon_register_io(struct gk20a *g);
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int nvgpu_utf_falcon_init(struct unit_module *m, struct gk20a *g, u32 flcn_id);
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int nvgpu_utf_falcon_init(struct unit_module *m, struct gk20a *g, u32 flcn_id);
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void nvgpu_utf_falcon_set_dmactl(struct gk20a *g, u32 flcn_id, u32 reg_data);
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void nvgpu_utf_falcon_free(struct gk20a *g, u32 flcn_id);
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void nvgpu_utf_falcon_free(struct gk20a *g, u32 flcn_id);
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#endif
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#endif
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@@ -23,3 +23,4 @@
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nvgpu_utf_falcon_free
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nvgpu_utf_falcon_free
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nvgpu_utf_falcon_init
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nvgpu_utf_falcon_init
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nvgpu_utf_falcon_register_io
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nvgpu_utf_falcon_register_io
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nvgpu_utf_falcon_set_dmactl
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