diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index a7e9eed8b..e636d5ae7 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -570,6 +570,25 @@ static int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
 	return err ? err : msg.ret;
 }
 
+int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev);
+	struct tegra_vgpu_cmd_msg msg;
+	struct tegra_vgpu_channel_timeslice_params *p =
+			&msg.params.channel_timeslice;
+	int err;
+
+	gk20a_dbg_fn("");
+
+	msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE;
+	msg.handle = platform->virt_handle;
+	p->handle = ch->virt_ctx;
+	p->timeslice_us = timeslice;
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	WARN_ON(err || msg.ret);
+	return err ? err : msg.ret;
+}
+
 static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g,
 		struct channel_gk20a *ch)
 {
@@ -656,4 +675,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops)
 	gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle;
 	gops->fifo.channel_set_priority = vgpu_channel_set_priority;
 	gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave;
+	gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice;
 }
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 5f697e78f..d84d0c635 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -75,7 +75,8 @@ enum {
 	TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE,
 	TEGRA_VGPU_CMD_REG_OPS,
 	TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY,
-	TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE
+	TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE,
+	TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE
 };
 
 struct tegra_vgpu_connect_params {
@@ -305,6 +306,11 @@ struct tegra_vgpu_channel_runlist_interleave_params {
 	u32 level;
 };
 
+struct tegra_vgpu_channel_timeslice_params {
+	u64 handle;
+	u32 timeslice_us;
+};
+
 struct tegra_vgpu_cmd_msg {
 	u32 cmd;
 	int ret;
@@ -334,6 +340,7 @@ struct tegra_vgpu_cmd_msg {
 		struct tegra_vgpu_reg_ops_params reg_ops;
 		struct tegra_vgpu_channel_priority_params channel_priority;
 		struct tegra_vgpu_channel_runlist_interleave_params channel_interleave;
+		struct tegra_vgpu_channel_timeslice_params channel_timeslice;
 		char padding[192];
 	} params;
 };