From 84a24c9593b798d4466df76d83a14e1898cb603f Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Tue, 19 Nov 2019 15:12:55 +0530 Subject: [PATCH] gpu: nvgpu: Remove TPC powergate from safety build - Remove non-safe TPC powergate feature from the safety build by introducing a new flag: CONFIG_NVGPU_TPC_POWERGATE - Move nvgpu_init_power_gate_gr() under same compile time flag. and move HAL function gr_gv11b_powergate_tpc() to tpc_gv11b.c - Also, remove the negative test scenario and usage of tpc_powergate from unit tests JIRA NVGPU-4149 Change-Id: If489482401e94de499e472b16b1bc091b00992e6 Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/2242323 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.shared.configs | 4 ++++ drivers/gpu/nvgpu/Makefile.sources | 5 ++++- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 19 +++++++++++------ drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c | 17 --------------- drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h | 1 - drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 5 ++++- drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 5 ++++- drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 8 ++++++-- drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.c | 16 +++++++++++++++ drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.h | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 5 ++++- drivers/gpu/nvgpu/include/nvgpu/gops_gr.h | 1 - userspace/units/init/nvgpu-init.c | 24 ---------------------- 14 files changed, 57 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 60f51435d..377a99553 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -26,6 +26,7 @@ ifeq ($(CONFIG_TEGRA_NVLINK),y) ccflags-y += -DCONFIG_NVGPU_NVLINK endif +ccflags-y += -DCONFIG_NVGPU_TPC_POWERGATE ccflags-y += -DCONFIG_NVGPU_ACR_LEGACY ccflags-y += -DCONFIG_NVGPU_ENGINE_QUEUE ccflags-y += -DCONFIG_NVGPU_FIFO_ENGINE_ACTIVITY diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index be254a6c9..825f99d20 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -126,6 +126,10 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_GRAPHICS CONFIG_NVGPU_NVLINK := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_NVLINK +# Enable tpc_powergate support for normal build. +CONFIG_NVGPU_TPC_POWERGATE := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_TPC_POWERGATE + # Enable mssnvlink0 reset control for normal build CONFIG_MSSNVLINK0_RST_CONTROL := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_MSSNVLINK0_RST_CONTROL diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 83d62735e..46ebc23a4 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -150,7 +150,6 @@ srcs += common/utils/enabled.c \ hal/power_features/cg/gv11b_gating_reglist.c \ hal/fifo/runlist_fifo_gv11b.c \ hal/fifo/userd_gk20a.c \ - hal/tpc/tpc_gv11b.c \ hal/sync/syncpt_cmdbuf_gv11b.c # Source files below are functionaly safe (FuSa) and must always be included. @@ -647,3 +646,7 @@ endif ifeq ($(CONFIG_NVGPU_NON_FUSA),1) srcs += common/power_features/power_features.c endif + +ifeq ($(CONFIG_NVGPU_TPC_POWERGATE),1) +srcs += hal/tpc/tpc_gv11b.c +endif diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 04eb86d67..4e83b2f17 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -312,6 +312,7 @@ int nvgpu_prepare_poweroff(struct gk20a *g) return ret; } +#ifdef CONFIG_NVGPU_TPC_POWERGATE static bool have_tpc_pg_lock = false; static int nvgpu_init_acquire_tpc_pg_lock(struct gk20a *g) @@ -327,6 +328,7 @@ static int nvgpu_init_release_tpc_pg_lock(struct gk20a *g) have_tpc_pg_lock = false; return 0; } +#endif static int nvgpu_init_fb_mem_unlock(struct gk20a *g) { @@ -344,6 +346,7 @@ static int nvgpu_init_fb_mem_unlock(struct gk20a *g) return 0; } +#ifdef CONFIG_NVGPU_TPC_POWERGATE static int nvgpu_init_power_gate(struct gk20a *g) { int err; @@ -357,8 +360,8 @@ static int nvgpu_init_power_gate(struct gk20a *g) g->can_tpc_powergate = false; fuse_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); - if (g->ops.tpc.tpc_powergate != NULL) { - err = g->ops.tpc.tpc_powergate(g, fuse_status); + if (g->ops.tpc.init_tpc_powergate != NULL) { + err = g->ops.tpc.init_tpc_powergate(g, fuse_status); if (err != 0) { return err; } @@ -367,11 +370,10 @@ static int nvgpu_init_power_gate(struct gk20a *g) return 0; } -#ifdef CONFIG_NVGPU_DEBUGGER static int nvgpu_init_power_gate_gr(struct gk20a *g) { - if (g->can_tpc_powergate && (g->ops.gr.powergate_tpc != NULL)) { - g->ops.gr.powergate_tpc(g); + if (g->can_tpc_powergate && (g->ops.tpc.tpc_gr_pg != NULL)) { + g->ops.tpc.tpc_gr_pg(g); } return 0; } @@ -560,9 +562,9 @@ int nvgpu_finalize_poweron(struct gk20a *g) NVGPU_INIT_TABLE_ENTRY(g->ops.fifo.fifo_init_support, NO_FLAG), NVGPU_INIT_TABLE_ENTRY(g->ops.therm.elcg_init_idle_filters, NO_FLAG), +#ifdef CONFIG_NVGPU_TPC_POWERGATE NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_power_gate, NO_FLAG), NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_acquire_tpc_pg_lock, NO_FLAG), -#ifdef CONFIG_NVGPU_DEBUGGER NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_power_gate_gr, NO_FLAG), #endif /* prepare portion of sw required for enable hw */ @@ -585,8 +587,11 @@ int nvgpu_finalize_poweron(struct gk20a *g) */ NVGPU_INIT_TABLE_ENTRY(g->ops.ecc.ecc_finalize_support, NO_FLAG), +#ifdef CONFIG_NVGPU_TPC_POWERGATE NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_release_tpc_pg_lock, NO_FLAG), +#endif + #ifdef CONFIG_NVGPU_LS_PMU NVGPU_INIT_TABLE_ENTRY(g->ops.pmu.pmu_pstate_sw_setup, NVGPU_PMU_PSTATE), @@ -647,6 +652,7 @@ int nvgpu_finalize_poweron(struct gk20a *g) return err; done: +#ifdef CONFIG_NVGPU_TPC_POWERGATE if (have_tpc_pg_lock) { int release_err = nvgpu_init_release_tpc_pg_lock(g); @@ -654,6 +660,7 @@ done: nvgpu_err(g, "failed to release tpc_gp_lock"); } } +#endif nvgpu_falcons_sw_free(g); return err; diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c index 58bf671e4..4db2b3364 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c @@ -62,23 +62,6 @@ #define PRI_BROADCAST_FLAGS_SMPC BIT32(17) -void gr_gv11b_powergate_tpc(struct gk20a *g) -{ - u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); - - if (tpc_pg_status == g->tpc_pg_mask) { - return; - } - - g->ops.fuse.fuse_ctrl_opt_tpc_gpc(g, 0, g->tpc_pg_mask); - - do { - tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); - } while (tpc_pg_status != g->tpc_pg_mask); - - return; -} - void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) { struct nvgpu_gr *gr = g->gr; diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h index 3b68db139..7dc92ce79 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.h @@ -94,7 +94,6 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, u32 addr, u32 *priv_addr_table, u32 *num_registers); -void gr_gv11b_powergate_tpc(struct gk20a *g); bool gv11b_gr_esr_bpt_pending_events(u32 global_esr, enum nvgpu_event_id_type bpt_event); #endif /* CONFIG_NVGPU_DEBUGGER */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 29b8bf086..048fe142c 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -1110,9 +1110,12 @@ static const struct gpu_ops gm20b_ops = { .get_max_lts_per_ltc = gm20b_top_get_max_lts_per_ltc, .get_num_ltcs = gm20b_top_get_num_ltcs, }, +#ifdef CONFIG_NVGPU_TPC_POWERGATE .tpc = { - .tpc_powergate = NULL, + .init_tpc_powergate = NULL, + .tpc_gr_pg = NULL, }, +#endif .chip_init_gpu_characteristics = nvgpu_init_gpu_characteristics, .get_litter_value = gm20b_get_litter_value, }; diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 9f85358ac..2e0f2517b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -1218,9 +1218,12 @@ static const struct gpu_ops gp10b_ops = { .get_max_lts_per_ltc = gm20b_top_get_max_lts_per_ltc, .get_num_ltcs = gm20b_top_get_num_ltcs, }, +#ifdef CONFIG_NVGPU_TPC_POWERGATE .tpc = { - .tpc_powergate = NULL, + .init_tpc_powergate = NULL, + .tpc_gr_pg = NULL, }, +#endif .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, .get_litter_value = gp10b_get_litter_value, }; diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index f10cdbd71..356d5b9c6 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -291,7 +291,6 @@ static const struct gpu_ops gv11b_ops = { .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, .is_tpc_addr = gr_gm20b_is_tpc_addr, .get_tpc_num = gr_gm20b_get_tpc_num, - .powergate_tpc = gr_gv11b_powergate_tpc, .dump_gr_regs = gr_gv11b_dump_gr_status_regs, .update_pc_sampling = gr_gm20b_update_pc_sampling, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, @@ -1432,9 +1431,12 @@ static const struct gpu_ops gv11b_ops = { .get_num_ltcs = gm20b_top_get_num_ltcs, .get_num_lce = gv11b_top_get_num_lce, }, +#ifdef CONFIG_NVGPU_TPC_POWERGATE .tpc = { - .tpc_powergate = gv11b_tpc_powergate, + .init_tpc_powergate = gv11b_tpc_powergate, + .tpc_gr_pg = gv11b_gr_pg_tpc, }, +#endif .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -1491,7 +1493,9 @@ int gv11b_init_hal(struct gk20a *g) gops->falcon = gv11b_ops.falcon; gops->priv_ring = gv11b_ops.priv_ring; gops->fuse = gv11b_ops.fuse; +#ifdef CONFIG_NVGPU_TPC_POWERGATE gops->tpc = gv11b_ops.tpc; +#endif #ifdef CONFIG_NVGPU_CLK_ARB gops->clk_arb = gv11b_ops.clk_arb; #endif diff --git a/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.c b/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.c index 975d2f766..ad7d313f7 100644 --- a/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.c @@ -69,3 +69,19 @@ int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status) return err; } +void gv11b_gr_pg_tpc(struct gk20a *g) +{ + u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); + + if (tpc_pg_status == g->tpc_pg_mask) { + return; + } + + g->ops.fuse.fuse_ctrl_opt_tpc_gpc(g, 0, g->tpc_pg_mask); + + do { + tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); + } while (tpc_pg_status != g->tpc_pg_mask); + + return; +} diff --git a/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.h b/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.h index 15b04ae2c..68974a3e0 100644 --- a/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.h +++ b/drivers/gpu/nvgpu/hal/tpc/tpc_gv11b.h @@ -28,6 +28,7 @@ struct gk20a; int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status); +void gv11b_gr_pg_tpc(struct gk20a *g); #endif /* NVGPU_TPC_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 5250a21d5..16414c6c8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -615,9 +615,12 @@ struct gpu_ops { void (*falcon_setup_boot_config)(struct gk20a *g); int (*gsp_reset)(struct gk20a *g); } gsp; +#ifdef CONFIG_NVGPU_TPC_POWERGATE struct { - int (*tpc_powergate)(struct gk20a *g, u32 fuse_status); + int (*init_tpc_powergate)(struct gk20a *g, u32 fuse_status); + void (*tpc_gr_pg)(struct gk20a *g); } tpc; +#endif void (*semaphore_wakeup)(struct gk20a *g, bool post_events); }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h index 23fdbe67f..0555c60b6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h @@ -1028,7 +1028,6 @@ struct gops_gr { u32 *gpc_num, u32 *tpc_num); u32 (*get_tpc_num)(struct gk20a *g, u32 addr); u32 (*get_egpc_base)(struct gk20a *g); - void (*powergate_tpc)(struct gk20a *g); int (*update_smpc_ctxsw_mode)(struct gk20a *g, struct nvgpu_channel *c, bool enable); diff --git a/userspace/units/init/nvgpu-init.c b/userspace/units/init/nvgpu-init.c index 301e7b22f..aa1e984e5 100644 --- a/userspace/units/init/nvgpu-init.c +++ b/userspace/units/init/nvgpu-init.c @@ -115,18 +115,6 @@ static int falcon_sw_init(struct gk20a *g, u32 falcon_id) return 0; } -/* generic for passing in a u32 */ -static int return_success_u32_param(struct gk20a *g, u32 dummy) -{ - return 0; -} - -/* generic for passing in a u32 and returning int */ -static int return_failure_u32_param(struct gk20a *g, u32 dummy) -{ - return -1; -} - /* generic for passing in a u32 and returning u32 */ static u32 return_u32_u32_param(struct gk20a *g, u32 dummy) { @@ -524,7 +512,6 @@ static void set_poweron_funcs_success(struct gk20a *g) g->ops.falcon.falcon_sw_init = falcon_sw_init; falcon_fail_on_id = U32_MAX; /* don't fail */ g->ops.fuse.fuse_status_opt_tpc_gpc = return_u32_u32_param; - g->ops.tpc.tpc_powergate = return_success_u32_param; g->ops.falcon.falcon_sw_free = no_return_u32_param; /* used in support functions */ @@ -580,16 +567,6 @@ int test_poweron(struct unit_module *m, struct gk20a *g, void *args) "nvgpu_finalize_poweron errantly returned success\n"); } falcon_fail_on_id = U32_MAX; /* stop failing */ - - g->ops.tpc.tpc_powergate = return_failure_u32_param; - nvgpu_set_power_state(g, NVGPU_STATE_POWERED_OFF); - err = nvgpu_finalize_poweron(g); - if (err == 0) { - unit_return_fail(m, - "nvgpu_finalize_poweron errantly returned success\n"); - } - g->ops.tpc.tpc_powergate = return_success_u32_param; - /* test the case of already being powered on */ nvgpu_set_power_state(g, NVGPU_STATE_POWERED_ON); err = nvgpu_finalize_poweron(g); @@ -616,7 +593,6 @@ int test_poweron_branches(struct unit_module *m, struct gk20a *g, void *args) g->ops.clk.init_clk_support = NULL; g->ops.fb.init_fbpa = NULL; g->ops.fb.mem_unlock = NULL; - g->ops.tpc.tpc_powergate = NULL; g->ops.therm.elcg_init_idle_filters = NULL; g->ops.ecc.ecc_init_support = NULL; g->ops.channel.resume_all_serviceable_ch = NULL;