diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index c5c2e50e8..8882f24f1 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -826,7 +826,8 @@ void nvgpu_tsg_unbind_channel_ctx_reload_check(struct nvgpu_tsg *tsg,
 		nvgpu_list_for_each_entry(temp_ch, &tsg->ch_list,
 				nvgpu_channel, ch_entry) {
 			if (temp_ch->chid != ch->chid) {
-				g->ops.channel.force_ctx_reload(temp_ch);
+				g->ops.channel.force_ctx_reload(g,
+					temp_ch->runlist->id, temp_ch->chid);
 				break;
 			}
 		}
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h
index 1283c12ae..55c5c8612 100644
--- a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b.h
@@ -39,6 +39,6 @@ void ga10b_channel_read_state(struct gk20a *g, u32 runlist_id, u32 chid,
 					struct nvgpu_channel_hw_state *state);
 void ga10b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
 		bool eng, bool pbdma);
-void ga10b_channel_force_ctx_reload(struct nvgpu_channel *ch);
+void ga10b_channel_force_ctx_reload(struct gk20a *g, u32 runlist_id, u32 chid);
 
 #endif /* FIFO_CHANNEL_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c
index 4478ddda3..ac3b161ae 100644
--- a/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_ga10b_fusa.c
@@ -273,14 +273,11 @@ void ga10b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
 
 }
 
-void ga10b_channel_force_ctx_reload(struct nvgpu_channel *ch)
+void ga10b_channel_force_ctx_reload(struct gk20a *g, u32 runlist_id, u32 chid)
 {
-	struct gk20a *g = ch->g;
-	struct nvgpu_runlist *runlist = NULL;
+	struct nvgpu_runlist *runlist = g->fifo.runlists[runlist_id];
 
-	runlist = ch->runlist;
-
-	nvgpu_chram_bar0_writel(g, runlist, runlist_chram_channel_r(ch->chid),
+	nvgpu_chram_bar0_writel(g, runlist, runlist_chram_channel_r(chid),
 		runlist_chram_channel_update_f(
 			runlist_chram_channel_update_force_ctx_reload_v()));
 }
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_gm20b.h b/drivers/gpu/nvgpu/hal/fifo/channel_gm20b.h
index 62d6d3b54..e1fe0a088 100644
--- a/drivers/gpu/nvgpu/hal/fifo/channel_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,7 +29,7 @@ struct nvgpu_channel;
 struct gk20a;
 
 void gm20b_channel_bind(struct nvgpu_channel *c);
-void gm20b_channel_force_ctx_reload(struct nvgpu_channel *ch);
+void gm20b_channel_force_ctx_reload(struct gk20a *g, u32 runlist_id, u32 chid);
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 u32 gm20b_channel_count(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c
index 211dfbede..dd3cd2932 100644
--- a/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -58,11 +58,11 @@ void gm20b_channel_bind(struct nvgpu_channel *c)
 	nvgpu_atomic_set(&c->bound, 1);
 }
 
-void gm20b_channel_force_ctx_reload(struct nvgpu_channel *ch)
+void gm20b_channel_force_ctx_reload(struct gk20a *g, u32 runlist_id, u32 chid)
 {
-	struct gk20a *g = ch->g;
-	u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid));
+	u32 reg = nvgpu_readl(g, ccsr_channel_r(chid));
 
-	nvgpu_writel(g, ccsr_channel_r(ch->chid),
+	(void)runlist_id;
+	nvgpu_writel(g, ccsr_channel_r(chid),
 		reg | ccsr_channel_force_ctx_reload_true_f());
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h
index cdd34fb49..bb5ca5422 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/channel.h
@@ -141,7 +141,7 @@ struct gops_channel {
 	void (*unbind)(struct nvgpu_channel *ch);
 	void (*read_state)(struct gk20a *g, u32 runlist_id, u32 chid,
 			struct nvgpu_channel_hw_state *state);
-	void (*force_ctx_reload)(struct nvgpu_channel *ch);
+	void (*force_ctx_reload)(struct gk20a *g, u32 runlist_id, u32 chid);
 	void (*abort_clean_up)(struct nvgpu_channel *ch);
 	void (*reset_faulted)(struct gk20a *g, struct nvgpu_channel *ch,
 			bool eng, bool pbdma);
diff --git a/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c b/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c
index bc4a1e474..3bdc1cf59 100644
--- a/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c
+++ b/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -112,13 +112,14 @@ int test_gm20b_channel_force_ctx_reload(struct unit_module *m,
 	unit_assert(ch, goto done);
 
 	nvgpu_writel(g, ccsr_channel_r(ch->chid), 0);
-	gm20b_channel_force_ctx_reload(ch);
+	gm20b_channel_force_ctx_reload(g, ch->runlist->id, ch->chid);
 	unit_assert((nvgpu_readl(g, ccsr_channel_r(ch->chid)) &
 		ccsr_channel_force_ctx_reload_true_f()) != 0, goto done);
 
 	chid = ch->chid;
 	ch->chid = U32_MAX;
-	err = EXPECT_BUG(gm20b_channel_force_ctx_reload(ch));
+	err = EXPECT_BUG(gm20b_channel_force_ctx_reload(g,
+			ch->runlist->id, ch->chid));
 	ch->chid = chid;
 	unit_assert(err != 0, goto done);
 
diff --git a/userspace/units/fifo/tsg/nvgpu-tsg.c b/userspace/units/fifo/tsg/nvgpu-tsg.c
index 633689b6f..065ac2f60 100644
--- a/userspace/units/fifo/tsg/nvgpu-tsg.c
+++ b/userspace/units/fifo/tsg/nvgpu-tsg.c
@@ -1002,10 +1002,11 @@ static const char *f_unbind_channel_check_ctx_reload[] = {
 	"chid_match",
 };
 
-static void stub_channel_force_ctx_reload(struct nvgpu_channel *ch)
+static void stub_channel_force_ctx_reload(struct gk20a *g,
+		u32 runlist_id, u32 chid)
 {
 	stub[0].name = __func__;
-	stub[0].chid = ch->chid;
+	stub[0].chid = chid;
 }
 
 int test_tsg_unbind_channel_check_ctx_reload(struct unit_module *m,