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gpu: nvgpu: add read_ptimer to gops
Move all places that read ptimer to use the callback. It's for add vgpu implementation of read ptimer. Bug 1395833 Change-Id: Ia339f2f08d75ca4969a443fffc9a61cff1d3d2b7 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159587 (cherry picked from commit a01f804684f875c9cffc31eb2c1038f2f29ec66f) Reviewed-on: http://git-master/r/1158449 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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committed by
Terje Bergstrom
parent
03164b0f4a
commit
86225cb04e
@@ -626,50 +626,17 @@ static int nvgpu_gpu_get_gpu_time(
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struct gk20a *g,
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struct nvgpu_gpu_get_gpu_time_args *args)
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{
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int err = 0;
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const unsigned int max_iterations = 3;
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unsigned int i = 0;
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u32 gpu_timestamp_hi_prev = 0;
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u64 time;
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int err;
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err = gk20a_busy(g->dev);
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if (err)
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return err;
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/* Note. The GPU nanosecond timer consists of two 32-bit
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* registers (high & low). To detect a possible low register
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* wrap-around between the reads, we need to read the high
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* register before and after low. The wraparound happens
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* approximately once per 4 secs. */
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err = g->ops.read_ptimer(g, &time);
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if (!err)
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args->gpu_timestamp = time;
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/* get initial gpu_timestamp_hi value */
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gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r());
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for (i = 0; i < max_iterations; ++i) {
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u32 gpu_timestamp_hi = 0;
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u32 gpu_timestamp_lo = 0;
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rmb(); /* maintain read order */
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gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r());
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rmb(); /* maintain read order */
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gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r());
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if (gpu_timestamp_hi == gpu_timestamp_hi_prev) {
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args->gpu_timestamp =
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(((u64)gpu_timestamp_hi) << 32) |
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gpu_timestamp_lo;
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goto clean_up;
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}
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/* wrap-around detected, retry */
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gpu_timestamp_hi_prev = gpu_timestamp_hi;
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}
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/* too many iterations, bail out */
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gk20a_err(dev_from_gk20a(g),
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"Failed to read GPU time. Clock or bus unstable?\n");
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err = -EBUSY;
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clean_up:
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gk20a_idle(g->dev);
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return err;
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}
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