From 8664b3be6c92cd7fd26705aeae1c97c175e1f5ec Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Fri, 5 Apr 2019 09:43:09 +0530 Subject: [PATCH] gpu: nvgpu: make ctx structs private Add ctx_priv.h header for structs which are used within nvgpu_gr_ctx. APIs are added to manage fields of nvgpu_gr_ctx. JIRA NVGPU-3060 Change-Id: I396fbbb5199e354c62772e901e3bbf61d135f3b1 Signed-off-by: Nitin Kumbhar Reviewed-on: https://git-master.nvidia.com/r/2090398 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/tsg.c | 7 +- drivers/gpu/nvgpu/common/gr/ctx.c | 123 ++++++++++++++++++ drivers/gpu/nvgpu/common/gr/ctx_priv.h | 82 ++++++++++++ drivers/gpu/nvgpu/common/gr/fecs_trace.c | 2 +- drivers/gpu/nvgpu/common/gr/gr_setup.c | 15 ++- drivers/gpu/nvgpu/common/gr/obj_ctx.c | 28 ++-- drivers/gpu/nvgpu/common/gr/subctx.c | 17 +-- drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c | 2 + drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c | 79 ++++++----- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 12 +- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 2 +- drivers/gpu/nvgpu/gp106/gr_gp106.c | 9 +- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 31 +++-- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 5 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c | 8 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c | 5 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_tu104.c | 8 +- drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h | 116 +++++++++-------- drivers/gpu/nvgpu/os/linux/debug_fifo.c | 4 +- drivers/gpu/nvgpu/os/linux/ioctl_channel.c | 4 +- drivers/gpu/nvgpu/os/linux/sched.c | 4 +- 22 files changed, 403 insertions(+), 161 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/gr/ctx_priv.h diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 0a5a38c36..9c1072282 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -686,7 +686,7 @@ int nvgpu_tsg_open_common(struct gk20a *g, struct tsg_gk20a *tsg, pid_t pid) tsg->timeslice_scale = 0U; tsg->runlist_id = FIFO_INVAL_TSG_ID; tsg->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; - tsg->gr_ctx = nvgpu_kzalloc(g, sizeof(*tsg->gr_ctx)); + tsg->gr_ctx = nvgpu_alloc_gr_ctx_struct(g); if (tsg->gr_ctx == NULL) { err = -ENOMEM; goto clean_up; @@ -742,7 +742,7 @@ void nvgpu_tsg_release_common(struct gk20a *g, struct tsg_gk20a *tsg) g->ops.tsg.release(tsg); } - nvgpu_kfree(g, tsg->gr_ctx); + nvgpu_free_gr_ctx_struct(g, tsg->gr_ctx); tsg->gr_ctx = NULL; if (g->ops.tsg.deinit_eng_method_buffers != NULL) { @@ -773,7 +773,8 @@ void nvgpu_tsg_release(struct nvgpu_ref *ref) struct gk20a *g = tsg->g; struct gk20a_event_id_data *event_id_data, *event_id_data_temp; - if (tsg->gr_ctx != NULL && nvgpu_mem_is_valid(&tsg->gr_ctx->mem) && + if (tsg->gr_ctx != NULL && nvgpu_mem_is_valid( + nvgpu_gr_ctx_get_ctx_mem(tsg->gr_ctx)) && tsg->vm != NULL) { g->ops.gr.setup.free_gr_ctx(g, tsg->vm, tsg->gr_ctx); } diff --git a/drivers/gpu/nvgpu/common/gr/ctx.c b/drivers/gpu/nvgpu/common/gr/ctx.c index aa4e44483..d24599159 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx.c +++ b/drivers/gpu/nvgpu/common/gr/ctx.c @@ -28,6 +28,8 @@ #include #include +#include "common/gr/ctx_priv.h" + static void nvgpu_gr_ctx_unmap_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer, @@ -52,6 +54,16 @@ void nvgpu_gr_ctx_set_size(struct nvgpu_gr_ctx_desc *gr_ctx_desc, gr_ctx_desc->size[index] = size; } +struct nvgpu_gr_ctx *nvgpu_alloc_gr_ctx_struct(struct gk20a *g) +{ + return nvgpu_kzalloc(g, sizeof(struct nvgpu_gr_ctx)); +} + +void nvgpu_free_gr_ctx_struct(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx) +{ + nvgpu_kfree(g, gr_ctx); +} + int nvgpu_gr_ctx_alloc(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_ctx_desc *gr_ctx_desc, @@ -464,6 +476,72 @@ u64 nvgpu_gr_ctx_get_global_ctx_va(struct nvgpu_gr_ctx *gr_ctx, return gr_ctx->global_ctx_buffer_va[index]; } +struct nvgpu_mem *nvgpu_gr_ctx_get_patch_ctx_mem(struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->patch_ctx.mem; +} + +void nvgpu_gr_ctx_set_patch_ctx_data_count(struct nvgpu_gr_ctx *gr_ctx, + u32 data_count) +{ + gr_ctx->patch_ctx.data_count = data_count; +} + +struct nvgpu_mem *nvgpu_gr_ctx_get_pm_ctx_mem(struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->pm_ctx.mem; +} + +void nvgpu_gr_ctx_set_pm_ctx_pm_mode(struct nvgpu_gr_ctx *gr_ctx, u32 pm_mode) +{ + gr_ctx->pm_ctx.pm_mode = pm_mode; +} + +u32 nvgpu_gr_ctx_get_pm_ctx_pm_mode(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->pm_ctx.pm_mode; +} + +u64 nvgpu_gr_ctx_get_zcull_ctx_va(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->zcull_ctx.gpu_va; +} + +struct nvgpu_mem *nvgpu_gr_ctx_get_preempt_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->preempt_ctxsw_buffer; +} + +struct nvgpu_mem *nvgpu_gr_ctx_get_spill_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->spill_ctxsw_buffer; +} + +struct nvgpu_mem *nvgpu_gr_ctx_get_betacb_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->betacb_ctxsw_buffer; +} + +struct nvgpu_mem *nvgpu_gr_ctx_get_pagepool_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->pagepool_ctxsw_buffer; +} + +struct nvgpu_mem *nvgpu_gr_ctx_get_gfxp_rtvcb_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->gfxp_rtvcb_ctxsw_buffer; +} + +struct nvgpu_mem *nvgpu_gr_ctx_get_ctx_mem(struct nvgpu_gr_ctx *gr_ctx) +{ + return &gr_ctx->mem; +} + /* load saved fresh copy of gloden image into channel gr_ctx */ int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, @@ -772,12 +850,22 @@ void nvgpu_gr_ctx_init_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, gr_ctx->compute_preempt_mode = compute_preempt_mode; } +u32 nvgpu_gr_ctx_get_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->compute_preempt_mode; +} + void nvgpu_gr_ctx_init_graphics_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, u32 graphics_preempt_mode) { gr_ctx->graphics_preempt_mode = graphics_preempt_mode; } +u32 nvgpu_gr_ctx_get_graphics_preemption_mode(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->graphics_preempt_mode; +} + bool nvgpu_gr_ctx_check_valid_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, u32 graphics_preempt_mode, u32 compute_preempt_mode) { @@ -836,3 +924,38 @@ void nvgpu_gr_ctx_set_preemption_buffer_va(struct gk20a *g, } } +void nvgpu_gr_ctx_set_tsgid(struct nvgpu_gr_ctx *gr_ctx, u32 tsgid) +{ + gr_ctx->tsgid = tsgid; +} + +u32 nvgpu_gr_ctx_get_tsgid(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->tsgid; +} + +bool nvgpu_gr_ctx_get_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->cilp_preempt_pending; +} + +void nvgpu_gr_ctx_set_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx, + bool cilp_preempt_pending) +{ + gr_ctx->cilp_preempt_pending = cilp_preempt_pending; +} + +u32 nvgpu_gr_ctx_read_ctx_id(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->ctx_id; +} + +void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost) +{ + gr_ctx->boosted_ctx = boost; +} + +bool nvgpu_gr_ctx_get_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx) +{ + return gr_ctx->boosted_ctx; +} diff --git a/drivers/gpu/nvgpu/common/gr/ctx_priv.h b/drivers/gpu/nvgpu/common/gr/ctx_priv.h new file mode 100644 index 000000000..328e5b893 --- /dev/null +++ b/drivers/gpu/nvgpu/common/gr/ctx_priv.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_GR_CTX_PRIV_H +#define NVGPU_GR_CTX_PRIV_H + +struct nvgpu_mem; +enum nvgpu_gr_global_ctx_index; + +struct patch_desc { + struct nvgpu_mem mem; + u32 data_count; +}; + +struct zcull_ctx_desc { + u64 gpu_va; + u32 ctx_sw_mode; +}; + +struct pm_ctx_desc { + struct nvgpu_mem mem; + u64 gpu_va; + u32 pm_mode; +}; + +struct nvgpu_gr_ctx_desc { + u32 size[NVGPU_GR_CTX_COUNT]; +}; + +struct nvgpu_gr_ctx { + u32 ctx_id; + bool ctx_id_valid; + struct nvgpu_mem mem; + + struct nvgpu_mem preempt_ctxsw_buffer; + struct nvgpu_mem spill_ctxsw_buffer; + struct nvgpu_mem betacb_ctxsw_buffer; + struct nvgpu_mem pagepool_ctxsw_buffer; + struct nvgpu_mem gfxp_rtvcb_ctxsw_buffer; + + struct patch_desc patch_ctx; + struct zcull_ctx_desc zcull_ctx; + struct pm_ctx_desc pm_ctx; + + u32 graphics_preempt_mode; + u32 compute_preempt_mode; + + bool golden_img_loaded; + bool cilp_preempt_pending; + bool boosted_ctx; + +#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION + u64 virt_ctx; +#endif + + u64 global_ctx_buffer_va[NVGPU_GR_CTX_VA_COUNT]; + enum nvgpu_gr_global_ctx_index global_ctx_buffer_index[NVGPU_GR_CTX_VA_COUNT]; + bool global_ctx_buffer_mapped; + + u32 tsgid; +}; + +#endif /* NVGPU_GR_CTX_PRIV_H */ diff --git a/drivers/gpu/nvgpu/common/gr/fecs_trace.c b/drivers/gpu/nvgpu/common/gr/fecs_trace.c index 28501dacc..51f1cdae7 100644 --- a/drivers/gpu/nvgpu/common/gr/fecs_trace.c +++ b/drivers/gpu/nvgpu/common/gr/fecs_trace.c @@ -594,7 +594,7 @@ int nvgpu_gr_fecs_trace_bind_channel(struct gk20a *g, return -ENOMEM; } - mem = &gr_ctx->mem; + mem = nvgpu_gr_ctx_get_ctx_mem(gr_ctx); nvgpu_log(g, gpu_dbg_ctxsw, "addr=%llx count=%d", addr, GK20A_FECS_TRACE_NUM_RECORDS); diff --git a/drivers/gpu/nvgpu/common/gr/gr_setup.c b/drivers/gpu/nvgpu/common/gr/gr_setup.c index cb315e532..c847075f6 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_setup.c +++ b/drivers/gpu/nvgpu/common/gr/gr_setup.c @@ -124,7 +124,7 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, } } - if (!nvgpu_mem_is_valid(&gr_ctx->mem)) { + if (!nvgpu_mem_is_valid(nvgpu_gr_ctx_get_ctx_mem(gr_ctx))) { tsg->vm = c->vm; nvgpu_vm_get(tsg->vm); @@ -140,11 +140,11 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, goto out; } - gr_ctx->tsgid = tsg->tsgid; + nvgpu_gr_ctx_set_tsgid(gr_ctx, tsg->tsgid); } else { /* commit gr ctx buffer */ nvgpu_gr_obj_ctx_commit_inst(g, &c->inst_block, gr_ctx, - c->subctx, gr_ctx->mem.gpu_va); + c->subctx, nvgpu_gr_ctx_get_ctx_mem(gr_ctx)->gpu_va); } #ifdef CONFIG_GK20A_CTXSW_TRACE @@ -181,7 +181,8 @@ void nvgpu_gr_setup_free_gr_ctx(struct gk20a *g, if (gr_ctx != NULL) { if ((g->ops.gr.ctxsw_prog.dump_ctxsw_stats != NULL) && g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close) { - g->ops.gr.ctxsw_prog.dump_ctxsw_stats(g, &gr_ctx->mem); + g->ops.gr.ctxsw_prog.dump_ctxsw_stats(g, + nvgpu_gr_ctx_get_ctx_mem(gr_ctx)); } nvgpu_gr_ctx_free(g, gr_ctx, g->gr.global_ctx_buffer, vm); @@ -214,12 +215,14 @@ int nvgpu_gr_setup_set_preemption_mode(struct channel_gk20a *ch, /* skip setting anything if both modes are already set */ if ((graphics_preempt_mode != 0U) && - (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) { + (graphics_preempt_mode == + nvgpu_gr_ctx_get_graphics_preemption_mode(gr_ctx))) { graphics_preempt_mode = 0; } if ((compute_preempt_mode != 0U) && - (compute_preempt_mode == gr_ctx->compute_preempt_mode)) { + (compute_preempt_mode == + nvgpu_gr_ctx_get_compute_preemption_mode(gr_ctx))) { compute_preempt_mode = 0; } diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c index b3aad6c7f..f8875d049 100644 --- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c +++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c @@ -207,6 +207,7 @@ void nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(struct gk20a *g, int err; u64 addr; u32 size; + struct nvgpu_mem *mem; nvgpu_log_fn(g, " "); @@ -216,7 +217,8 @@ void nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(struct gk20a *g, return; } - if (!nvgpu_mem_is_valid(&gr_ctx->preempt_ctxsw_buffer)) { + if (!nvgpu_mem_is_valid( + nvgpu_gr_ctx_get_preempt_ctxsw_buffer(gr_ctx))) { return; } @@ -233,22 +235,24 @@ void nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode(struct gk20a *g, goto out; } - addr = gr_ctx->betacb_ctxsw_buffer.gpu_va; + addr = nvgpu_gr_ctx_get_betacb_ctxsw_buffer(gr_ctx)->gpu_va; g->ops.gr.init.commit_global_attrib_cb(g, gr_ctx, nvgpu_gr_config_get_tpc_count(g->gr.config), nvgpu_gr_config_get_max_tpc_count(g->gr.config), addr, true); - addr = gr_ctx->pagepool_ctxsw_buffer.gpu_va; - nvgpu_assert(gr_ctx->pagepool_ctxsw_buffer.size <= U32_MAX); - size = (u32)gr_ctx->pagepool_ctxsw_buffer.size; + mem = nvgpu_gr_ctx_get_pagepool_ctxsw_buffer(gr_ctx); + addr = mem->gpu_va; + nvgpu_assert(mem->size <= U32_MAX); + size = (u32)mem->size; g->ops.gr.init.commit_global_pagepool(g, gr_ctx, addr, size, true, false); - addr = gr_ctx->spill_ctxsw_buffer.gpu_va; - nvgpu_assert(gr_ctx->spill_ctxsw_buffer.size <= U32_MAX); - size = (u32)gr_ctx->spill_ctxsw_buffer.size; + mem = nvgpu_gr_ctx_get_spill_ctxsw_buffer(gr_ctx); + addr = mem->gpu_va; + nvgpu_assert(mem->size <= U32_MAX); + size = (u32)mem->size; g->ops.gr.init.commit_ctxsw_spill(g, gr_ctx, addr, size, true); @@ -392,7 +396,7 @@ int nvgpu_gr_obj_ctx_alloc_golden_ctx_image(struct gk20a *g, nvgpu_log_fn(g, " "); - gr_mem = &gr_ctx->mem; + gr_mem = nvgpu_gr_ctx_get_ctx_mem(gr_ctx); /* * golden ctx is global to all channels. Although only the first @@ -570,8 +574,8 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g, } /* allocate patch buffer */ - if (!nvgpu_mem_is_valid(&gr_ctx->patch_ctx.mem)) { - gr_ctx->patch_ctx.data_count = 0; + if (!nvgpu_mem_is_valid(nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx))) { + nvgpu_gr_ctx_set_patch_ctx_data_count(gr_ctx, 0); nvgpu_gr_ctx_set_size(g->gr.gr_ctx_desc, NVGPU_GR_CTX_PATCH_CTX, @@ -606,7 +610,7 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g, /* commit gr ctx buffer */ nvgpu_gr_obj_ctx_commit_inst(g, inst_block, gr_ctx, subctx, - gr_ctx->mem.gpu_va); + nvgpu_gr_ctx_get_ctx_mem(gr_ctx)->gpu_va); /* init golden image, ELPG enabled after this is done */ err = nvgpu_gr_obj_ctx_alloc_golden_ctx_image(g, golden_image, gr_ctx, diff --git a/drivers/gpu/nvgpu/common/gr/subctx.c b/drivers/gpu/nvgpu/common/gr/subctx.c index 0c10ce436..9a3b33104 100644 --- a/drivers/gpu/nvgpu/common/gr/subctx.c +++ b/drivers/gpu/nvgpu/common/gr/subctx.c @@ -99,12 +99,13 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g, NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA)); g->ops.gr.ctxsw_prog.set_patch_addr(g, ctxheader, - gr_ctx->patch_ctx.mem.gpu_va); + nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx)->gpu_va); g->ops.gr.ctxsw_prog.set_pm_ptr(g, ctxheader, - gr_ctx->pm_ctx.mem.gpu_va); + nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->gpu_va); + g->ops.gr.ctxsw_prog.set_zcull_ptr(g, ctxheader, - gr_ctx->zcull_ctx.gpu_va); + nvgpu_gr_ctx_get_zcull_ctx_va(gr_ctx)); g->ops.gr.ctxsw_prog.set_context_buffer_ptr(g, ctxheader, gpu_va); @@ -118,33 +119,33 @@ void nvgpu_gr_subctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx nvgpu_log_fn(g, " "); g->ops.gr.ctxsw_prog.set_zcull_ptr(g, &subctx->ctx_header, - gr_ctx->zcull_ctx.gpu_va); + nvgpu_gr_ctx_get_zcull_ctx_va(gr_ctx)); } void nvgpu_gr_subctx_set_hwpm_mode(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx) { g->ops.gr.ctxsw_prog.set_pm_ptr(g, &subctx->ctx_header, - gr_ctx->pm_ctx.gpu_va); + nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->gpu_va); } void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx) { g->ops.gr.ctxsw_prog.set_patch_addr(g, &subctx->ctx_header, - gr_ctx->patch_ctx.mem.gpu_va); + nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx)->gpu_va); } void nvgpu_gr_subctx_set_preemption_buffer_va(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx) { g->ops.gr.ctxsw_prog.set_full_preemption_ptr(g, &subctx->ctx_header, - gr_ctx->preempt_ctxsw_buffer.gpu_va); + nvgpu_gr_ctx_get_preempt_ctxsw_buffer(gr_ctx)->gpu_va); if (g->ops.gr.ctxsw_prog.set_full_preemption_ptr_veid0 != NULL) { g->ops.gr.ctxsw_prog.set_full_preemption_ptr_veid0(g, &subctx->ctx_header, - gr_ctx->preempt_ctxsw_buffer.gpu_va); + nvgpu_gr_ctx_get_preempt_ctxsw_buffer(gr_ctx)->gpu_va); } } diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c index 73beab88a..a55525c78 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/ctx_vgpu.c @@ -32,6 +32,8 @@ #include #include +#include "common/gr/ctx_priv.h" + #include "ctx_vgpu.h" #include "common/vgpu/ivc/comm_vgpu.h" diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c index 577e4e59b..c9353eb9a 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c @@ -244,10 +244,10 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) gr_ctx = tsg->gr_ctx; - if (!nvgpu_mem_is_valid(&gr_ctx->mem)) { + if (!nvgpu_mem_is_valid(nvgpu_gr_ctx_get_ctx_mem(gr_ctx))) { tsg->vm = c->vm; nvgpu_vm_get(tsg->vm); - gr_ctx->tsgid = tsg->tsgid; + nvgpu_gr_ctx_set_tsgid(gr_ctx, tsg->tsgid); err = vgpu_gr_alloc_gr_ctx(g, gr_ctx, c->vm); if (err) { nvgpu_err(g, @@ -286,7 +286,8 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) } /* commit gr ctx buffer */ - err = vgpu_gr_commit_inst(c, gr_ctx->mem.gpu_va); + err = vgpu_gr_commit_inst(c, + nvgpu_gr_ctx_get_ctx_mem(gr_ctx)->gpu_va); if (err) { nvgpu_err(g, "fail to commit gr ctx buffer"); goto out; @@ -301,7 +302,8 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) } } else { /* commit gr ctx buffer */ - err = vgpu_gr_commit_inst(c, gr_ctx->mem.gpu_va); + err = vgpu_gr_commit_inst(c, + nvgpu_gr_ctx_get_ctx_mem(gr_ctx)->gpu_va); if (err) { nvgpu_err(g, "fail to commit gr ctx buffer"); goto out; @@ -318,7 +320,8 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) } /* PM ctxt switch is off by default */ - gr_ctx->pm_ctx.pm_mode = g->ops.gr.ctxsw_prog.hw_get_pm_mode_no_ctxsw(); + nvgpu_gr_ctx_set_pm_ctx_pm_mode(gr_ctx, + g->ops.gr.ctxsw_prog.hw_get_pm_mode_no_ctxsw()); nvgpu_log_fn(g, "done"); return 0; @@ -868,8 +871,7 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, struct channel_gk20a *ch, u64 gpu_va, u32 mode) { struct tsg_gk20a *tsg; - struct nvgpu_gr_ctx *ch_ctx; - struct pm_ctx_desc *pm_ctx; + struct nvgpu_gr_ctx *gr_ctx; struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode; int err; @@ -886,8 +888,7 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, return -EINVAL; } - ch_ctx = tsg->gr_ctx; - pm_ctx = &ch_ctx->pm_ctx; + gr_ctx = tsg->gr_ctx; if (mode == NVGPU_GR_CTX_HWPM_CTXSW_MODE_CTXSW) { /* @@ -895,20 +896,20 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, * will return an error due to using the same GPU VA twice. */ - if (pm_ctx->pm_mode == + if (nvgpu_gr_ctx_get_pm_ctx_pm_mode(gr_ctx) == g->ops.gr.ctxsw_prog.hw_get_pm_mode_ctxsw()) { return 0; } p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW; } else if (mode == NVGPU_GR_CTX_HWPM_CTXSW_MODE_NO_CTXSW) { - if (pm_ctx->pm_mode == + if (nvgpu_gr_ctx_get_pm_ctx_pm_mode(gr_ctx) == g->ops.gr.ctxsw_prog.hw_get_pm_mode_no_ctxsw()) { return 0; } p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW; } else if ((mode == NVGPU_GR_CTX_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW) && g->ops.gr.ctxsw_prog.hw_get_pm_mode_stream_out_ctxsw()) { - if (pm_ctx->pm_mode == + if (nvgpu_gr_ctx_get_pm_ctx_pm_mode(gr_ctx) == g->ops.gr.ctxsw_prog.hw_get_pm_mode_stream_out_ctxsw()) { return 0; } @@ -926,27 +927,28 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, "failed to allocate pm ctxt buffer"); return err; } - pm_ctx->mem.size = g->gr.ctx_vars.pm_ctxsw_image_size; + nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->size = + g->gr.ctx_vars.pm_ctxsw_image_size; } msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE; msg.handle = vgpu_get_handle(g); p->handle = ch->virt_ctx; - p->gpu_va = pm_ctx->mem.gpu_va; + p->gpu_va = nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->gpu_va; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); err = err ? err : msg.ret; if (!err) { if (mode == NVGPU_GR_CTX_HWPM_CTXSW_MODE_CTXSW) { - pm_ctx->pm_mode = - g->ops.gr.ctxsw_prog.hw_get_pm_mode_ctxsw(); + nvgpu_gr_ctx_set_pm_ctx_pm_mode(gr_ctx, + g->ops.gr.ctxsw_prog.hw_get_pm_mode_ctxsw()); } else if (mode == NVGPU_GR_CTX_HWPM_CTXSW_MODE_NO_CTXSW) { - pm_ctx->pm_mode = - g->ops.gr.ctxsw_prog.hw_get_pm_mode_no_ctxsw(); + nvgpu_gr_ctx_set_pm_ctx_pm_mode(gr_ctx, + g->ops.gr.ctxsw_prog.hw_get_pm_mode_no_ctxsw()); } else { - pm_ctx->pm_mode = - g->ops.gr.ctxsw_prog.hw_get_pm_mode_stream_out_ctxsw(); + nvgpu_gr_ctx_set_pm_ctx_pm_mode(gr_ctx, + g->ops.gr.ctxsw_prog.hw_get_pm_mode_stream_out_ctxsw()); } } @@ -1335,30 +1337,32 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g, goto fail; } - desc = &gr_ctx->preempt_ctxsw_buffer; + desc = nvgpu_gr_ctx_get_preempt_ctxsw_buffer(gr_ctx); p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; - desc = &gr_ctx->spill_ctxsw_buffer; + desc = nvgpu_gr_ctx_get_spill_ctxsw_buffer(gr_ctx); p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; - desc = &gr_ctx->pagepool_ctxsw_buffer; + desc = nvgpu_gr_ctx_get_pagepool_ctxsw_buffer(gr_ctx); p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; - desc = &gr_ctx->betacb_ctxsw_buffer; + desc = nvgpu_gr_ctx_get_betacb_ctxsw_buffer(gr_ctx); p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; - gr_ctx->graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; + nvgpu_gr_ctx_init_graphics_preemption_mode(gr_ctx, + NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP); p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; break; } case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI: - gr_ctx->graphics_preempt_mode = graphics_preempt_mode; + nvgpu_gr_ctx_init_graphics_preemption_mode(gr_ctx, + graphics_preempt_mode); break; default: @@ -1368,19 +1372,19 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g, if (g->ops.gr.is_valid_compute_class(g, class)) { switch (compute_preempt_mode) { case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: - gr_ctx->compute_preempt_mode = - NVGPU_PREEMPTION_MODE_COMPUTE_WFI; + nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx, + NVGPU_PREEMPTION_MODE_COMPUTE_WFI); p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI; break; case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: - gr_ctx->compute_preempt_mode = - NVGPU_PREEMPTION_MODE_COMPUTE_CTA; + nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx, + NVGPU_PREEMPTION_MODE_COMPUTE_CTA); p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; break; case NVGPU_PREEMPTION_MODE_COMPUTE_CILP: - gr_ctx->compute_preempt_mode = - NVGPU_PREEMPTION_MODE_COMPUTE_CILP; + nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx, + NVGPU_PREEMPTION_MODE_COMPUTE_CILP); p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; break; @@ -1389,10 +1393,11 @@ static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g, } } - if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { + if ((nvgpu_gr_ctx_get_graphics_preemption_mode(gr_ctx) != 0U) || + (nvgpu_gr_ctx_get_compute_preemption_mode(gr_ctx) != 0U)) { msg.cmd = TEGRA_VGPU_CMD_BIND_GR_CTXSW_BUFFERS; msg.handle = vgpu_get_handle(g); - p->tsg_id = gr_ctx->tsgid; + p->tsg_id = nvgpu_gr_ctx_get_tsgid(gr_ctx); err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); if (err || msg.ret) { err = -ENOMEM; @@ -1433,12 +1438,14 @@ int vgpu_gr_set_preemption_mode(struct channel_gk20a *ch, /* skip setting anything if both modes are already set */ if (graphics_preempt_mode && - (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) { + (graphics_preempt_mode == + nvgpu_gr_ctx_get_graphics_preemption_mode(gr_ctx))) { graphics_preempt_mode = 0; } if (compute_preempt_mode && - (compute_preempt_mode == gr_ctx->compute_preempt_mode)) { + (compute_preempt_mode == + nvgpu_gr_ctx_get_compute_preemption_mode(gr_ctx))) { compute_preempt_mode = 0; } diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0caee5cb6..3b0dc3e9b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2331,7 +2331,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, if (!gr_ctx_ready) { gr_ctx_ready = true; } - current_mem = &gr_ctx->mem; + current_mem = nvgpu_gr_ctx_get_ctx_mem(gr_ctx); } else { err = gr_gk20a_get_pm_ctx_buffer_offsets(g, ctx_ops[i].offset, @@ -2348,7 +2348,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, } if (!pm_ctx_ready) { /* Make sure ctx buffer was initialized */ - if (!nvgpu_mem_is_valid(&gr_ctx->pm_ctx.mem)) { + if (!nvgpu_mem_is_valid(nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx))) { nvgpu_err(g, "Invalid ctx buffer"); err = -EINVAL; @@ -2356,7 +2356,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, } pm_ctx_ready = true; } - current_mem = &gr_ctx->pm_ctx.mem; + current_mem = nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx); } /* if this is a quad access, setup for special access*/ @@ -2370,7 +2370,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, /* sanity check gr ctxt offsets, * don't write outside, worst case */ - if ((current_mem == &gr_ctx->mem) && + if ((current_mem == nvgpu_gr_ctx_get_ctx_mem(gr_ctx)) && (offsets[j] >= g->gr.ctx_vars.golden_image_size)) { continue; } @@ -2395,7 +2395,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, offsets[j] + 4U, v); } - if (current_mem == &gr_ctx->mem) { + if (current_mem == nvgpu_gr_ctx_get_ctx_mem(gr_ctx)) { /* check to see if we need to add a special WAR for some of the SMPC perf regs */ gr_gk20a_ctx_patch_smpc(g, ch, @@ -2430,7 +2430,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, nvgpu_kfree(g, offsets); } - if (gr_ctx->patch_ctx.mem.cpu_va != NULL) { + if (nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx)->cpu_va != NULL) { nvgpu_gr_ctx_patch_write_end(g, gr_ctx, gr_ctx_ready); } diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 7ce432284..dd9ff7822 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -57,6 +57,7 @@ struct nvgpu_gr_global_ctx_local_golden_image; struct nvgpu_gr_zbc; struct nvgpu_gr_hwpm_map; struct nvgpu_gr_isr_data; +struct nvgpu_gr_ctx_desc; enum ctxsw_addr_type; diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 1475da7f1..9bae026d5 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -545,7 +545,7 @@ int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, } gr_ctx = tsg->gr_ctx; - mem = &gr_ctx->mem; + mem = nvgpu_gr_ctx_get_ctx_mem(gr_ctx); if (!nvgpu_mem_is_valid(mem) || c->vpr) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index 545b4be4b..23b906719 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -195,12 +195,14 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, goto fail; } - gr_ctx->graphics_preempt_mode = graphics_preempt_mode; + nvgpu_gr_ctx_init_graphics_preemption_mode(gr_ctx, + graphics_preempt_mode); break; } case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI: - gr_ctx->graphics_preempt_mode = graphics_preempt_mode; + nvgpu_gr_ctx_init_graphics_preemption_mode(gr_ctx, + graphics_preempt_mode); break; default: @@ -212,7 +214,8 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: case NVGPU_PREEMPTION_MODE_COMPUTE_CILP: - gr_ctx->compute_preempt_mode = compute_preempt_mode; + nvgpu_gr_ctx_init_compute_preemption_mode(gr_ctx, + compute_preempt_mode); break; default: break; diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 558a88847..8dc33d563 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -717,7 +717,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, gr_ctx = tsg->gr_ctx; - if (gr_ctx->cilp_preempt_pending) { + if (nvgpu_gr_ctx_get_cilp_preempt_pending(gr_ctx)) { nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP is already pending for chid %d", fault_ch->chid); @@ -725,7 +725,8 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, } nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: ctx id is 0x%x", gr_ctx->ctx_id); + "CILP: ctx id is 0x%x", + nvgpu_gr_ctx_read_ctx_id(gr_ctx)); /* send ucode method to set ctxsw interrupt */ ret = g->ops.gr.falcon.ctrl_ctxsw(g, @@ -750,7 +751,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, } /* set cilp_preempt_pending = true and record the channel */ - gr_ctx->cilp_preempt_pending = true; + nvgpu_gr_ctx_set_cilp_preempt_pending(gr_ctx, true); g->gr.cilp_preempt_pending_chid = fault_ch->chid; g->ops.tsg.post_event_id(tsg, NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED); @@ -775,14 +776,14 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, /* The ucode is self-clearing, so all we need to do here is to clear cilp_preempt_pending. */ - if (!gr_ctx->cilp_preempt_pending) { + if (!nvgpu_gr_ctx_get_cilp_preempt_pending(gr_ctx)) { nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP is already cleared for chid %d\n", fault_ch->chid); return 0; } - gr_ctx->cilp_preempt_pending = false; + nvgpu_gr_ctx_set_cilp_preempt_pending(gr_ctx, false); g->gr.cilp_preempt_pending_chid = FIFO_INVAL_CHANNEL_ID; return 0; @@ -810,8 +811,9 @@ int gr_gp10b_pre_process_sm_exception(struct gk20a *g, return -EINVAL; } - cilp_enabled = (tsg->gr_ctx->compute_preempt_mode == - NVGPU_PREEMPTION_MODE_COMPUTE_CILP); + cilp_enabled = + (nvgpu_gr_ctx_get_compute_preemption_mode(tsg->gr_ctx) == + NVGPU_PREEMPTION_MODE_COMPUTE_CILP); } nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n", @@ -930,7 +932,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, u32 *__chid) gr_ctx = tsg->gr_ctx; - if (gr_ctx->cilp_preempt_pending) { + if (nvgpu_gr_ctx_get_cilp_preempt_pending(gr_ctx)) { *__chid = chid; ret = 0; } @@ -1053,7 +1055,8 @@ bool gr_gp10b_suspend_context(struct channel_gk20a *ch, if (gk20a_is_channel_ctx_resident(ch)) { g->ops.gr.suspend_all_sms(g, 0, false); - if (gr_ctx->compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP) { + if (nvgpu_gr_ctx_get_compute_preemption_mode(gr_ctx) == + NVGPU_PREEMPTION_MODE_COMPUTE_CILP) { err = gr_gp10b_set_cilp_preempt_pending(g, ch); if (err != 0) { nvgpu_err(g, "unable to set CILP preempt pending"); @@ -1140,7 +1143,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g), NVGPU_TIMER_CPU_TIMER); do { - if (!gr_ctx->cilp_preempt_pending) { + if (!nvgpu_gr_ctx_get_cilp_preempt_pending(gr_ctx)) { break; } @@ -1149,7 +1152,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, } while (nvgpu_timeout_expired(&timeout) == 0); /* If cilp is still pending at this point, timeout */ - if (gr_ctx->cilp_preempt_pending) { + if (nvgpu_gr_ctx_get_cilp_preempt_pending(gr_ctx)) { err = -ETIMEDOUT; } } @@ -1175,8 +1178,8 @@ int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, } gr_ctx = tsg->gr_ctx; - gr_ctx->boosted_ctx = boost; - mem = &gr_ctx->mem; + nvgpu_gr_ctx_set_boosted_ctx(gr_ctx, boost); + mem = nvgpu_gr_ctx_get_ctx_mem(gr_ctx); err = gk20a_disable_channel_tsg(g, ch); if (err != 0) { @@ -1191,7 +1194,7 @@ int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, if (g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies != NULL) { g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies(g, - mem, gr_ctx->boosted_ctx); + mem, nvgpu_gr_ctx_get_boosted_ctx(gr_ctx)); } else { err = -ENOSYS; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 93c4e2fc0..41a9390b9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1465,8 +1465,9 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, return -EINVAL; } - cilp_enabled = (tsg->gr_ctx->compute_preempt_mode == - NVGPU_PREEMPTION_MODE_COMPUTE_CILP); + cilp_enabled = + (nvgpu_gr_ctx_get_compute_preemption_mode(tsg->gr_ctx) == + NVGPU_PREEMPTION_MODE_COMPUTE_CILP); } nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c index ba0077c8d..e70ad10f7 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c @@ -391,8 +391,9 @@ void gp10b_gr_init_commit_global_attrib_cb(struct gk20a *g, (u64_hi32(addr) << (32U - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); - if (gr_ctx->preempt_ctxsw_buffer.gpu_va != 0ULL) { - attrBufferSize = U32(gr_ctx->betacb_ctxsw_buffer.size); + if (nvgpu_gr_ctx_get_preempt_ctxsw_buffer(gr_ctx)->gpu_va != 0ULL) { + attrBufferSize = + U32(nvgpu_gr_ctx_get_betacb_ctxsw_buffer(gr_ctx)->size); } else { attrBufferSize = g->ops.gr.init.get_global_attr_cb_size(g, tpc_count, max_tpc); @@ -435,7 +436,8 @@ void gp10b_gr_init_commit_global_cb_manager(struct gk20a *g, nvgpu_log_fn(g, " "); - if (gr_ctx->graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) { + if (nvgpu_gr_ctx_get_graphics_preemption_mode(gr_ctx) + == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) { attrib_size_in_chunk = g->ops.gr.init.get_attrib_cb_gfxp_size(g); cb_attrib_cache_size_init = diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c index c76d5f8f0..ea1e9b616 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c @@ -842,8 +842,9 @@ void gv11b_gr_init_commit_global_attrib_cb(struct gk20a *g, (u64_hi32(addr) << (32U - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); - if (gr_ctx->preempt_ctxsw_buffer.gpu_va != 0ULL) { - attrBufferSize = U32(gr_ctx->betacb_ctxsw_buffer.size); + if (nvgpu_gr_ctx_get_preempt_ctxsw_buffer(gr_ctx)->gpu_va != 0ULL) { + attrBufferSize = + U32(nvgpu_gr_ctx_get_betacb_ctxsw_buffer(gr_ctx)->size); } else { attrBufferSize = g->ops.gr.init.get_global_attr_cb_size(g, tpc_count, max_tpc); diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_tu104.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_tu104.c index bebef1374..0abd01417 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_tu104.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_tu104.c @@ -73,6 +73,7 @@ void tu104_gr_init_commit_gfxp_rtv_cb(struct gk20a *g, u64 addr_hi; u32 rtv_cb_size; u32 gfxp_addr_size; + struct nvgpu_mem *buf_mem; nvgpu_log_fn(g, " "); @@ -83,9 +84,10 @@ void tu104_gr_init_commit_gfxp_rtv_cb(struct gk20a *g, gfxp_addr_size = gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f(); /* GFXP RTV circular buffer */ - addr_lo = (u64)(u64_lo32(gr_ctx->gfxp_rtvcb_ctxsw_buffer.gpu_va) >> - gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f()); - addr_hi = (u64)(u64_hi32(gr_ctx->gfxp_rtvcb_ctxsw_buffer.gpu_va)); + buf_mem = nvgpu_gr_ctx_get_gfxp_rtvcb_ctxsw_buffer(gr_ctx); + addr_lo = (u64)(u64_lo32(buf_mem->gpu_va) >> + gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f()); + addr_hi = (u64)(buf_mem->gpu_va); addr = addr_lo | (addr_hi << (32U - gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f())); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h index e85f5e8f5..691a7470e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h @@ -45,8 +45,13 @@ struct gk20a; struct vm_gk20a; +struct nvgpu_gr_ctx; struct nvgpu_gr_global_ctx_buffer_desc; struct nvgpu_gr_global_ctx_local_golden_image; +struct patch_desc; +struct zcull_ctx_desc; +struct pm_ctx_desc; +struct nvgpu_gr_ctx_desc; enum nvgpu_gr_ctx_index { NVGPU_GR_CTX_CTX = 0, @@ -73,16 +78,6 @@ enum nvgpu_gr_ctx_global_ctx_va { NVGPU_GR_CTX_VA_COUNT = 6 }; -struct patch_desc { - struct nvgpu_mem mem; - u32 data_count; -}; - -struct zcull_ctx_desc { - u64 gpu_va; - u32 ctx_sw_mode; -}; - /* PM Context Switch Mode */ /*This mode says that the pms are not to be context switched. */ #define NVGPU_GR_CTX_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000U) @@ -91,51 +86,7 @@ struct zcull_ctx_desc { /* This mode says that the pms in Mode-E (stream out) are to be context switched. */ #define NVGPU_GR_CTX_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW (0x00000002U) -struct pm_ctx_desc { - struct nvgpu_mem mem; - u64 gpu_va; - u32 pm_mode; -}; - -struct nvgpu_gr_ctx_desc { - u32 size[NVGPU_GR_CTX_COUNT]; -}; - -struct nvgpu_gr_ctx { - u32 ctx_id; - bool ctx_id_valid; - struct nvgpu_mem mem; - - struct nvgpu_mem preempt_ctxsw_buffer; - struct nvgpu_mem spill_ctxsw_buffer; - struct nvgpu_mem betacb_ctxsw_buffer; - struct nvgpu_mem pagepool_ctxsw_buffer; - struct nvgpu_mem gfxp_rtvcb_ctxsw_buffer; - - struct patch_desc patch_ctx; - struct zcull_ctx_desc zcull_ctx; - struct pm_ctx_desc pm_ctx; - - u32 graphics_preempt_mode; - u32 compute_preempt_mode; - - bool golden_img_loaded; - bool cilp_preempt_pending; - bool boosted_ctx; - -#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION - u64 virt_ctx; -#endif - - u64 global_ctx_buffer_va[NVGPU_GR_CTX_VA_COUNT]; - enum nvgpu_gr_global_ctx_index global_ctx_buffer_index[NVGPU_GR_CTX_VA_COUNT]; - bool global_ctx_buffer_mapped; - - u32 tsgid; -}; - -struct nvgpu_gr_ctx_desc * -nvgpu_gr_ctx_desc_alloc(struct gk20a *g); +struct nvgpu_gr_ctx_desc *nvgpu_gr_ctx_desc_alloc(struct gk20a *g); void nvgpu_gr_ctx_desc_free(struct gk20a *g, struct nvgpu_gr_ctx_desc *desc); @@ -178,9 +129,36 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer, struct vm_gk20a *vm, bool vpr); + u64 nvgpu_gr_ctx_get_global_ctx_va(struct nvgpu_gr_ctx *gr_ctx, enum nvgpu_gr_ctx_global_ctx_va index); +struct nvgpu_mem *nvgpu_gr_ctx_get_spill_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx); + +struct nvgpu_mem *nvgpu_gr_ctx_get_betacb_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx); + +struct nvgpu_mem *nvgpu_gr_ctx_get_pagepool_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx); + +struct nvgpu_mem *nvgpu_gr_ctx_get_preempt_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx); + +struct nvgpu_mem *nvgpu_gr_ctx_get_gfxp_rtvcb_ctxsw_buffer( + struct nvgpu_gr_ctx *gr_ctx); + +struct nvgpu_mem *nvgpu_gr_ctx_get_patch_ctx_mem(struct nvgpu_gr_ctx *gr_ctx); + +void nvgpu_gr_ctx_set_patch_ctx_data_count(struct nvgpu_gr_ctx *gr_ctx, + u32 data_count); + +struct nvgpu_mem *nvgpu_gr_ctx_get_pm_ctx_mem(struct nvgpu_gr_ctx *gr_ctx); + +u64 nvgpu_gr_ctx_get_zcull_ctx_va(struct nvgpu_gr_ctx *gr_ctx); + +struct nvgpu_mem *nvgpu_gr_ctx_get_ctx_mem(struct nvgpu_gr_ctx *gr_ctx); + int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_global_ctx_local_golden_image *local_golden_image, @@ -217,8 +195,12 @@ int nvgpu_gr_ctx_set_hwpm_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, void nvgpu_gr_ctx_init_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, u32 compute_preempt_mode); +u32 nvgpu_gr_ctx_get_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx); + void nvgpu_gr_ctx_init_graphics_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, u32 graphics_preempt_mode); +u32 nvgpu_gr_ctx_get_graphics_preemption_mode(struct nvgpu_gr_ctx *gr_ctx); + bool nvgpu_gr_ctx_check_valid_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, u32 graphics_preempt_mode, u32 compute_preempt_mode); void nvgpu_gr_ctx_set_preemption_modes(struct gk20a *g, @@ -226,4 +208,28 @@ void nvgpu_gr_ctx_set_preemption_modes(struct gk20a *g, void nvgpu_gr_ctx_set_preemption_buffer_va(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx); +struct nvgpu_gr_ctx *nvgpu_alloc_gr_ctx_struct(struct gk20a *g); + +void nvgpu_free_gr_ctx_struct(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx); + +void nvgpu_gr_ctx_set_tsgid(struct nvgpu_gr_ctx *gr_ctx, u32 tsgid); + +u32 nvgpu_gr_ctx_get_tsgid(struct nvgpu_gr_ctx *gr_ctx); + +void nvgpu_gr_ctx_set_pm_ctx_pm_mode(struct nvgpu_gr_ctx *gr_ctx, u32 pm_mode); + +u32 nvgpu_gr_ctx_get_pm_ctx_pm_mode(struct nvgpu_gr_ctx *gr_ctx); + +bool nvgpu_gr_ctx_get_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx); + +void nvgpu_gr_ctx_set_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx, + bool cilp_preempt_pending); + +u32 nvgpu_gr_ctx_read_ctx_id(struct nvgpu_gr_ctx *gr_ctx); + +void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost); + +bool nvgpu_gr_ctx_get_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx); + + #endif /* NVGPU_INCLUDE_GR_CTX_H */ diff --git a/drivers/gpu/nvgpu/os/linux/debug_fifo.c b/drivers/gpu/nvgpu/os/linux/debug_fifo.c index 593ea405c..2f0de0031 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_fifo.c +++ b/drivers/gpu/nvgpu/os/linux/debug_fifo.c @@ -95,8 +95,8 @@ static int gk20a_fifo_sched_debugfs_seq_show( tsg->timeslice_us, ch->ctxsw_timeout_max_ms, tsg->interleave_level, - tsg->gr_ctx->graphics_preempt_mode, - tsg->gr_ctx->compute_preempt_mode); + nvgpu_gr_ctx_get_graphics_preemption_mode(tsg->gr_ctx), + nvgpu_gr_ctx_get_compute_preemption_mode(tsg->gr_ctx)); gk20a_channel_put(ch); } return 0; diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c index e64c75fe6..f79b0be57 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c @@ -91,9 +91,9 @@ static void gk20a_channel_trace_sched_param( ch->ctxsw_timeout_max_ms, gk20a_fifo_interleave_level_name(tsg->interleave_level), gr_gk20a_graphics_preempt_mode_name( - tsg->gr_ctx->graphics_preempt_mode), + nvgpu_gr_ctx_get_graphics_preemption_mode(tsg->gr_ctx)), gr_gk20a_compute_preempt_mode_name( - tsg->gr_ctx->compute_preempt_mode)); + nvgpu_gr_ctx_get_compute_preemption_mode(tsg->gr_ctx))); } /* diff --git a/drivers/gpu/nvgpu/os/linux/sched.c b/drivers/gpu/nvgpu/os/linux/sched.c index 9cc917f6c..184811812 100644 --- a/drivers/gpu/nvgpu/os/linux/sched.c +++ b/drivers/gpu/nvgpu/os/linux/sched.c @@ -210,9 +210,9 @@ static int gk20a_sched_dev_ioctl_get_params(struct gk20a_sched_ctrl *sched, arg->timeslice = tsg->timeslice_us; arg->graphics_preempt_mode = - tsg->gr_ctx->graphics_preempt_mode; + nvgpu_gr_ctx_get_graphics_preemption_mode(tsg->gr_ctx); arg->compute_preempt_mode = - tsg->gr_ctx->compute_preempt_mode; + nvgpu_gr_ctx_get_compute_preemption_mode(tsg->gr_ctx); nvgpu_ref_put(&tsg->refcount, nvgpu_ioctl_tsg_release);