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gpu: nvgpu: Remove bare channel scheduling

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Remove scheduling IOCTL implementations for bare channels. Also
removes code that constructs bare channels in runlist.

Bug 1842197

Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627326
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2017-12-27 13:04:17 -08:00
committed by mobile promotions
parent 14fa8207e2
commit 86691b59c6
19 changed files with 22 additions and 257 deletions
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55
drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
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@@ -604,8 +604,8 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g)
return 0;
}
static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g,
u32 tsgid,
int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
u32 id,
u32 runlist_id,
u32 new_level)
{
@@ -618,62 +618,13 @@ static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g,
msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE;
msg.handle = vgpu_get_handle(g);
p->tsg_id = tsgid;
p->tsg_id = id;
p->level = new_level;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
WARN_ON(err || msg.ret);
return err ? err : msg.ret;
}
int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
u32 id,
bool is_tsg,
u32 runlist_id,
u32 new_level)
{
struct tegra_vgpu_cmd_msg msg;
struct tegra_vgpu_channel_runlist_interleave_params *p =
&msg.params.channel_interleave;
struct channel_gk20a *ch;
int err;
gk20a_dbg_fn("");
if (is_tsg)
return vgpu_fifo_tsg_set_runlist_interleave(g, id,
runlist_id, new_level);
ch = &g->fifo.channel[id];
msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE;
msg.handle = vgpu_get_handle(ch->g);
p->handle = ch->virt_ctx;
p->level = new_level;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
WARN_ON(err || msg.ret);
return err ? err : msg.ret;
}
int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
{
struct tegra_vgpu_cmd_msg msg;
struct tegra_vgpu_channel_timeslice_params *p =
&msg.params.channel_timeslice;
int err;
gk20a_dbg_fn("");
msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE;
msg.handle = vgpu_get_handle(ch->g);
p->handle = ch->virt_ctx;
p->timeslice_us = timeslice;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
WARN_ON(err);
if (!err)
ch->timeslice_us = p->timeslice_us;
return err;
}
int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
u32 err_code, bool verbose)
{