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gpu: nvgpu: Move sm_arch to nvgpu_gpu_params
Move sm_arch_* fields to nvgpu_gpu_params to make them available from common code without accessing Linux specific GPU characteristics. JIRA NVGPU-259 Change-Id: Ieffb2ddde81b27af53dfedb9fe3972d20757cc35 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593686 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -226,6 +226,10 @@ gk20a_ctrl_ioctl_gpu_characteristics(
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g->ops.mm.get_mmu_levels(g, pgpu->big_page_size)[0].lo_bit[0];
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g->ops.mm.get_mmu_levels(g, pgpu->big_page_size)[0].lo_bit[0];
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pgpu->available_big_page_sizes = nvgpu_mm_get_available_big_page_sizes(g);
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pgpu->available_big_page_sizes = nvgpu_mm_get_available_big_page_sizes(g);
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pgpu->sm_arch_sm_version = g->params.sm_arch_sm_version;
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pgpu->sm_arch_spa_version = g->params.sm_arch_spa_version;
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pgpu->sm_arch_warp_count = g->params.sm_arch_warp_count;
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if (request->gpu_characteristics_buf_size > 0) {
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if (request->gpu_characteristics_buf_size > 0) {
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size_t write_size = sizeof(*pgpu);
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size_t write_size = sizeof(*pgpu);
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@@ -1075,6 +1075,11 @@ struct nvgpu_gpu_params {
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u32 gpu_impl;
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u32 gpu_impl;
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/* GPU revision ID */
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/* GPU revision ID */
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u32 gpu_rev;
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u32 gpu_rev;
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/* sm version */
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u32 sm_arch_sm_version;
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/* sm instruction set */
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u32 sm_arch_spa_version;
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u32 sm_arch_warp_count;
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};
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};
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struct gk20a {
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struct gk20a {
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@@ -841,11 +841,11 @@ void gr_gm20b_detect_sm_arch(struct gk20a *g)
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{
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{
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u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r());
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u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r());
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g->gpu_characteristics.sm_arch_spa_version =
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g->params.sm_arch_spa_version =
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gr_gpc0_tpc0_sm_arch_spa_version_v(v);
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gr_gpc0_tpc0_sm_arch_spa_version_v(v);
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g->gpu_characteristics.sm_arch_sm_version =
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g->params.sm_arch_sm_version =
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gr_gpc0_tpc0_sm_arch_sm_version_v(v);
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gr_gpc0_tpc0_sm_arch_sm_version_v(v);
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g->gpu_characteristics.sm_arch_warp_count =
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g->params.sm_arch_warp_count =
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gr_gpc0_tpc0_sm_arch_warp_count_v(v);
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gr_gpc0_tpc0_sm_arch_warp_count_v(v);
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}
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}
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@@ -1154,7 +1154,7 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
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/* for maxwell & kepler */
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/* for maxwell & kepler */
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u32 numSmPerTpc = 1;
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u32 numSmPerTpc = 1;
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u32 numWarpPerTpc = g->gpu_characteristics.sm_arch_warp_count * numSmPerTpc;
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u32 numWarpPerTpc = g->params.sm_arch_warp_count * numSmPerTpc;
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for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) {
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for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) {
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gpc = g->gr.sm_to_cluster[sm_id].gpc_index;
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gpc = g->gr.sm_to_cluster[sm_id].gpc_index;
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@@ -37,11 +37,11 @@ void vgpu_gr_detect_sm_arch(struct gk20a *g)
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gk20a_dbg_fn("");
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gk20a_dbg_fn("");
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g->gpu_characteristics.sm_arch_sm_version =
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g->params.sm_arch_sm_version =
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priv->constants.sm_arch_sm_version;
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priv->constants.sm_arch_sm_version;
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g->gpu_characteristics.sm_arch_spa_version =
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g->params.sm_arch_spa_version =
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priv->constants.sm_arch_spa_version;
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priv->constants.sm_arch_spa_version;
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g->gpu_characteristics.sm_arch_warp_count =
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g->params.sm_arch_warp_count =
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priv->constants.sm_arch_warp_count;
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priv->constants.sm_arch_warp_count;
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}
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}
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