diff --git a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c
index 39a036c82..b094dff01 100644
--- a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c
+++ b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c
@@ -178,7 +178,7 @@ static int nvgpu_clk_mon_get_fault(struct gk20a *g, u32 i, u32 data,
 	return status;
 }
 
-bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g)
+bool tu104_clk_mon_check_master_fault_status(struct gk20a *g)
 {
 	u32 fmon_master_status = nvgpu_readl(g, trim_fmon_master_status_r());
 
@@ -207,7 +207,7 @@ int nvgpu_clk_mon_alloc_memory(struct gk20a *g)
 	return 0;
 }
 
-int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask)
+int tu104_clk_mon_check_status(struct gk20a *g, u32 domain_mask)
 {
 	u32 reg_address, bit_pos;
 	u32 data;
@@ -247,7 +247,7 @@ int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask)
 	return 0;
 }
 
-bool nvgpu_clk_mon_check_clk_good(struct gk20a *g)
+bool tu104_clk_mon_check_clk_good(struct gk20a *g)
 {
 	u32 clk_status = nvgpu_readl(g, trim_xtal4x_cfg5_r());
 
@@ -258,7 +258,7 @@ bool nvgpu_clk_mon_check_clk_good(struct gk20a *g)
 	return false;
 }
 
-bool nvgpu_clk_mon_check_pll_lock(struct gk20a *g)
+bool tu104_clk_mon_check_pll_lock(struct gk20a *g)
 {
 	u32 clk_status = nvgpu_readl(g, trim_xtal4x_cfg_r());
 
diff --git a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h
index 271d1786e..8fdc1bb96 100644
--- a/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h
+++ b/drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h
@@ -50,8 +50,9 @@ struct clk_domains_mon_status_params {
 		clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
 };
 
-bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g);
-int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask);
-bool nvgpu_clk_mon_check_clk_good(struct gk20a *g);
-bool nvgpu_clk_mon_check_pll_lock(struct gk20a *g);
+bool tu104_clk_mon_check_master_fault_status(struct gk20a *g);
+int tu104_clk_mon_check_status(struct gk20a *g, u32 domain_mask);
+bool tu104_clk_mon_check_clk_good(struct gk20a *g);
+bool tu104_clk_mon_check_pll_lock(struct gk20a *g);
+
 #endif /* CLK_MON_TU104_H */
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 0cc0dc009..c09d6e0e0 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1318,10 +1318,10 @@ static const struct gpu_ops tu104_ops = {
 	.clk_mon = {
 		.clk_mon_alloc_memory = nvgpu_clk_mon_alloc_memory,
 		.clk_mon_check_master_fault_status =
-			nvgpu_clk_mon_check_master_fault_status,
-		.clk_mon_check_status = nvgpu_clk_mon_check_status,
-		.clk_mon_check_clk_good = nvgpu_clk_mon_check_clk_good,
-		.clk_mon_check_pll_lock = nvgpu_clk_mon_check_pll_lock,
+			tu104_clk_mon_check_master_fault_status,
+		.clk_mon_check_status = tu104_clk_mon_check_status,
+		.clk_mon_check_clk_good = tu104_clk_mon_check_clk_good,
+		.clk_mon_check_pll_lock = tu104_clk_mon_check_pll_lock,
 
 	},
 #ifdef CONFIG_NVGPU_CLK_ARB