diff --git a/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c b/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c
index ed4792a87..49c7b07f9 100644
--- a/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c
+++ b/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -181,12 +181,8 @@ u32 nvgpu_cic_mon_intr_stall_isr(struct gk20a *g)
 
 void nvgpu_cic_mon_intr_stall_handle(struct gk20a *g)
 {
-	nvgpu_trace_intr_thread_stall_start(g);
-
 	g->ops.mc.isr_stall(g);
 
-	nvgpu_trace_intr_thread_stall_done(g);
-
 	/* sync handled irq counter before re-enabling interrupts */
 	nvgpu_cic_rm_set_irq_stall(g, 0);
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index b69ec9b44..d371a1108 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11B Tegra HAL interface
  *
- * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1475,7 +1475,6 @@ static const struct gops_grmgr gv11b_ops_grmgr = {
 
 static const struct gops_cic_mon gv11b_ops_cic_mon = {
 	.init = gv11b_cic_mon_init,
-	.report_err = nvgpu_cic_mon_report_err_safety_services,
 };
 
 int gv11b_init_hal(struct gk20a *g)
diff --git a/userspace/units/bus/nvgpu-bus.c b/userspace/units/bus/nvgpu-bus.c
index 393f26491..3c23da05b 100644
--- a/userspace/units/bus/nvgpu-bus.c
+++ b/userspace/units/bus/nvgpu-bus.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -131,7 +131,6 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
 					mc_gp10b_intr_nonstall_unit_config;
 	g->ops.ptimer.isr = gk20a_ptimer_isr;
 	g->ops.cic_mon.init = gv11b_cic_mon_init;
-	g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
 
 	/* Map register space NV_PRIV_MASTER */
 	if (nvgpu_posix_io_add_reg_space(g, NV_PBUS_START, NV_PBUS_SIZE) != 0) {
diff --git a/userspace/units/ce/nvgpu-ce.c b/userspace/units/ce/nvgpu-ce.c
index 2a6fb52bd..bfa447b15 100644
--- a/userspace/units/ce/nvgpu-ce.c
+++ b/userspace/units/ce/nvgpu-ce.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -129,7 +129,6 @@ int test_ce_setup_env(struct unit_module *m,
 	nvgpu_spinlock_init(&g->mc.intr_lock);
 
 	g->ops.cic_mon.init = gv11b_cic_mon_init;
-	g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
 
 	if (nvgpu_cic_mon_setup(g) != 0) {
 		unit_err(m, "%s: failed to initialize CIC\n",
diff --git a/userspace/units/fb/fb_gv11b_fusa.c b/userspace/units/fb/fb_gv11b_fusa.c
index 5fafc1e20..eb3e96811 100644
--- a/userspace/units/fb/fb_gv11b_fusa.c
+++ b/userspace/units/fb/fb_gv11b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -65,7 +65,6 @@ int fb_gv11b_init_test(struct unit_module *m, struct gk20a *g, void *args)
 		mc_gp10b_intr_nonstall_unit_config;
 	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
 	g->ops.cic_mon.init = gv11b_cic_mon_init;
-	g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
 
 	/*
 	 * Define some arbitrary addresses for test purposes.
diff --git a/userspace/units/gr/nvgpu-gr.c b/userspace/units/gr/nvgpu-gr.c
index 7a0606dba..f1a46c626 100644
--- a/userspace/units/gr/nvgpu-gr.c
+++ b/userspace/units/gr/nvgpu-gr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -169,7 +169,6 @@ int test_gr_init_setup_ready(struct unit_module *m,
 	nvgpu_fifo_setup_sw(g);
 
 	g->ops.cic_mon.init = gv11b_cic_mon_init;
-	g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
 
 	err = nvgpu_cic_mon_setup(g);
 	if (err != 0) {
diff --git a/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c b/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
index 2edce1e28..286fca4e7 100644
--- a/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
+++ b/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -223,7 +223,6 @@ int test_env_init_mm_mmu_fault_gv11b_fusa(struct unit_module *m,
 	}
 
 	g->ops.cic_mon.init = gv11b_cic_mon_init;
-	g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
 
 	if (nvgpu_cic_mon_setup(g) != 0) {
 		unit_return_fail(m, "Failed to initialize CIC\n");
diff --git a/userspace/units/priv_ring/nvgpu-priv_ring.c b/userspace/units/priv_ring/nvgpu-priv_ring.c
index 54607d9e5..3cd50fa2c 100644
--- a/userspace/units/priv_ring/nvgpu-priv_ring.c
+++ b/userspace/units/priv_ring/nvgpu-priv_ring.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -127,7 +127,6 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.mc.intr_stall_unit_config =
 					mc_gp10b_intr_stall_unit_config;
 	g->ops.cic_mon.init = gv11b_cic_mon_init;
-	g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
 
 	/* Map register space NV_PRIV_MASTER */
 	if (nvgpu_posix_io_add_reg_space(g, NV_PRIV_MASTER_START,
diff --git a/userspace/units/ptimer/nvgpu-ptimer.c b/userspace/units/ptimer/nvgpu-ptimer.c
index ab79bb204..e379833be 100644
--- a/userspace/units/ptimer/nvgpu-ptimer.c
+++ b/userspace/units/ptimer/nvgpu-ptimer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -90,7 +90,6 @@ int test_setup_env(struct unit_module *m,
 	g->ops.ptimer.isr = gk20a_ptimer_isr;
 
 	g->ops.cic_mon.init = gv11b_cic_mon_init;
-	g->ops.cic_mon.report_err = nvgpu_cic_mon_report_err_safety_services;
 
 	/* Create ptimer register space */
 	if (nvgpu_posix_io_add_reg_space(g, PTIMER_REG_SPACE_START,