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gpu: nvgpu: support nvriscv debug feature

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Enable nvriscv debug buffer feature in NVGPU.
Debug buffer is a feature to print the debug log from ucode onto console
in real time.
Debug buffer feature uses the DMEM, queue and SWGEN1 interrupt to share
ucode debug data with NVGPU.
Ucode writes debug message to DMEM and updates offset in queue to trigger
interrupt to NVGPU.
NVGPU copies the debug message from DMEM to local buffer to process and
print onto console.

Debug buffer feature is added under falcon unit and required engine
can utilize the feature by providing required param through public
functions.

Currently GA10B NVRISCV NS/LS PMU ucode has support for this feature
and enabled support on NVGPU side by adding required changes, with this
feature enabled, it is now possible to see prints in real time.

JIRA NVGPU-6959

Change-Id: I9d46020470285b490b6bc876204f62698055b1ec
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548951
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
mkumbar
2021-06-30 11:23:39 +05:30
committed by mobile promotions
parent 7ce01d3d1d
commit 87984ea344
21 changed files with 576 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
View File

@@ -34,6 +34,7 @@
#include <nvgpu/pmu.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/falcon.h>
#include <nvgpu/pmu/mutex.h>
#include <nvgpu/pmu/seq.h>
@@ -159,6 +160,13 @@ static void remove_pmu_support(struct nvgpu_pmu *pmu)
nvgpu_pmu_pstate_deinit(g);
}
#ifdef CONFIG_NVGPU_FALCON_DEBUG
if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
nvgpu_falcon_dbg_buf_display(pmu->flcn);
nvgpu_falcon_dbg_buf_destroy(pmu->flcn);
}
#endif
nvgpu_pmu_debug_deinit(g, pmu);
nvgpu_pmu_lsfm_deinit(g, pmu, pmu->lsfm);
#ifdef CONFIG_PMU_POWER_PG
@@ -418,6 +426,18 @@ int nvgpu_pmu_rtos_init(struct gk20a *g)
#if defined(CONFIG_NVGPU_NON_FUSA)
if (nvgpu_is_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED)) {
#ifdef CONFIG_NVGPU_FALCON_DEBUG
err = nvgpu_falcon_dbg_buf_init(g->pmu->flcn,
NV_RISCV_DMESG_BUFFER_SIZE,
g->ops.pmu.pmu_get_queue_head(NV_RISCV_DEBUG_BUFFER_QUEUE),
g->ops.pmu.pmu_get_queue_tail(NV_RISCV_DEBUG_BUFFER_QUEUE));
if (err != 0) {
nvgpu_err(g,
"Failed to allocate RISCV PMU debug buffer status=0x%x)",
err);
goto exit;
}
#endif
g->ops.falcon.bootstrap(g->pmu->flcn, 0U);
err = nvgpu_pmu_wait_for_priv_lockdown_release(g,
g->pmu->flcn, U32_MAX);