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gpu: nvgpu: Trigger quiesce on PBDMA preempt fail

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During recovery, we preempt the faulty TSG from PBDMA and engines.
If the TSG preempt on PBDMA times out(timeout = 100ms), the PBDMA
might be hung state. We do not reset the HOST during recovery, so
stuck PBDMAs are unrecoverable.
Abort the recovery and trigger GPU to quiesce as there is no way
back.

Triggering Quiesce from recovery sequence should be fine as the only
redundant operation will be write to FIFO_RUNLIST_PREEMPT register.
The error notifiers will eventually be set by Quiesce thread.

Bug 2768005
JIRA NVGPU-4631

Change-Id: I914b9379aa8e48014e6ddace9abe47180a072863
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2368187
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2020-07-13 10:55:47 +00:00
committed by Alex Waterman
parent f7a73f4ab8
commit 881a6f35be
4 changed files with 19 additions and 24 deletions
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19
userspace/units/fifo/preempt/nvgpu-preempt.c
View File

@@ -162,13 +162,11 @@ done:
}
#define F_PREEMPT_POLL_PBDMA_NULL BIT(0)
#define F_PREEMPT_POLL_TSG_NULL BIT(1)
#define F_PREEMPT_POLL_PBDMA_BUSY BIT(2)
#define F_PREEMPT_POLL_LAST BIT(3)
#define F_PREEMPT_POLL_PBDMA_BUSY BIT(1)
#define F_PREEMPT_POLL_LAST BIT(2)
static const char *f_preempt_poll[] = {
"preempt_poll_pbdma_null",
"tsg_null",
"preempt_poll_pbdma_busy",
};
@@ -197,7 +195,7 @@ int test_preempt_poll_tsg_on_pbdma(struct unit_module *m, struct gk20a *g,
u32 branches = 0U;
int ret = UNIT_FAIL;
u32 prune = F_PREEMPT_POLL_PBDMA_NULL | F_PREEMPT_POLL_TSG_NULL;
u32 prune = F_PREEMPT_POLL_PBDMA_NULL;
tsg = nvgpu_tsg_open(g, getpid());
unit_assert(tsg != NULL, goto done);
@@ -221,14 +219,11 @@ int test_preempt_poll_tsg_on_pbdma(struct unit_module *m, struct gk20a *g,
stub_fifo_preempt_poll_pbdma_busy :
stub_fifo_preempt_poll_pbdma);
if (branches & F_PREEMPT_POLL_TSG_NULL) {
nvgpu_preempt_poll_tsg_on_pbdma(g, NULL);
} else {
nvgpu_preempt_poll_tsg_on_pbdma(g, tsg);
}
nvgpu_preempt_poll_tsg_on_pbdma(g, tsg);
if (branches & F_PREEMPT_POLL_TSG_NULL) {
unit_assert(stub[0].tsgid == NVGPU_INVALID_TSG_ID,
if (branches & F_PREEMPT_POLL_PBDMA_BUSY) {
unit_assert(stub[0].pbdma_id !=
nvgpu_ffs(f->runlist_info[0]->pbdma_bitmask),
goto done);
} else if (!(branches & F_PREEMPT_POLL_PBDMA_NULL)) {
unit_assert(stub[0].tsgid == 0, goto done);