diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml
index e4089c457..2672abcb4 100644
--- a/arch/nvgpu-common.yaml
+++ b/arch/nvgpu-common.yaml
@@ -786,7 +786,7 @@ pmu:
                      common/pmu/clk/clk_vf_point.h,
                      common/pmu/clk/clk_vin.c,
                      common/pmu/clk/clk_vin.h,
-                     include/nvgpu/clk.h,
+                     common/pmu/clk/clk.h,
                      include/nvgpu/pmu/clk/clk.h]
     ipc:
       safe: yes
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c
index be950ac4e..044c158d5 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c
@@ -39,31 +39,6 @@
 #include "clk_fll.h"
 #include "clk_vf_point.h"
 
-int nvgpu_pmu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx,
-	u32 *pclkmhz, u32 *pvoltuv, u8 railidx)
-{
-
-	struct nvgpu_clk_vf_points *pclk_vf_points;
-	struct boardobjgrp *pboardobjgrp;
-	struct boardobj *pboardobj = NULL;
-	int status = -EINVAL;
-	struct clk_vf_point *pclk_vf_point;
-	u8 index;
-
-	nvgpu_log_info(g, " ");
-	pclk_vf_points = g->pmu->clk_pmu->clk_vf_pointobjs;
-	pboardobjgrp = &pclk_vf_points->super.super;
-
-	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
-		pclk_vf_point = (struct clk_vf_point *)(void *)pboardobj;
-		if((*pclkmhz) <= pclk_vf_point->pair.freq_mhz) {
-			*pvoltuv = pclk_vf_point->pair.voltage_uv;
-			return 0;
-		}
-	}
-	return status;
-}
-
 #ifdef CONFIG_NVGPU_CLK_ARB
 int nvgpu_clk_get_fll_clks(struct gk20a *g,
 		struct nvgpu_set_fll_clk *setfllclk)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk.h b/drivers/gpu/nvgpu/common/pmu/clk/clk.h
similarity index 62%
rename from drivers/gpu/nvgpu/include/nvgpu/clk.h
rename to drivers/gpu/nvgpu/common/pmu/clk/clk.h
index 490097ac0..0ca3259c7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/clk.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
- *
+* Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+*
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
@@ -18,26 +18,36 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
- */
+*/
 
-#ifndef NVGPU_INCLUDE_CLK_H
-#define NVGPU_INCLUDE_CLK_H
+#ifndef NVGPU_CLK_H
+#define NVGPU_CLK_H
 
-#define CLK_NAME_MAX	24
-#define CLK_MAX_CNTRL_REGISTERS   2
+#include <nvgpu/boardobjgrp_e255.h>
+#include "ucode_clk_inf.h"
 
-struct namemap_cfg {
-	u32 namemap;
-	u32 is_enable;	/* Namemap enabled */
-	u32 is_counter;	/* Using cntr */
-	struct gk20a *g;
-	struct {
-		u32 reg_ctrl_addr;
-		u32 reg_ctrl_idx;
-		u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS];
-	} cntr;
-	u32 scale;
-	char name[CLK_NAME_MAX];
+struct clk_vf_point {
+	struct boardobj super;
+	u8  vfe_equ_idx;
+	u8  volt_rail_idx;
+	struct ctrl_clk_vf_pair pair;
 };
 
-#endif /* NVGPU_INCLUDE_CLK_H */
+struct clk_vf_point_volt {
+	struct clk_vf_point super;
+	u32 source_voltage_uv;
+	struct ctrl_clk_freq_delta freq_delta;
+};
+
+struct clk_vf_point_freq {
+	struct clk_vf_point super;
+	int volt_delta_uv;
+};
+
+struct nvgpu_clk_vf_points {
+	struct boardobjgrp_e255 super;
+};
+
+struct clk_vf_point *nvgpu_construct_clk_vf_point(struct gk20a *g,
+	void *pargs);
+#endif /* NVGPU_CLK_H */
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
index bdb08b848..9e94bfd82 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
@@ -37,6 +37,7 @@
 #include "ucode_clk_inf.h"
 #include "clk_domain.h"
 #include "clk_prog.h"
+#include "clk.h"
 
 static struct nvgpu_clk_domain *construct_clk_domain(struct gk20a *g,
 		void *pargs);
@@ -1724,3 +1725,29 @@ u8 nvgpu_pmu_clk_domain_update_clk_info(struct gk20a *g,
 	return num_domains;
 
 }
+
+int nvgpu_pmu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx,
+	u32 *pclkmhz, u32 *pvoltuv, u8 railidx)
+{
+
+	struct nvgpu_clk_vf_points *pclk_vf_points;
+	struct boardobjgrp *pboardobjgrp;
+	struct boardobj *pboardobj = NULL;
+	int status = -EINVAL;
+	struct clk_vf_point *pclk_vf_point;
+	u8 index;
+
+	nvgpu_log_info(g, " ");
+	pclk_vf_points = g->pmu->clk_pmu->clk_vf_pointobjs;
+	pboardobjgrp = &pclk_vf_points->super.super;
+
+	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
+		pclk_vf_point = (struct clk_vf_point *)(void *)pboardobj;
+		if((*pclkmhz) <= pclk_vf_point->pair.freq_mhz) {
+			*pvoltuv = pclk_vf_point->pair.voltage_uv;
+			return 0;
+		}
+	}
+	return status;
+}
+
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
index 3ac00ddb6..ff05bec69 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
@@ -31,6 +31,8 @@
 
 #include "ucode_clk_inf.h"
 #include "clk_fll.h"
+#include "clk_vin.h"
+#include "clk.h"
 
 #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP	0x10U
 #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK	0x1FU
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
index 9a00e61ab..780ebe7a0 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
@@ -32,6 +32,7 @@
 
 #include "ucode_clk_inf.h"
 #include "clk_prog.h"
+#include "clk.h"
 
 static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs);
 static int devinit_get_clk_prog_table(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
index 9d81ada6f..50fe73f1c 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
@@ -35,6 +35,7 @@
 
 #include "ucode_clk_inf.h"
 #include "clk_vf_point.h"
+#include "clk.h"
 
 int nvgpu_clk_domain_volt_to_freq(struct gk20a *g, u8 clkdomain_idx,
 	u32 *pclkmhz, u32 *pvoltuv, u8 railidx)
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h
index a5c846ed2..b78489af8 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h
@@ -25,6 +25,17 @@
 #ifndef NVGPU_CLK_VF_POINT_H
 #define NVGPU_CLK_VF_POINT_H
 
+struct nv_pmu_rpc_clk_domain_35_prog_freq_to_volt {
+	/*[IN/OUT] Must be first field in RPC structure */
+	struct nv_pmu_rpc_header hdr;
+	u8 clk_domain_idx;
+	u8 volt_rail_idx;
+	u8 voltage_type;
+	struct ctrl_clk_vf_input input;
+	struct ctrl_clk_vf_output output;
+	u32 scratch[1];
+};
+
 int clk_vf_point_init_pmupstate(struct gk20a *g);
 void clk_vf_point_free_pmupstate(struct gk20a *g);
 int clk_vf_point_sw_setup(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
index b62a1226d..ff478f38e 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
@@ -35,6 +35,7 @@
 
 #include "ucode_clk_inf.h"
 #include "clk_vin.h"
+#include "clk.h"
 
 static int devinit_get_vin_device_table(struct gk20a *g,
 		struct nvgpu_avfsvinobjs *pvinobjs);
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h
index 07c9ea19c..3cdf60fc3 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h
@@ -27,6 +27,17 @@
 #include <nvgpu/boardobjgrp.h>
 #include <nvgpu/boardobjgrp_e32.h>
 
+struct nvgpu_vin_device {
+	struct boardobj super;
+	u8 id;
+	u8 volt_domain;
+	u8 volt_domain_vbios;
+	u8 por_override_mode;
+	u8 override_mode;
+	u32 flls_shared_mask;
+	vin_device_state_load  *state_load;
+};
+
 struct vin_device_v20 {
 	struct nvgpu_vin_device super;
 	struct ctrl_clk_vin_device_info_data_v20 data;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/ucode_clk_inf.h b/drivers/gpu/nvgpu/common/pmu/clk/ucode_clk_inf.h
index 0959bcac8..f355c8c97 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/ucode_clk_inf.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/ucode_clk_inf.h
@@ -121,6 +121,21 @@
 #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS		(0x00000002U)
 #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES	(0x00000001U)
 
+union ctrl_clk_freq_delta_data {
+	s32 delta_khz;
+	s16 delta_percent;
+};
+
+struct ctrl_clk_freq_delta {
+	u8 type;
+	union ctrl_clk_freq_delta_data data;
+};
+
+struct ctrl_clk_clk_delta {
+	struct ctrl_clk_freq_delta freq_delta;
+	int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
+};
+
 struct ctrl_clk_domain_control_35_prog_clk_mon {
 	u32 flags;
 	u32 low_threshold_override;
@@ -468,6 +483,17 @@ struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header {
 	u16 max_min_freq_mhz;
 };
 
+struct nv_pmu_clk_lut_device_desc {
+	u8 vselect_mode;
+	u16 hysteresis_threshold;
+};
+
+struct nv_pmu_clk_regime_desc {
+	u8 regime_id;
+	u8 target_regime_id_override;
+	u16 fixed_freq_regime_limit_mhz;
+};
+
 struct nv_pmu_clk_clk_fll_device_boardobj_set {
 	struct nv_pmu_boardobj super;
 	u8 id;
@@ -596,6 +622,11 @@ struct nv_pmu_clk_clk_vf_point_35_volt_sec_boardobj_get_status {
 		offseted_vf_tuple[CTRL_CLK_CLK_VF_POINT_FREQ_TUPLE_MAX_SIZE];
 };
 
+struct ctrl_clk_vf_pair {
+	u16 freq_mhz;
+	u32 voltage_uv;
+};
+
 struct nv_pmu_clk_clk_vf_point_boardobj_get_status {
 	struct nv_pmu_boardobj super;
 	struct ctrl_clk_vf_pair pair;
@@ -717,40 +748,5 @@ union nv_pmu_clk_clk_fll_device_boardobj_get_status_union {
 
 NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device);
 
-struct nv_pmu_rpc_clk_domain_35_prog_freq_to_volt {
-	/*[IN/OUT] Must be first field in RPC structure */
-	struct nv_pmu_rpc_header hdr;
-	u8 clk_domain_idx;
-	u8 volt_rail_idx;
-	u8 voltage_type;
-	struct ctrl_clk_vf_input input;
-	struct ctrl_clk_vf_output output;
-	u32 scratch[1];
-};
-
-struct nvgpu_clk_vf_points {
-	struct boardobjgrp_e255 super;
-};
-
-struct clk_vf_point {
-	struct boardobj super;
-	u8  vfe_equ_idx;
-	u8  volt_rail_idx;
-	struct ctrl_clk_vf_pair pair;
-};
-
-struct clk_vf_point_volt {
-	struct clk_vf_point super;
-	u32 source_voltage_uv;
-	struct ctrl_clk_freq_delta freq_delta;
-};
-
-struct clk_vf_point_freq {
-	struct clk_vf_point super;
-	int volt_delta_uv;
-};
-
-struct clk_vf_point *nvgpu_construct_clk_vf_point(struct gk20a *g,
-	void *pargs);
 
 #endif /* NVGPU_PMUIF_CLK_H */
diff --git a/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h b/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h
index 5b2618998..8e349f2fa 100644
--- a/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h
+++ b/drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h
@@ -165,6 +165,17 @@ struct ctrl_perf_change_seq_pmu_script_step_bif {
 	u8 nvlink_idx;
 };
 
+struct ctrl_clk_vin_sw_override_list_item {
+	u8 override_mode;
+	u32 voltage_uV;
+};
+
+struct ctrl_clk_vin_sw_override_list {
+	struct ctrl_boardobjgrp_mask_e32 volt_rails_mask;
+	struct ctrl_clk_vin_sw_override_list_item
+		volt[4];
+};
+
 struct ctrl_perf_change_seq_pmu_script_step_clks {
 	struct ctrl_perf_change_seq_pmu_script_step_super super;
 	struct ctrl_clk_clk_domain_list clk_list;
diff --git a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c
index c9306a8cf..a067e4ca0 100644
--- a/drivers/gpu/nvgpu/hal/clk/clk_tu104.c
+++ b/drivers/gpu/nvgpu/hal/clk/clk_tu104.c
@@ -33,7 +33,6 @@
 #include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/soc.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/clk.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/pmu/volt.h>
diff --git a/drivers/gpu/nvgpu/hal/clk/clk_tu104.h b/drivers/gpu/nvgpu/hal/clk/clk_tu104.h
index 097127b32..9640f8936 100644
--- a/drivers/gpu/nvgpu/hal/clk/clk_tu104.h
+++ b/drivers/gpu/nvgpu/hal/clk/clk_tu104.h
@@ -25,6 +25,23 @@
 #include <nvgpu/lock.h>
 #include <nvgpu/gk20a.h>
 
+#define CLK_NAME_MAX			24
+#define CLK_MAX_CNTRL_REGISTERS		2
+
+struct namemap_cfg {
+	u32 namemap;
+	u32 is_enable;
+	u32 is_counter;
+	struct gk20a *g;
+	struct {
+		u32 reg_ctrl_addr;
+		u32 reg_ctrl_idx;
+		u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS];
+	} cntr;
+	u32 scale;
+	char name[CLK_NAME_MAX];
+};
+
 u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
 int tu104_init_clk_support(struct gk20a *g);
 u32 tu104_crystal_clk_hz(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
index e63643e99..6fbb6a654 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
@@ -33,51 +33,49 @@
 /*!
  * Valid global VIN ID values
  */
-#define	CTRL_CLK_VIN_ID_SYS		0x00000000U
-#define	CTRL_CLK_VIN_ID_LTC		0x00000001U
-#define	CTRL_CLK_VIN_ID_XBAR		0x00000002U
-#define	CTRL_CLK_VIN_ID_GPC0		0x00000003U
-#define	CTRL_CLK_VIN_ID_GPC1		0x00000004U
-#define	CTRL_CLK_VIN_ID_GPC2		0x00000005U
-#define	CTRL_CLK_VIN_ID_GPC3		0x00000006U
-#define	CTRL_CLK_VIN_ID_GPC4		0x00000007U
-#define	CTRL_CLK_VIN_ID_GPC5		0x00000008U
-#define	CTRL_CLK_VIN_ID_GPCS		0x00000009U
-#define	CTRL_CLK_VIN_ID_SRAM		0x0000000AU
-#define	CTRL_CLK_VIN_ID_UNDEFINED	0x000000FFU
+#define	CTRL_CLK_VIN_ID_SYS			0x00000000U
+#define	CTRL_CLK_VIN_ID_LTC			0x00000001U
+#define	CTRL_CLK_VIN_ID_XBAR			0x00000002U
+#define	CTRL_CLK_VIN_ID_GPC0			0x00000003U
+#define	CTRL_CLK_VIN_ID_GPC1			0x00000004U
+#define	CTRL_CLK_VIN_ID_GPC2			0x00000005U
+#define	CTRL_CLK_VIN_ID_GPC3			0x00000006U
+#define	CTRL_CLK_VIN_ID_GPC4			0x00000007U
+#define	CTRL_CLK_VIN_ID_GPC5			0x00000008U
+#define	CTRL_CLK_VIN_ID_GPCS			0x00000009U
+#define	CTRL_CLK_VIN_ID_SRAM			0x0000000AU
+#define	CTRL_CLK_VIN_ID_UNDEFINED		0x000000FFU
 
-#define	CTRL_CLK_VIN_TYPE_DISABLED 0x00000000U
-#define CTRL_CLK_VIN_TYPE_V20      0x00000002U
+#define	CTRL_CLK_VIN_TYPE_DISABLED		0x00000000U
+#define CTRL_CLK_VIN_TYPE_V20			0x00000002U
 
 /* valid clock domain values */
-#define CTRL_CLK_DOMAIN_MCLK                                (0x00000010U)
-#define CTRL_CLK_DOMAIN_HOSTCLK                             (0x00000020U)
-#define CTRL_CLK_DOMAIN_DISPCLK                             (0x00000040U)
-#define CTRL_CLK_DOMAIN_GPC2CLK                             (0x00010000U)
-#define CTRL_CLK_DOMAIN_XBAR2CLK                            (0x00040000U)
-#define CTRL_CLK_DOMAIN_SYS2CLK                             (0x00800000U)
-#define CTRL_CLK_DOMAIN_HUB2CLK                             (0x01000000U)
-#define CTRL_CLK_DOMAIN_UTILSCLK                            (0x00040000U)
-#define CTRL_CLK_DOMAIN_PWRCLK                              (0x00080000U)
-#define CTRL_CLK_DOMAIN_NVDCLK                              (0x00100000U)
-#define CTRL_CLK_DOMAIN_PCIEGENCLK                          (0x00200000U)
-#define CTRL_CLK_DOMAIN_XCLK                                (0x04000000U)
-#define CTRL_CLK_DOMAIN_NVL_COMMON                          (0x08000000U)
-#define CTRL_CLK_DOMAIN_PEX_REFCLK                          (0x10000000U)
-
-#define CTRL_CLK_DOMAIN_GPCCLK                              (0x00000001U)
-#define CTRL_CLK_DOMAIN_XBARCLK                             (0x00000002U)
-#define CTRL_CLK_DOMAIN_SYSCLK                              (0x00000004U)
-#define CTRL_CLK_DOMAIN_HUBCLK                              (0x00000008U)
+#define CTRL_CLK_DOMAIN_MCLK			0x00000010U
+#define CTRL_CLK_DOMAIN_HOSTCLK			0x00000020U
+#define CTRL_CLK_DOMAIN_DISPCLK			0x00000040U
+#define CTRL_CLK_DOMAIN_GPC2CLK			0x00010000U
+#define CTRL_CLK_DOMAIN_XBAR2CLK		0x00040000U
+#define CTRL_CLK_DOMAIN_SYS2CLK			0x00800000U
+#define CTRL_CLK_DOMAIN_HUB2CLK			0x01000000U
+#define CTRL_CLK_DOMAIN_UTILSCLK		0x00040000U
+#define CTRL_CLK_DOMAIN_PWRCLK			0x00080000U
+#define CTRL_CLK_DOMAIN_NVDCLK			0x00100000U
+#define CTRL_CLK_DOMAIN_PCIEGENCLK		0x00200000U
+#define CTRL_CLK_DOMAIN_XCLK			0x04000000U
+#define CTRL_CLK_DOMAIN_NVL_COMMON		0x08000000U
+#define CTRL_CLK_DOMAIN_PEX_REFCLK		0x10000000U
+#define CTRL_CLK_DOMAIN_GPCCLK			0x00000001U
+#define CTRL_CLK_DOMAIN_XBARCLK			0x00000002U
+#define CTRL_CLK_DOMAIN_SYSCLK			0x00000004U
+#define CTRL_CLK_DOMAIN_HUBCLK			0x00000008U
 
 
-#define CTRL_CLK_FLL_REGIME_ID_INVALID                     ((u8)0x00000000)
-#define CTRL_CLK_FLL_REGIME_ID_FFR                         ((u8)0x00000001)
-#define CTRL_CLK_FLL_REGIME_ID_FR                          ((u8)0x00000002)
+#define CTRL_CLK_FLL_REGIME_ID_INVALID		((u8)0x00000000)
+#define CTRL_CLK_FLL_REGIME_ID_FFR		((u8)0x00000001)
+#define CTRL_CLK_FLL_REGIME_ID_FR		((u8)0x00000002)
 
-#define CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS			16
-#define CLK_CLOCK_MON_DOMAIN_COUNT				0x32U
-#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4U
+#define CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS	16
+#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 	4U
 /*
  *  Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal
  *
@@ -89,42 +87,43 @@
  *  xbar2clk is 19 in Pascal and 14 in Volta
  *    Changing for Pascal would break pwrclk of Volta
  */
-#define CLKWHICH_GPCCLK		1U
-#define CLKWHICH_XBARCLK	2U
-#define CLKWHICH_SYSCLK		3U
-#define CLKWHICH_HUBCLK		4U
-#define CLKWHICH_MCLK		5U
-#define CLKWHICH_HOSTCLK	6U
-#define CLKWHICH_DISPCLK	7U
-#define CLKWHICH_XCLK		12U
-#define CLKWHICH_XBAR2CLK	14U
-#define CLKWHICH_SYS2CLK	15U
-#define CLKWHICH_HUB2CLK	16U
-#define CLKWHICH_GPC2CLK	17U
-#define CLKWHICH_PWRCLK		19U
-#define CLKWHICH_NVDCLK		20U
-#define CLKWHICH_PCIEGENCLK	26U
+#define CLKWHICH_GPCCLK				1U
+#define CLKWHICH_XBARCLK			2U
+#define CLKWHICH_SYSCLK				3U
+#define CLKWHICH_HUBCLK				4U
+#define CLKWHICH_MCLK				5U
+#define CLKWHICH_HOSTCLK			6U
+#define CLKWHICH_DISPCLK			7U
+#define CLKWHICH_XCLK				12U
+#define CLKWHICH_XBAR2CLK			14U
+#define CLKWHICH_SYS2CLK			15U
+#define CLKWHICH_HUB2CLK			16U
+#define CLKWHICH_GPC2CLK			17U
+#define CLKWHICH_PWRCLK				19U
+#define CLKWHICH_NVDCLK				20U
+#define CLKWHICH_PCIEGENCLK			26U
 
 
 /*!
  * Mask of all GPC VIN IDs supported by RM
  */
-#define CTRL_CLK_LUT_NUM_ENTRIES_MAX   (128U)
-#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128U)
-#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100U)
-#define CTRL_CLK_VIN_STEP_SIZE_UV (6250U)
-#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000U)
-#define CTRL_CLK_FLL_TYPE_DISABLED 0U
+#define CTRL_CLK_LUT_NUM_ENTRIES_MAX		128U
+#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x		128U
+#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x		100U
+#define CTRL_CLK_VIN_STEP_SIZE_UV		6250U
+#define CTRL_CLK_LUT_MIN_VOLTAGE_UV		450000U
+#define CTRL_CLK_FLL_TYPE_DISABLED		0U
 
-#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC			   (0x00000000U)
-#define CTRL_CLK_FLL_LUT_VSELECT_MIN			   (0x00000001U)
-#define CTRL_CLK_FLL_LUT_VSELECT_SRAM			   (0x00000002U)
+#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC		0x00000000U
+#define CTRL_CLK_FLL_LUT_VSELECT_MIN		0x00000001U
+#define CTRL_CLK_FLL_LUT_VSELECT_SRAM		0x00000002U
 
-#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_HW_REQ  (0x00000000U)
-#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN     (0x00000001U)
-#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ  (0x00000003U)
+#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_HW_REQ	0x00000000U
+#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN	0x00000001U
+#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ	0x00000003U
+#define CLK_CLOCK_MON_DOMAIN_COUNT		0x32U
+#define FREQ_STEP_SIZE_MHZ			15U
 
-#define FREQ_STEP_SIZE_MHZ      15U
 
 struct gk20a;
 struct clk_avfs_fll_objs;
@@ -137,6 +136,21 @@ struct nvgpu_pmu_perf_change_input_clk_info;
 struct nvgpu_vin_device;
 struct nvgpu_clk_domain;
 struct nvgpu_clk_arb;
+struct nvgpu_clk_pmupstate;
+
+
+struct clk_domain_mon_status {
+	u32 clk_api_domain;
+	u32 low_threshold;
+	u32 high_threshold;
+	u32 clk_domain_fault_status;
+};
+
+struct clk_domains_mon_status_params {
+	u32 clk_mon_domain_mask;
+	struct clk_domain_mon_status
+		clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
+};
 
 struct ctrl_clk_domain_clk_mon_item {
 	u32 clk_api_domain;
@@ -164,61 +178,6 @@ struct ctrl_clk_clk_domain_list {
 		clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
 };
 
-struct clk_domain_mon_status {
-	u32 clk_api_domain;
-	u32 low_threshold;
-	u32 high_threshold;
-	u32 clk_domain_fault_status;
-};
-
-struct clk_domains_mon_status_params {
-	u32 clk_mon_domain_mask;
-	struct clk_domain_mon_status
-		clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
-};
-
-struct ctrl_clk_vin_sw_override_list_item {
-	u8 override_mode;
-	u32 voltage_uV;
-};
-
-struct ctrl_clk_vin_sw_override_list {
-	struct ctrl_boardobjgrp_mask_e32 volt_rails_mask;
-	struct ctrl_clk_vin_sw_override_list_item
-		volt[4];
-};
-
-union ctrl_clk_freq_delta_data {
-	s32 delta_khz;
-	s16 delta_percent;
-};
-struct ctrl_clk_freq_delta {
-	u8 type;
-	union ctrl_clk_freq_delta_data data;
-};
-
-struct ctrl_clk_clk_delta {
-	struct ctrl_clk_freq_delta freq_delta;
-	int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
-};
-
-struct nv_pmu_clk_lut_device_desc {
-	u8 vselect_mode;
-	u16 hysteresis_threshold;
-};
-
-
-struct nv_pmu_clk_regime_desc {
-	u8 regime_id;
-	u8 target_regime_id_override;
-	u16 fixed_freq_regime_limit_mhz;
-};
-
-struct ctrl_clk_vf_pair {
-	u16 freq_mhz;
-	u32 voltage_uv;
-};
-
 struct nvgpu_set_fll_clk {
 	u32 voltuv;
 	u16 gpc2clkmhz;
@@ -274,18 +233,6 @@ struct nvgpu_clk_pmupstate {
 typedef u32 vin_device_state_load(struct gk20a *g,
 		struct nvgpu_clk_pmupstate *clk, struct nvgpu_vin_device *pdev);
 
-struct nvgpu_vin_device {
-	struct boardobj super;
-	u8 id;
-	u8 volt_domain;
-	u8 volt_domain_vbios;
-	u8 por_override_mode;
-	u8 override_mode;
-	u32 flls_shared_mask;
-
-	vin_device_state_load  *state_load;
-};
-
 typedef int nvgpu_clkproglink(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
 	struct nvgpu_clk_domain *pdomain);
 
diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c b/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
index caa667864..12b69380a 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
@@ -19,7 +19,6 @@
 
 #include "os_linux.h"
 
-#include <nvgpu/clk.h>
 #include <nvgpu/boardobj.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/boardobjgrp_e255.h>