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gpu: nvgpu: Fix MISRA violations in PMU unit

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- Rule 17.7 states that the value returned by a
  function having non-void return type shall be
  used.
- Add NVGPU_FEATURE_LS_PMU to compile out headers
  in pmu_gv11b.h to fix MISRA violation 8.6

JIRA NVGPU-3570

Change-Id: I6ab104aa72d8fd6419bd336c45e9055a40ba5a7e
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131420
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2019-06-04 15:44:16 +05:30
committed by mobile promotions
parent 7e8d0c2bb1
commit 8948c91719
7 changed files with 16 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -443,7 +443,10 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable)
#ifdef CONFIG_NVGPU_LS_PMU
g->ops.pmu.pmu_enable_irq(pmu, false);
#endif
pmu_enable_hw(pmu, false);
err = pmu_enable_hw(pmu, false);
if (err != 0) {
goto exit;
}
}
} else {
err = pmu_enable_hw(pmu, true);
@@ -480,6 +483,9 @@ int nvgpu_pmu_reset(struct gk20a *g)
}
err = pmu_enable(pmu, true);
if (err != 0) {
goto exit;
}
exit:
nvgpu_log_fn(g, " %s Done, status - %d ", g->name, err);

4
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
View File

@@ -734,7 +734,7 @@ bool gk20a_pmu_is_engine_in_reset(struct gk20a *g)
return status;
}
int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset)
void gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset)
{
u32 reset_mask = g->ops.mc.reset_mask(g, NVGPU_UNIT_PWR);
@@ -743,8 +743,6 @@ int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset)
} else {
g->ops.mc.disable(g, reset_mask);
}
return 0;
}
void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)

2
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h
View File

@@ -57,7 +57,7 @@ int gk20a_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status,
int gk20a_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
u32 args_offset);
bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
void gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr);
u32 gk20a_pmu_falcon_base_addr(void);
bool gk20a_is_pmu_supported(struct gk20a *g);

4
drivers/gpu/nvgpu/hal/pmu/pmu_gp106.c
View File

@@ -42,7 +42,7 @@ bool gp106_pmu_is_engine_in_reset(struct gk20a *g)
return status;
}
int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset)
void gp106_pmu_engine_reset(struct gk20a *g, bool do_reset)
{
/*
* From GP10X onwards, we are using PPWR_FALCON_ENGINE for reset. And as
@@ -58,8 +58,6 @@ int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset)
pwr_falcon_engine_reset_true_f());
(void) gk20a_readl(g, pwr_falcon_engine_r());
}
return 0;
}
#ifdef CONFIG_NVGPU_LS_PMU
void gp106_pmu_setup_apertures(struct gk20a *g)

2
drivers/gpu/nvgpu/hal/pmu/pmu_gp106.h
View File

@@ -30,7 +30,7 @@ struct gk20a;
bool gp106_is_pmu_supported(struct gk20a *g);
bool gp106_pmu_is_engine_in_reset(struct gk20a *g);
int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset);
void gp106_pmu_engine_reset(struct gk20a *g, bool do_reset);
void gp106_pmu_setup_apertures(struct gk20a *g);
u32 gp106_pmu_falcon_base_addr(void);

4
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h
View File

@@ -37,11 +37,15 @@ void gv11b_write_dmatrfbase(struct gk20a *g, u32 addr);
u32 gv11b_pmu_falcon_base_addr(void);
void gv11b_secured_pmu_start(struct gk20a *g);
bool gv11b_is_pmu_supported(struct gk20a *g);
#ifdef CONFIG_NVGPU_LS_PMU
int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
u32 args_offset);
void gv11b_pmu_setup_elpg(struct gk20a *g);
u32 gv11b_pmu_get_irqdest(struct gk20a *g);
void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
#endif
void gv11b_clear_pmu_bar0_host_err_status(struct gk20a *g);
int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status,
u32 *etype);

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1369,7 +1369,7 @@ struct gpu_ops {
u32 (*falcon_base_addr)(void);
/* reset */
int (*pmu_reset)(struct gk20a *g);
int (*reset_engine)(struct gk20a *g, bool do_reset);
void (*reset_engine)(struct gk20a *g, bool do_reset);
bool (*is_engine_in_reset)(struct gk20a *g);
/* secure boot */
void (*setup_apertures)(struct gk20a *g);