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gpu: nvgpu: MISRA 14.4 bitwise operation as boolean

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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the result of a bitwise operation is used as a
boolean in the controlling expression of if and loop statements.

JIRA NVGPU-1020

Change-Id: If910150072c3dd67c31fe9819c3a9e738fd3c1c6
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932389
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Amurthyreddy
2018-10-22 16:35:48 +05:30
committed by mobile promotions
parent 0d065df144
commit 89660dbd62
21 changed files with 226 additions and 206 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c
View File

@@ -243,8 +243,8 @@ void gp10b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice)
ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset);
/* Detect and handle ECC errors */
if (ltc_intr &
ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) {
if ((ltc_intr &
ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) != 0U) {
u32 ecc_stats_reg_val;
nvgpu_err(g,
@@ -262,8 +262,8 @@ void gp10b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice)
ecc_stats_reg_val);
g->ops.mm.l2_flush(g, true);
}
if (ltc_intr &
ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) {
if ((ltc_intr &
ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) != 0U) {
u32 ecc_stats_reg_val;
nvgpu_err(g,

16
drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c
View File

@@ -121,9 +121,9 @@ void gv11b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice)
offset);
/* Detect and handle ECC PARITY errors */
if (ltc_intr3 &
if ((ltc_intr3 &
(ltc_ltcs_ltss_intr3_ecc_uncorrected_m() |
ltc_ltcs_ltss_intr3_ecc_corrected_m())) {
ltc_ltcs_ltss_intr3_ecc_corrected_m())) != 0U) {
ecc_status = gk20a_readl(g,
ltc_ltc0_lts0_l2_cache_ecc_status_r() +
@@ -173,22 +173,22 @@ void gv11b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice)
nvgpu_log(g, gpu_dbg_intr,
"ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3);
if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()) {
if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "rstg ecc error corrected");
}
if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()) {
if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "rstg ecc error uncorrected");
}
if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()) {
if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "tstg ecc error corrected");
}
if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()) {
if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "tstg ecc error uncorrected");
}
if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()) {
if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "dstg ecc error corrected");
}
if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()) {
if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "dstg ecc error uncorrected");
}