diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4686e0dd6..12e69afcd 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -244,7 +244,8 @@ nvgpu-$(CONFIG_GK20A_PCI) += \ nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += \ os/linux/nvhost.o \ - common/sync/syncpt_cmdbuf_gk20a.o + common/sync/syncpt_cmdbuf_gk20a.o \ + common/sync/syncpt_cmdbuf_gv11b.o nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ os/linux/vgpu/platform_vgpu_tegra.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 774568966..4e625f501 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -161,6 +161,7 @@ srcs += common/sim.c \ common/sync/channel_sync_syncpt.c \ common/sync/channel_sync_semaphore.c \ common/sync/syncpt_cmdbuf_gk20a.c \ + common/sync/syncpt_cmdbuf_gv11b.c \ common/clock_gating/gm20b_gating_reglist.c \ common/clock_gating/gp10b_gating_reglist.c \ common/clock_gating/gv11b_gating_reglist.c \ diff --git a/drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gv11b.c b/drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gv11b.c new file mode 100644 index 000000000..9229c8572 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gv11b.c @@ -0,0 +1,191 @@ +/* + * GV11B syncpt cmdbuf + * + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. +* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "syncpt_cmdbuf_gv11b.h" + +static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm) +{ + struct gk20a *g = gk20a_from_vm(vm); + + if (vm->syncpt_ro_map_gpu_va) + return 0; + + vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(vm, + &g->syncpt_mem, g->syncpt_unit_size, + 0, gk20a_mem_flag_read_only, + false, APERTURE_SYSMEM); + + if (!vm->syncpt_ro_map_gpu_va) { + nvgpu_err(g, "failed to ro map syncpt buffer"); + return -ENOMEM; + } + + return 0; +} + +int gv11b_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf) +{ + u32 nr_pages; + int err = 0; + struct gk20a *g = c->g; + + /* + * Add ro map for complete sync point shim range in vm + * All channels sharing same vm will share same ro mapping. + * Create rw map for current channel sync point + */ + nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock); + err = set_syncpt_ro_map_gpu_va_locked(c->vm); + nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock); + if (err != 0) + return err; + + nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE); + __nvgpu_mem_create_from_phys(g, syncpt_buf, + (g->syncpt_unit_base + + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id)), + nr_pages); + syncpt_buf->gpu_va = nvgpu_gmmu_map(c->vm, syncpt_buf, + g->syncpt_size, 0, gk20a_mem_flag_none, + false, APERTURE_SYSMEM); + + if (!syncpt_buf->gpu_va) { + nvgpu_err(g, "failed to map syncpt buffer"); + nvgpu_dma_free(g, syncpt_buf); + err = -ENOMEM; + } + return err; +} + +void gv11b_free_syncpt_buf(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf) +{ + nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va); + nvgpu_dma_free(c->g, syncpt_buf); +} + +int gv11b_get_sync_ro_map(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size) +{ + struct gk20a *g = gk20a_from_vm(vm); + int err; + + nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock); + err = set_syncpt_ro_map_gpu_va_locked(vm); + nvgpu_mutex_release(&vm->syncpt_ro_map_lock); + if (err != 0) + return err; + + *base_gpuva = vm->syncpt_ro_map_gpu_va; + *sync_size = g->syncpt_size; + + return 0; +} + +void gv11b_add_syncpt_wait_cmd(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va_base) +{ + u64 gpu_va = gpu_va_base + + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); + + nvgpu_log_fn(g, " "); + + off = cmd->off + off; + + /* sema_addr_lo */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); + nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); + + /* sema_addr_hi */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); + nvgpu_mem_wr32(g, cmd->mem, off++, (gpu_va >> 32) & 0xff); + + /* payload_lo */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); + nvgpu_mem_wr32(g, cmd->mem, off++, thresh); + + /* payload_hi : ignored */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); + nvgpu_mem_wr32(g, cmd->mem, off++, 0); + + /* sema_execute : acq_strict_geq | switch_en | 32bit */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2 | (1 << 12)); +} + +u32 gv11b_get_syncpt_wait_cmd_size(void) +{ + return 10U; +} + +u32 gv11b_get_syncpt_incr_per_release(void) +{ + return 1U; +} + +void gv11b_add_syncpt_incr_cmd(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va) +{ + u32 off = cmd->off; + + nvgpu_log_fn(g, " "); + + /* sema_addr_lo */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); + nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); + + /* sema_addr_hi */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); + nvgpu_mem_wr32(g, cmd->mem, off++, (gpu_va >> 32) & 0xff); + + /* payload_lo */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); + nvgpu_mem_wr32(g, cmd->mem, off++, 0); + + /* payload_hi : ignored */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); + nvgpu_mem_wr32(g, cmd->mem, off++, 0); + + /* sema_execute : release | wfi | 32bit */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); + nvgpu_mem_wr32(g, cmd->mem, off++, + 0x1 | ((wfi_cmd ? 0x1 : 0x0) << 20)); +} + +u32 gv11b_get_syncpt_incr_cmd_size(bool wfi_cmd) +{ + return 10U; +} \ No newline at end of file diff --git a/drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gv11b.h b/drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gv11b.h new file mode 100644 index 000000000..4317daad3 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gv11b.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_SYNC_SYNCPT_CMDBUF_GV11B_H +#define NVGPU_SYNC_SYNCPT_CMDBUF_GV11B_H + +#include + +struct gk20a; +struct priv_cmd_entry; +struct nvgpu_mem; +struct channel_gk20a; +struct vm_gk20a; + +#ifdef CONFIG_TEGRA_GK20A_NVHOST + +void gv11b_add_syncpt_wait_cmd(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va); +u32 gv11b_get_syncpt_wait_cmd_size(void); +u32 gv11b_get_syncpt_incr_per_release(void); +void gv11b_add_syncpt_incr_cmd(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va); +u32 gv11b_get_syncpt_incr_cmd_size(bool wfi_cmd); +void gv11b_free_syncpt_buf(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf); + +int gv11b_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf); + +int gv11b_get_sync_ro_map(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size); + +#else + +static inline void gv11b_add_syncpt_wait_cmd(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va) +{ +} +static inline u32 gv11b_get_syncpt_wait_cmd_size(void) +{ + return 0U; +} +static inline u32 gv11b_get_syncpt_incr_per_release(void) +{ + return 0U; +} +static inline void gv11b_add_syncpt_incr_cmd(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va) +{ +} +static inline u32 gv11b_get_syncpt_incr_cmd_size(bool wfi_cmd) +{ + return 0U; +} +static inline void gv11b_free_syncpt_buf(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf) +{ +} + +static inline int gv11b_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf) +{ + return -EINVAL; +} + +static inline int gv11b_get_sync_ro_map(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size) +{ + return -EINVAL; +} + +#endif + +#endif /* NVGPU_SYNC_SYNCPT_CMDBUF_GV11B_H */ \ No newline at end of file diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index d4a67b690..9d00ad1bc 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -71,6 +71,7 @@ #include "common/nvlink/nvlink_gv100.h" #include "common/nvlink/nvlink_tu104.h" #include "common/pmu/perf/perf_gv100.h" +#include "common/sync/syncpt_cmdbuf_gv11b.h" #include "common/regops/regops_gv100.h" #include "common/fifo/runlist_gk20a.h" #include "common/fifo/runlist_gv11b.h" @@ -765,15 +766,15 @@ static const struct gpu_ops gv100_ops = { }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST - .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, - .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, - .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, - .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, - .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, - .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, + .alloc_syncpt_buf = gv11b_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_get_syncpt_incr_cmd_size, .get_syncpt_incr_per_release = - gv11b_fifo_get_syncpt_incr_per_release, - .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, + gv11b_get_syncpt_incr_per_release, + .get_sync_ro_map = gv11b_get_sync_ro_map, #endif .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 98401035d..53ebdb73f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1930,165 +1930,6 @@ void gv11b_fifo_add_sema_cmd(struct gk20a *g, } } -#ifdef CONFIG_TEGRA_GK20A_NVHOST -static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm) -{ - struct gk20a *g = gk20a_from_vm(vm); - - if (vm->syncpt_ro_map_gpu_va) - return 0; - - vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(vm, - &g->syncpt_mem, g->syncpt_unit_size, - 0, gk20a_mem_flag_read_only, - false, APERTURE_SYSMEM); - - if (!vm->syncpt_ro_map_gpu_va) { - nvgpu_err(g, "failed to ro map syncpt buffer"); - return -ENOMEM; - } - - return 0; -} - -int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, - u32 syncpt_id, struct nvgpu_mem *syncpt_buf) -{ - u32 nr_pages; - int err = 0; - struct gk20a *g = c->g; - - /* - * Add ro map for complete sync point shim range in vm - * All channels sharing same vm will share same ro mapping. - * Create rw map for current channel sync point - */ - nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock); - err = set_syncpt_ro_map_gpu_va_locked(c->vm); - nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock); - if (err != 0) - return err; - - nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE); - __nvgpu_mem_create_from_phys(g, syncpt_buf, - (g->syncpt_unit_base + - nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id)), - nr_pages); - syncpt_buf->gpu_va = nvgpu_gmmu_map(c->vm, syncpt_buf, - g->syncpt_size, 0, gk20a_mem_flag_none, - false, APERTURE_SYSMEM); - - if (!syncpt_buf->gpu_va) { - nvgpu_err(g, "failed to map syncpt buffer"); - nvgpu_dma_free(g, syncpt_buf); - err = -ENOMEM; - } - return err; -} - -void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, - struct nvgpu_mem *syncpt_buf) -{ - nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va); - nvgpu_dma_free(c->g, syncpt_buf); -} - -int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, - u64 *base_gpuva, u32 *sync_size) -{ - struct gk20a *g = gk20a_from_vm(vm); - int err; - - nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock); - err = set_syncpt_ro_map_gpu_va_locked(vm); - nvgpu_mutex_release(&vm->syncpt_ro_map_lock); - if (err != 0) - return err; - - *base_gpuva = vm->syncpt_ro_map_gpu_va; - *sync_size = g->syncpt_size; - - return 0; -} - -void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, - struct priv_cmd_entry *cmd, u32 off, - u32 id, u32 thresh, u64 gpu_va_base) -{ - u64 gpu_va = gpu_va_base + - nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); - - nvgpu_log_fn(g, " "); - - off = cmd->off + off; - - /* sema_addr_lo */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); - nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffffU); - - /* sema_addr_hi */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); - nvgpu_mem_wr32(g, cmd->mem, off++, (gpu_va >> 32) & 0xff); - - /* payload_lo */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); - nvgpu_mem_wr32(g, cmd->mem, off++, thresh); - - /* payload_hi : ignored */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); - nvgpu_mem_wr32(g, cmd->mem, off++, 0); - - /* sema_execute : acq_strict_geq | switch_en | 32bit */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2 | (1 << 12)); -} - -u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) -{ - return 10; -} - -u32 gv11b_fifo_get_syncpt_incr_per_release(void) -{ - return 1; -} - -void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, - bool wfi_cmd, struct priv_cmd_entry *cmd, - u32 id, u64 gpu_va) -{ - u32 off = cmd->off; - - nvgpu_log_fn(g, " "); - - /* sema_addr_lo */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017); - nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffffU); - - /* sema_addr_hi */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018); - nvgpu_mem_wr32(g, cmd->mem, off++, (gpu_va >> 32) & 0xff); - - /* payload_lo */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019); - nvgpu_mem_wr32(g, cmd->mem, off++, 0); - - /* payload_hi : ignored */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a); - nvgpu_mem_wr32(g, cmd->mem, off++, 0); - - /* sema_execute : release | wfi | 32bit */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b); - nvgpu_mem_wr32(g, cmd->mem, off++, - 0x1 | ((wfi_cmd ? 0x1 : 0x0) << 20)); -} - -u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) -{ - return 10; -} -#endif /* CONFIG_TEGRA_GK20A_NVHOST */ - int gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 894079909..c5bf0aaa6 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -100,27 +100,12 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg); void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg); -int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, - u32 syncpt_id, struct nvgpu_mem *syncpt_buf); -void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, - struct nvgpu_mem *syncpt_buf); -int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, - u64 *base_gpuva, u32 *sync_size); u32 gv11b_fifo_get_sema_wait_cmd_size(void); u32 gv11b_fifo_get_sema_incr_cmd_size(void); void gv11b_fifo_add_sema_cmd(struct gk20a *g, struct nvgpu_semaphore *s, u64 sema_va, struct priv_cmd_entry *cmd, u32 off, bool acquire, bool wfi); -void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, - struct priv_cmd_entry *cmd, u32 off, - u32 id, u32 thresh, u64 gpu_va_base); -u32 gv11b_fifo_get_syncpt_wait_cmd_size(void); -u32 gv11b_fifo_get_syncpt_incr_per_release(void); -void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, - bool wfi_cmd, struct priv_cmd_entry *cmd, - u32 id, u64 gpu_va_base); -u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); int gv11b_init_fifo_setup_hw(struct gk20a *g); void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index d58ca7338..2a79b6e9d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -62,6 +62,7 @@ #include "common/falcon/falcon_gk20a.h" #include "common/top/top_gm20b.h" #include "common/top/top_gp10b.h" +#include "common/sync/syncpt_cmdbuf_gv11b.h" #include "common/regops/regops_gv11b.h" #include "common/fifo/runlist_gk20a.h" #include "common/fifo/runlist_gv11b.h" @@ -718,15 +719,15 @@ static const struct gpu_ops gv11b_ops = { }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST - .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, - .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, - .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, - .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, - .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, - .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, + .alloc_syncpt_buf = gv11b_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_get_syncpt_incr_cmd_size, .get_syncpt_incr_per_release = - gv11b_fifo_get_syncpt_incr_per_release, - .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, + gv11b_get_syncpt_incr_per_release, + .get_sync_ro_map = gv11b_get_sync_ro_map, #endif .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 6125c6018..23369f86f 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -76,6 +76,7 @@ #include "common/top/top_gp10b.h" #include "common/nvlink/nvlink_gv100.h" #include "common/nvlink/nvlink_tu104.h" +#include "common/sync/syncpt_cmdbuf_gv11b.h" #include "common/regops/regops_tu104.h" #include "common/fifo/runlist_gk20a.h" #include "common/fifo/runlist_gv11b.h" @@ -795,15 +796,15 @@ static const struct gpu_ops tu104_ops = { }, .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST - .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, - .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, - .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, - .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, - .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, - .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, + .alloc_syncpt_buf = gv11b_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_get_syncpt_incr_cmd_size, .get_syncpt_incr_per_release = - gv11b_fifo_get_syncpt_incr_per_release, - .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, + gv11b_get_syncpt_incr_per_release, + .get_sync_ro_map = gv11b_get_sync_ro_map, #endif .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 294424d20..3a44c8a52 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -40,6 +40,7 @@ #include "common/ltc/ltc_gv11b.h" #include "common/fuse/fuse_gm20b.h" #include "common/fuse/fuse_gp10b.h" +#include "common/sync/syncpt_cmdbuf_gv11b.h" #include "common/regops/regops_gv11b.h" #include "common/fifo/runlist_gv11b.h" @@ -489,12 +490,12 @@ static const struct gpu_ops vgpu_gv11b_ops = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, .free_syncpt_buf = vgpu_gv11b_fifo_free_syncpt_buf, - .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, - .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_wait_cmd = gv11b_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_get_syncpt_wait_cmd_size, .get_syncpt_incr_per_release = - gv11b_fifo_get_syncpt_incr_per_release, - .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, - .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, + gv11b_get_syncpt_incr_per_release, + .add_syncpt_incr_cmd = gv11b_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_get_syncpt_incr_cmd_size, .get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map, #endif .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size,