diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h index 973e7673a..b532c5a72 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,116 +59,32 @@ #include #include -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} +#define bus_bar0_window_r() (0x00001700U) +#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) +#define bus_bar0_window_target_vid_mem_f() (0x0U) +#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) +#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) +#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) +#define bus_bar1_block_r() (0x00001704U) +#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar1_block_target_vid_mem_f() (0x0U) +#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar1_block_mode_virtual_f() (0x80000000U) +#define bus_bar2_block_r() (0x00001714U) +#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar2_block_target_vid_mem_f() (0x0U) +#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar2_block_mode_virtual_f() (0x80000000U) +#define bus_bar1_block_ptr_shift_v() (0x0000000cU) +#define bus_bar2_block_ptr_shift_v() (0x0000000cU) +#define bus_intr_0_r() (0x00001100U) +#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U) +#define bus_intr_en_0_r() (0x00001140U) +#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h index 24527fb9d..121c22db6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,148 +59,42 @@ #include #include -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000080U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000080U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_in_use_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_runlist_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 ccsr_channel_status_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acquire_v(void) -{ - return 0x00000003U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_v(void) -{ - return 0x00000005U; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void) -{ - return 0x00000006U; -} -static inline u32 ccsr_channel_status_on_eng_v(void) -{ - return 0x00000007U; -} -static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void) -{ - return 0x00000008U; -} -static inline u32 ccsr_channel_status_on_eng_pending_v(void) -{ - return 0x00000009U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ccsr_channel_busy_true_v(void) -{ - return 0x00000001U; -} +#define ccsr_channel_inst_r(i)\ + (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel_inst__size_1_v() (0x00000080U) +#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define ccsr_channel_inst_target_vid_mem_f() (0x0U) +#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) +#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) +#define ccsr_channel_inst_bind_false_f() (0x0U) +#define ccsr_channel_inst_bind_true_f() (0x80000000U) +#define ccsr_channel_r(i)\ + (nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel__size_1_v() (0x00000080U) +#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) +#define ccsr_channel_enable_in_use_v() (0x00000001U) +#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) +#define ccsr_channel_enable_set_true_f() (0x400U) +#define ccsr_channel_enable_clr_true_f() (0x800U) +#define ccsr_channel_runlist_f(v) (((v)&0xfU) << 16U) +#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) +#define ccsr_channel_status_idle_v() (0x00000000U) +#define ccsr_channel_status_pending_v() (0x00000001U) +#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U) +#define ccsr_channel_status_pending_acquire_v() (0x00000003U) +#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U) +#define ccsr_channel_status_on_pbdma_v() (0x00000005U) +#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U) +#define ccsr_channel_status_on_eng_v() (0x00000007U) +#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U) +#define ccsr_channel_status_on_eng_pending_v() (0x00000009U) +#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU) +#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU) +#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU) +#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU) +#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU) +#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) +#define ccsr_channel_next_true_v() (0x00000001U) +#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U) +#define ccsr_channel_busy_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h index e398d08dd..c73232aad 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ce2_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,11 @@ #include #include -static inline u32 ce2_intr_status_r(void) -{ - return 0x00106908U; -} -static inline u32 ce2_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce2_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} +#define ce2_intr_status_r() (0x00106908U) +#define ce2_intr_status_blockpipe_pending_f() (0x1U) +#define ce2_intr_status_blockpipe_reset_f() (0x1U) +#define ce2_intr_status_nonblockpipe_pending_f() (0x2U) +#define ce2_intr_status_nonblockpipe_reset_f() (0x2U) +#define ce2_intr_status_launcherr_pending_f() (0x4U) +#define ce2_intr_status_launcherr_reset_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h index 800424915..c5f8791d1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,396 +59,129 @@ #include #include -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_gpccs_header_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000acU; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeefU; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return U32(0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000aU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000bU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000dU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000U; -} +#define ctxsw_prog_fecs_header_v() (0x00000100U) +#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) +#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) +#define ctxsw_prog_main_image_patch_count_o() (0x00000010U) +#define ctxsw_prog_main_image_context_id_o() (0x000000f0U) +#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U) +#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U) +#define ctxsw_prog_main_image_zcull_o() (0x0000001cU) +#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U) +#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U) +#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U) +#define ctxsw_prog_main_image_pm_o() (0x00000028U) +#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U) +#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U) +#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) +#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) +#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) +#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) +#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) +#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) +#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) +#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) +#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) +#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) +#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U) +#define ctxsw_prog_local_magic_value_o() (0x000000fcU) +#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU) +#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU) +#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU) +#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U) +#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\ + (0x00000005U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\ + (0x00000004U) +#define ctxsw_prog_extended_num_smpc_quadrants_v() (0x00000004U) +#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ + (((r) >> 0U) & 0x3U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U) +#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U) +#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U) +#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU) +#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U) +#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\ + (((v)&0xffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\ + (U32(0xfffffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m()\ + (U32(0x3U) << 28U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()\ + (0x0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f()\ + (0x20000000U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f()\ + (0x30000000U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U) +#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U) +#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U) +#define ctxsw_prog_record_timestamp_magic_value_lo_v_value_v() (0x00000000U) +#define ctxsw_prog_record_timestamp_magic_value_hi_o() (0x00000004U) +#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v() (0x600dbeefU) +#define ctxsw_prog_record_timestamp_context_id_o() (0x00000008U) +#define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU) +#define ctxsw_prog_record_timestamp_new_context_id_o() (0x00000010U) +#define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U) +#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U) +#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\ + (((r) >> 0U) & 0xffffffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\ + (0x00000001U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f()\ + (0x1000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v() (0x00000002U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f() (0x2000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v()\ + (0x0000000aU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f() (0xa000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v()\ + (0x0000000bU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f()\ + (0xb000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v()\ + (0x0000000cU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f()\ + (0xc000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v()\ + (0x0000000dU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f()\ + (0xd000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v() (0x00000003U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f() (0x3000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v()\ + (0x00000004U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f()\ + (0x4000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v()\ + (0x00000005U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f()\ + (0x5000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\ + (0x000000ffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\ + (0xff000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h index 13c5468d1..f27f10779 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,504 +59,134 @@ #include #include -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} +#define falcon_falcon_irqsset_r() (0x00000000U) +#define falcon_falcon_irqsset_swgen0_set_f() (0x40U) +#define falcon_falcon_irqsclr_r() (0x00000004U) +#define falcon_falcon_irqstat_r() (0x00000008U) +#define falcon_falcon_irqstat_halt_true_f() (0x10U) +#define falcon_falcon_irqstat_exterr_true_f() (0x20U) +#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) +#define falcon_falcon_irqmode_r() (0x0000000cU) +#define falcon_falcon_irqmset_r() (0x00000010U) +#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_r() (0x00000014U) +#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqmask_r() (0x00000018U) +#define falcon_falcon_irqdest_r() (0x0000001cU) +#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define falcon_falcon_curctx_r() (0x00000050U) +#define falcon_falcon_nxtctx_r() (0x00000054U) +#define falcon_falcon_mailbox0_r() (0x00000040U) +#define falcon_falcon_mailbox1_r() (0x00000044U) +#define falcon_falcon_itfen_r() (0x00000048U) +#define falcon_falcon_itfen_ctxen_enable_f() (0x1U) +#define falcon_falcon_idlestate_r() (0x0000004cU) +#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define falcon_falcon_os_r() (0x00000080U) +#define falcon_falcon_engctl_r() (0x000000a4U) +#define falcon_falcon_cpuctl_r() (0x00000100U) +#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) +#define falcon_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) +#define falcon_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_bootvec_r() (0x00000104U) +#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define falcon_falcon_dmactl_r() (0x0000010cU) +#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_hwcfg_r() (0x00000108U) +#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define falcon_falcon_dmatrfbase_r() (0x00000110U) +#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) +#define falcon_falcon_dmatrfcmd_r() (0x00000118U) +#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) +#define falcon_falcon_imstat_r() (0x00000144U) +#define falcon_falcon_traceidx_r() (0x00000148U) +#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) +#define falcon_falcon_traceidx_idx_v(r) (((r) >> 0U) & 0xffU) +#define falcon_falcon_tracepc_r() (0x0000014cU) +#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) +#define falcon_falcon_exterraddr_r() (0x0010a168U) +#define falcon_falcon_exterrstat_r() (0x0010a16cU) +#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) +#define falcon_falcon_icd_cmd_r() (0x00000200U) +#define falcon_falcon_icd_cmd_opc_s() (4U) +#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define falcon_falcon_icd_rdata_r() (0x0000020cU) +#define falcon_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define falcon_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_debug1_r() (0x00000090U) +#define falcon_falcon_debug1_ctxsw_mode_s() (1U) +#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define falcon_falcon_debuginfo_r() (0x00000094U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h index aa77b252f..d55658c9d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,208 +59,55 @@ #include #include -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} +#define fb_mmu_ctrl_r() (0x00100c80U) +#define fb_mmu_ctrl_vm_pg_size_f(v) (((v)&0x1U) << 0U) +#define fb_mmu_ctrl_vm_pg_size_128kb_f() (0x0U) +#define fb_mmu_ctrl_vm_pg_size_64kb_f() (0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) +#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) +#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) +#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) +#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_invalidate_r() (0x00100cbcU) +#define fb_mmu_invalidate_all_va_true_f() (0x1U) +#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) +#define fb_mmu_invalidate_trigger_s() (1U) +#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) +#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) +#define fb_mmu_debug_wr_r() (0x00100cc8U) +#define fb_mmu_debug_wr_aperture_s() (2U) +#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_wr_vol_false_f() (0x0U) +#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) +#define fb_mmu_debug_wr_vol_true_f() (0x4U) +#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_rd_r() (0x00100cccU) +#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_rd_vol_false_f() (0x0U) +#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_ctrl_r() (0x00100cc4U) +#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_enabled_f() (0x10000U) +#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U) +#define fb_mmu_vpr_info_r() (0x00100cd0U) +#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U) +#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U) +#define fb_niso_flush_sysmem_addr_r() (0x00100c10U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h index f54637ad9..1ab73497f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,572 +59,162 @@ #include #include -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_runlist_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002310U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 fifo_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 fifo_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_eng_timeout_r(void) -{ - return 0x00002a0cU; -} -static inline u32 fifo_eng_timeout_period_max_f(void) -{ - return 0x7fffffffU; -} -static inline u32 fifo_eng_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_eng_timeout_detection_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_pio_error_pending_f(void) -{ - return 0x10U; -} -static inline u32 fifo_intr_0_pio_error_reset_f(void) -{ - return 0x10U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x1fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return U32(0x3fffffffU) << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_pb_timeout_r(void) -{ - return 0x00002a08U; -} -static inline u32 fifo_pb_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} +#define fifo_bar1_base_r() (0x00002254U) +#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) +#define fifo_bar1_base_valid_false_f() (0x0U) +#define fifo_bar1_base_valid_true_f() (0x10000000U) +#define fifo_runlist_base_r() (0x00002270U) +#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_runlist_base_target_vid_mem_f() (0x0U) +#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) +#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) +#define fifo_runlist_r() (0x00002274U) +#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) +#define fifo_eng_runlist_base_r(i)\ + (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist_base__size_1_v() (0x00000001U) +#define fifo_eng_runlist_r(i)\ + (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist__size_1_v() (0x00000001U) +#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) +#define fifo_eng_runlist_length_max_v() (0x0000ffffU) +#define fifo_eng_runlist_pending_true_f() (0x100000U) +#define fifo_runlist_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x00002310U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_runlist_timeslice_timeout_128_f() (0x80U) +#define fifo_runlist_timeslice_timescale_3_f() (0x3000U) +#define fifo_runlist_timeslice_enable_true_f() (0x10000000U) +#define fifo_eng_timeout_r() (0x00002a0cU) +#define fifo_eng_timeout_period_max_f() (0x7fffffffU) +#define fifo_eng_timeout_detection_enabled_f() (0x80000000U) +#define fifo_eng_timeout_detection_disabled_f() (0x0U) +#define fifo_pb_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pb_timeslice_timeout_16_f() (0x10U) +#define fifo_pb_timeslice_timescale_0_f() (0x0U) +#define fifo_pb_timeslice_enable_true_f() (0x10000000U) +#define fifo_pbdma_map_r(i)\ + (nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_0_r() (0x00002100U) +#define fifo_intr_0_bind_error_pending_f() (0x1U) +#define fifo_intr_0_bind_error_reset_f() (0x1U) +#define fifo_intr_0_pio_error_pending_f() (0x10U) +#define fifo_intr_0_pio_error_reset_f() (0x10U) +#define fifo_intr_0_sched_error_pending_f() (0x100U) +#define fifo_intr_0_sched_error_reset_f() (0x100U) +#define fifo_intr_0_chsw_error_pending_f() (0x10000U) +#define fifo_intr_0_chsw_error_reset_f() (0x10000U) +#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U) +#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U) +#define fifo_intr_0_lb_error_pending_f() (0x1000000U) +#define fifo_intr_0_lb_error_reset_f() (0x1000000U) +#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U) +#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U) +#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U) +#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U) +#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) +#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) +#define fifo_intr_en_0_r() (0x00002140U) +#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) +#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) +#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) +#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) +#define fifo_intr_en_1_r() (0x00002528U) +#define fifo_intr_bind_error_r() (0x0000252cU) +#define fifo_intr_sched_error_r() (0x0000254cU) +#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) +#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) +#define fifo_intr_chsw_error_r() (0x0000256cU) +#define fifo_intr_mmu_fault_id_r() (0x0000259cU) +#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U) +#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U) +#define fifo_intr_mmu_fault_inst_r(i)\ + (nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU) +#define fifo_intr_mmu_fault_lo_r(i)\ + (nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_hi_r(i)\ + (nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_r(i)\ + (nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0xfU) +#define fifo_intr_mmu_fault_info_write_v(r) (((r) >> 7U) & 0x1U) +#define fifo_intr_mmu_fault_info_engine_subid_v(r) (((r) >> 6U) & 0x1U) +#define fifo_intr_mmu_fault_info_engine_subid_gpc_v() (0x00000000U) +#define fifo_intr_mmu_fault_info_engine_subid_hub_v() (0x00000001U) +#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x1fU) +#define fifo_intr_pbdma_id_r() (0x000025a0U) +#define fifo_intr_pbdma_id_status_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_pbdma_id_status_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U) +#define fifo_intr_runlist_r() (0x00002a00U) +#define fifo_fb_timeout_r() (0x00002a04U) +#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U) +#define fifo_fb_timeout_period_max_f() (0x3fffffffU) +#define fifo_pb_timeout_r() (0x00002a08U) +#define fifo_pb_timeout_detection_enabled_f() (0x80000000U) +#define fifo_error_sched_disable_r() (0x0000262cU) +#define fifo_sched_disable_r() (0x00002630U) +#define fifo_sched_disable_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_sched_disable_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_sched_disable_true_v() (0x00000001U) +#define fifo_preempt_r() (0x00002634U) +#define fifo_preempt_pending_true_f() (0x100000U) +#define fifo_preempt_type_channel_f() (0x0U) +#define fifo_preempt_type_tsg_f() (0x1000000U) +#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) +#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) +#define fifo_trigger_mmu_fault_r(i)\ + (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) +#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) +#define fifo_engine_status_r(i)\ + (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_engine_status__size_1_v() (0x00000002U) +#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_engine_status_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U) +#define fifo_engine_status_ctx_status_valid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U) +#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U) +#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U) +#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_engine_status_next_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U) +#define fifo_engine_status_faulted_true_v() (0x00000001U) +#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U) +#define fifo_engine_status_engine_idle_v() (0x00000000U) +#define fifo_engine_status_engine_busy_v() (0x00000001U) +#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U) +#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U) +#define fifo_pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pbdma_status__size_1_v() (0x00000001U) +#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_pbdma_status_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U) +#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U) +#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U) +#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h index 5ad35f4d3..6f7a2d3ab 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_flush_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,132 +59,36 @@ #include #include -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} +#define flush_l2_system_invalidate_r() (0x00070004U) +#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U) +#define flush_l2_system_invalidate_pending_busy_f() (0x1U) +#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U) +#define flush_l2_flush_dirty_r() (0x00070010U) +#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U) +#define flush_l2_flush_dirty_pending_empty_f() (0x0U) +#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U) +#define flush_l2_flush_dirty_pending_busy_f() (0x1U) +#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U) +#define flush_l2_flush_dirty_outstanding_false_f() (0x0U) +#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U) +#define flush_l2_clean_comptags_r() (0x0007000cU) +#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U) +#define flush_l2_clean_comptags_pending_empty_f() (0x0U) +#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U) +#define flush_l2_clean_comptags_pending_busy_f() (0x1U) +#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U) +#define flush_l2_clean_comptags_outstanding_false_f() (0x0U) +#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U) +#define flush_fb_flush_r() (0x00070000U) +#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_fb_flush_pending_busy_v() (0x00000001U) +#define flush_fb_flush_pending_busy_f() (0x1U) +#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_fb_flush_outstanding_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h index ad80c4b88..72906b832 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,228 +59,60 @@ #include #include -static inline u32 gmmu_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_big_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_size_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_size_full_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_small_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_vol_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_small_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_vol_big_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_small_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_small_sys_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_privilege_true_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_address_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_address_vid_f(u32 v) -{ - return (v & 0x1ffffffU) << 4U; -} -static inline u32 gmmu_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_vol_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_vol_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_read_only_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_write_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_write_disable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gmmu_pte_read_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_read_disable_true_f(void) -{ - return 0x40000000U; -} -static inline u32 gmmu_pte_comptagline_s(void) -{ - return 17U; -} -static inline u32 gmmu_pte_comptagline_f(u32 v) -{ - return (v & 0x1ffffU) << 12U; -} -static inline u32 gmmu_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} +#define gmmu_pde_aperture_big_w() (0U) +#define gmmu_pde_aperture_big_invalid_f() (0x0U) +#define gmmu_pde_aperture_big_video_memory_f() (0x1U) +#define gmmu_pde_aperture_big_sys_mem_coh_f() (0x2U) +#define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U) +#define gmmu_pde_size_w() (0U) +#define gmmu_pde_size_full_f() (0x0U) +#define gmmu_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_pde_address_big_sys_w() (0U) +#define gmmu_pde_aperture_small_w() (1U) +#define gmmu_pde_aperture_small_invalid_f() (0x0U) +#define gmmu_pde_aperture_small_video_memory_f() (0x1U) +#define gmmu_pde_aperture_small_sys_mem_coh_f() (0x2U) +#define gmmu_pde_aperture_small_sys_mem_ncoh_f() (0x3U) +#define gmmu_pde_vol_small_w() (1U) +#define gmmu_pde_vol_small_true_f() (0x4U) +#define gmmu_pde_vol_small_false_f() (0x0U) +#define gmmu_pde_vol_big_w() (1U) +#define gmmu_pde_vol_big_true_f() (0x8U) +#define gmmu_pde_vol_big_false_f() (0x0U) +#define gmmu_pde_address_small_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_pde_address_small_sys_w() (1U) +#define gmmu_pde_address_shift_v() (0x0000000cU) +#define gmmu_pde__size_v() (0x00000008U) +#define gmmu_pte__size_v() (0x00000008U) +#define gmmu_pte_valid_w() (0U) +#define gmmu_pte_valid_true_f() (0x1U) +#define gmmu_pte_valid_false_f() (0x0U) +#define gmmu_pte_privilege_w() (0U) +#define gmmu_pte_privilege_true_f() (0x2U) +#define gmmu_pte_privilege_false_f() (0x0U) +#define gmmu_pte_address_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_pte_address_sys_w() (0U) +#define gmmu_pte_address_vid_f(v) (((v)&0x1ffffffU) << 4U) +#define gmmu_pte_address_vid_w() (0U) +#define gmmu_pte_vol_w() (1U) +#define gmmu_pte_vol_true_f() (0x1U) +#define gmmu_pte_vol_false_f() (0x0U) +#define gmmu_pte_aperture_w() (1U) +#define gmmu_pte_aperture_video_memory_f() (0x0U) +#define gmmu_pte_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_pte_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_pte_read_only_w() (0U) +#define gmmu_pte_read_only_true_f() (0x4U) +#define gmmu_pte_write_disable_w() (1U) +#define gmmu_pte_write_disable_true_f() (0x80000000U) +#define gmmu_pte_read_disable_w() (1U) +#define gmmu_pte_read_disable_true_f() (0x40000000U) +#define gmmu_pte_comptagline_s() (17U) +#define gmmu_pte_comptagline_f(v) (((v)&0x1ffffU) << 12U) +#define gmmu_pte_comptagline_w() (1U) +#define gmmu_pte_address_shift_v() (0x0000000cU) +#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) +#define gmmu_pte_kind_w() (1U) +#define gmmu_pte_kind_invalid_v() (0x000000ffU) +#define gmmu_pte_kind_pitch_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h index 8f9e0d4aa..9bde3a575 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,3752 +59,991 @@ #include #include -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_timeout_not_pending_f(void) -{ - return 0x0U; -} -static inline u32 gr_intr_semaphore_timeout_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_intr_semaphore_timeout_reset_f(void) -{ - return 0x4U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_on_status_r(void) -{ - return 0x00404150U; -} -static inline u32 gr_pri_fe_go_idle_check_r(void) -{ - return 0x00404158U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_irqsset_r(void) -{ - return 0x00409000U; -} -static inline u32 gr_fecs_irqsclear_r(void) -{ - return 0x00409004U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_irqsset_r(void) -{ - return 0x0041a000U; -} -static inline u32 gr_gpcs_gpccs_irqsclr_r(void) -{ - return 0x0041a004U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409820U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return U32(0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0x7ffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000062U; -} -static inline u32 gr_pd_pagepool_r(void) -{ - return 0x004064ccU; -} -static inline u32 gr_pd_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_pd_alpha_ratio_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_alpha_ratio_table__size_1_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_alpha_ratio_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_pd_beta_ratio_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406c00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_beta_ratio_table__size_1_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_beta_ratio_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32(i, 0U)); -} -static inline u32 gr_gpccs_rc_lane_size__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_active_tpcs_r(void) -{ - return 0x00500c08U; -} -static inline u32 gr_gpc0_gpm_pd_active_tpcs_num_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_gpm_sd_active_tpcs_r(void) -{ - return 0x00500c8cU; -} -static inline u32 gr_gpc0_gpm_sd_active_tpcs_num_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_r(void) -{ - return 0x005044e8U; -} -static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_m(void) -{ - return U32(0xfffU) << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_default_v(void) -{ - return 0x00000240U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_size_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_start_offset_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_m(void) -{ - return U32(0xfffU) << 16U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_default_v(void) -{ - return 0x00000648U; -} -static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return U32(0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_r(void) -{ - return 0x00418808U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_r(void) -{ - return 0x0041880cU; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return U32(0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_fbps_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_fbps_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_r(void) -{ - return 0x00504670U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_r(void) -{ - return 0x00504674U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_r(void) -{ - return 0x0050467cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_r(void) -{ - return 0x00504680U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_r(void) -{ - return 0x00504684U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_r(void) -{ - return 0x00504688U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_r(void) -{ - return 0x0050468cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_r(void) -{ - return 0x00504690U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_l1c_dbg_r(void) -{ - return 0x005044b0U; -} -static inline u32 gr_gpc0_tpc0_l1c_dbg_cya15_en_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_r(void) -{ - return 0x00419ec8U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m(void) -{ - return U32(0xffU) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} +#define gr_intr_r() (0x00400100U) +#define gr_intr_notify_pending_f() (0x1U) +#define gr_intr_notify_reset_f() (0x1U) +#define gr_intr_semaphore_pending_f() (0x2U) +#define gr_intr_semaphore_reset_f() (0x2U) +#define gr_intr_semaphore_timeout_not_pending_f() (0x0U) +#define gr_intr_semaphore_timeout_pending_f() (0x4U) +#define gr_intr_semaphore_timeout_reset_f() (0x4U) +#define gr_intr_illegal_method_pending_f() (0x10U) +#define gr_intr_illegal_method_reset_f() (0x10U) +#define gr_intr_illegal_notify_pending_f() (0x40U) +#define gr_intr_illegal_notify_reset_f() (0x40U) +#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) +#define gr_intr_firmware_method_pending_f() (0x100U) +#define gr_intr_firmware_method_reset_f() (0x100U) +#define gr_intr_illegal_class_pending_f() (0x20U) +#define gr_intr_illegal_class_reset_f() (0x20U) +#define gr_intr_fecs_error_pending_f() (0x80000U) +#define gr_intr_fecs_error_reset_f() (0x80000U) +#define gr_intr_class_error_pending_f() (0x100000U) +#define gr_intr_class_error_reset_f() (0x100000U) +#define gr_intr_exception_pending_f() (0x200000U) +#define gr_intr_exception_reset_f() (0x200000U) +#define gr_fecs_intr_r() (0x00400144U) +#define gr_class_error_r() (0x00400110U) +#define gr_class_error_code_v(r) (((r) >> 0U) & 0xffffU) +#define gr_intr_nonstall_r() (0x00400120U) +#define gr_intr_nonstall_trap_pending_f() (0x2U) +#define gr_intr_en_r() (0x0040013cU) +#define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception1_r() (0x00400118U) +#define gr_exception1_gpc_0_pending_f() (0x1U) +#define gr_exception2_r() (0x0040011cU) +#define gr_exception_en_r() (0x00400138U) +#define gr_exception_en_fe_m() (U32(0x1U) << 0U) +#define gr_exception1_en_r() (0x00400130U) +#define gr_exception2_en_r() (0x00400134U) +#define gr_gpfifo_ctl_r() (0x00400500U) +#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) +#define gr_gpfifo_ctl_access_disabled_f() (0x0U) +#define gr_gpfifo_ctl_access_enabled_f() (0x1U) +#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) +#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) +#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) +#define gr_gpfifo_status_r() (0x00400504U) +#define gr_trapped_addr_r() (0x00400704U) +#define gr_trapped_addr_mthd_v(r) (((r) >> 2U) & 0xfffU) +#define gr_trapped_addr_subch_v(r) (((r) >> 16U) & 0x7U) +#define gr_trapped_addr_mme_generated_v(r) (((r) >> 20U) & 0x1U) +#define gr_trapped_addr_datahigh_v(r) (((r) >> 24U) & 0x1U) +#define gr_trapped_addr_priv_v(r) (((r) >> 28U) & 0x1U) +#define gr_trapped_addr_status_v(r) (((r) >> 31U) & 0x1U) +#define gr_trapped_data_lo_r() (0x00400708U) +#define gr_trapped_data_hi_r() (0x0040070cU) +#define gr_trapped_data_mme_r() (0x00400710U) +#define gr_trapped_data_mme_pc_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_status_r() (0x00400700U) +#define gr_status_fe_method_upper_v(r) (((r) >> 1U) & 0x1U) +#define gr_status_fe_method_lower_v(r) (((r) >> 2U) & 0x1U) +#define gr_status_fe_method_lower_idle_v() (0x00000000U) +#define gr_status_fe_gi_v(r) (((r) >> 21U) & 0x1U) +#define gr_status_mask_r() (0x00400610U) +#define gr_status_1_r() (0x00400604U) +#define gr_status_2_r() (0x00400608U) +#define gr_engine_status_r() (0x0040060cU) +#define gr_engine_status_value_busy_f() (0x1U) +#define gr_pri_be0_becs_be_exception_r() (0x00410204U) +#define gr_pri_be0_becs_be_exception_en_r() (0x00410208U) +#define gr_pri_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_pri_gpc0_gpccs_gpc_exception_en_r() (0x00502c94U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_activity_0_r() (0x00400380U) +#define gr_activity_1_r() (0x00400384U) +#define gr_activity_2_r() (0x00400388U) +#define gr_activity_4_r() (0x00400390U) +#define gr_pri_gpc0_gcc_dbg_r() (0x00501000U) +#define gr_pri_gpcs_gcc_dbg_r() (0x00419000U) +#define gr_pri_gpcs_gcc_dbg_invalidate_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cache_control_r() (0x005046a4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_r() (0x00419ea4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m() (U32(0x1U) << 0U) +#define gr_pri_sked_activity_r() (0x00407054U) +#define gr_pri_gpc0_gpccs_gpc_activity0_r() (0x00502c80U) +#define gr_pri_gpc0_gpccs_gpc_activity1_r() (0x00502c84U) +#define gr_pri_gpc0_gpccs_gpc_activity2_r() (0x00502c88U) +#define gr_pri_gpc0_gpccs_gpc_activity3_r() (0x00502c8cU) +#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() (0x00504500U) +#define gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r() (0x00501d00U) +#define gr_pri_gpcs_gpccs_gpc_activity_0_r() (0x0041ac80U) +#define gr_pri_gpcs_gpccs_gpc_activity_1_r() (0x0041ac84U) +#define gr_pri_gpcs_gpccs_gpc_activity_2_r() (0x0041ac88U) +#define gr_pri_gpcs_gpccs_gpc_activity_3_r() (0x0041ac8cU) +#define gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r() (0x0041c500U) +#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r() (0x00419d00U) +#define gr_pri_be0_becs_be_activity0_r() (0x00410200U) +#define gr_pri_bes_becs_be_activity0_r() (0x00408a00U) +#define gr_pri_ds_mpipe_status_r() (0x00405858U) +#define gr_pri_fe_go_idle_on_status_r() (0x00404150U) +#define gr_pri_fe_go_idle_check_r() (0x00404158U) +#define gr_pri_fe_go_idle_info_r() (0x00404194U) +#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r() (0x00504238U) +#define gr_pri_be0_crop_status1_r() (0x00410134U) +#define gr_pri_bes_crop_status1_r() (0x00408934U) +#define gr_pri_be0_zrop_status_r() (0x00410048U) +#define gr_pri_be0_zrop_status2_r() (0x0041004cU) +#define gr_pri_bes_zrop_status_r() (0x00408848U) +#define gr_pri_bes_zrop_status2_r() (0x0040884cU) +#define gr_pipe_bundle_address_r() (0x00400200U) +#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pipe_bundle_data_r() (0x00400204U) +#define gr_pipe_bundle_config_r() (0x00400208U) +#define gr_pipe_bundle_config_override_pipe_mode_disabled_f() (0x0U) +#define gr_pipe_bundle_config_override_pipe_mode_enabled_f() (0x80000000U) +#define gr_fe_hww_esr_r() (0x00404000U) +#define gr_fe_hww_esr_reset_active_f() (0x40000000U) +#define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) +#define gr_fe_go_idle_timeout_r() (0x00404154U) +#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) +#define gr_fe_go_idle_timeout_count_prod_f() (0x800U) +#define gr_fe_object_table_r(i)\ + (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) +#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_mme_hww_esr_r() (0x00404490U) +#define gr_mme_hww_esr_reset_active_f() (0x40000000U) +#define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) +#define gr_memfmt_hww_esr_r() (0x00404600U) +#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) +#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) +#define gr_fecs_cpuctl_r() (0x00409100U) +#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_dmactl_r() (0x0040910cU) +#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_fecs_os_r() (0x00409080U) +#define gr_fecs_idlestate_r() (0x0040904cU) +#define gr_fecs_mailbox0_r() (0x00409040U) +#define gr_fecs_mailbox1_r() (0x00409044U) +#define gr_fecs_irqstat_r() (0x00409008U) +#define gr_fecs_irqmode_r() (0x0040900cU) +#define gr_fecs_irqmask_r() (0x00409018U) +#define gr_fecs_irqdest_r() (0x0040901cU) +#define gr_fecs_curctx_r() (0x00409050U) +#define gr_fecs_nxtctx_r() (0x00409054U) +#define gr_fecs_engctl_r() (0x004090a4U) +#define gr_fecs_debug1_r() (0x00409090U) +#define gr_fecs_debuginfo_r() (0x00409094U) +#define gr_fecs_icd_cmd_r() (0x00409200U) +#define gr_fecs_icd_cmd_opc_s() (4U) +#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) +#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) +#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define gr_fecs_icd_rdata_r() (0x0040920cU) +#define gr_fecs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmemc_offs_s() (6U) +#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) +#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmatrfbase_r() (0x00409110U) +#define gr_fecs_dmatrfmoffs_r() (0x00409114U) +#define gr_fecs_dmatrffboffs_r() (0x0040911cU) +#define gr_fecs_dmatrfcmd_r() (0x00409118U) +#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define gr_fecs_bootvec_r() (0x00409104U) +#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_irqsset_r() (0x00409000U) +#define gr_fecs_irqsclear_r() (0x00409004U) +#define gr_fecs_falcon_hwcfg_r() (0x00409108U) +#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) +#define gr_gpcs_gpccs_irqsclr_r() (0x0041a004U) +#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) +#define gr_fecs_falcon_rm_r() (0x00409084U) +#define gr_fecs_current_ctx_r() (0x00409b00U) +#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_current_ctx_target_s() (2U) +#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_current_ctx_valid_s() (1U) +#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_current_ctx_valid_false_f() (0x0U) +#define gr_fecs_method_data_r() (0x00409500U) +#define gr_fecs_method_push_r() (0x00409504U) +#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) +#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) +#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) +#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) +#define gr_fecs_method_push_adr_wfi_golden_save_v() (0x00000009U) +#define gr_fecs_method_push_adr_restore_golden_v() (0x00000015U) +#define gr_fecs_method_push_adr_discover_zcull_image_size_v() (0x00000016U) +#define gr_fecs_method_push_adr_discover_pm_image_size_v() (0x00000025U) +#define gr_fecs_method_push_adr_discover_reglist_image_size_v() (0x00000030U) +#define gr_fecs_method_push_adr_set_reglist_bind_instance_v() (0x00000031U) +#define gr_fecs_method_push_adr_set_reglist_virtual_address_v() (0x00000032U) +#define gr_fecs_method_push_adr_stop_ctxsw_v() (0x00000038U) +#define gr_fecs_method_push_adr_start_ctxsw_v() (0x00000039U) +#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) +#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) +#define gr_fecs_host_int_status_r() (0x00409c18U) +#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) +#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) +#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) +#define gr_fecs_host_int_status_watchdog_active_f() (0x80000U) +#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_host_int_clear_r() (0x00409c20U) +#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) +#define gr_fecs_host_int_enable_r() (0x00409c24U) +#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) +#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) +#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f() (0x20000U) +#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f() (0x40000U) +#define gr_fecs_host_int_enable_watchdog_enable_f() (0x80000U) +#define gr_fecs_ctxsw_reset_ctl_r() (0x00409614U) +#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() (0x10U) +#define gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() (0x20U) +#define gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() (0x40U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() (0x100U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f() (0x400U) +#define gr_fecs_ctx_state_store_major_rev_id_r() (0x0040960cU) +#define gr_fecs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000008U) +#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) +#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) +#define gr_fecs_ctxsw_mailbox_set_r(i)\ + (nvgpu_safe_add_u32(0x00409820U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_clear_r(i)\ + (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_fs_r() (0x00409604U) +#define gr_fecs_fs_num_available_gpcs_s() (5U) +#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_fs_num_available_fbps_s() (5U) +#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) +#define gr_fecs_cfg_r() (0x00409620U) +#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_fecs_rc_lanes_r() (0x00409880U) +#define gr_fecs_rc_lanes_num_chains_s() (6U) +#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_fecs_ctxsw_status_1_r() (0x00409400U) +#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) +#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) +#define gr_fecs_new_ctx_r() (0x00409b04U) +#define gr_fecs_new_ctx_ptr_s() (28U) +#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_new_ctx_target_s() (2U) +#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_new_ctx_valid_s() (1U) +#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) +#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) +#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_arb_ctx_ptr_target_s() (2U) +#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) +#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) +#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) +#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r() (0x00502c04U) +#define gr_gpc0_gpccs_ctxsw_status_1_r() (0x00502400U) +#define gr_fecs_ctxsw_idlestate_r() (0x00409420U) +#define gr_gpc0_gpccs_ctxsw_idlestate_r() (0x00502420U) +#define gr_rstr2d_gpc_map0_r() (0x0040780cU) +#define gr_rstr2d_gpc_map1_r() (0x00407810U) +#define gr_rstr2d_gpc_map2_r() (0x00407814U) +#define gr_rstr2d_gpc_map3_r() (0x00407818U) +#define gr_rstr2d_gpc_map4_r() (0x0040781cU) +#define gr_rstr2d_gpc_map5_r() (0x00407820U) +#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) +#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_pd_hww_esr_r() (0x00406018U) +#define gr_pd_hww_esr_reset_active_f() (0x40000000U) +#define gr_pd_hww_esr_en_enable_f() (0x80000000U) +#define gr_pd_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) +#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) +#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) +#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) +#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) +#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) +#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) +#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) +#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) +#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) +#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) +#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) +#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0x7ffU) << 16U) +#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) +#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) +#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0xfffU) << 0U) +#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000100U) +#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0xfffU) << 16U) +#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) +#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000062U) +#define gr_pd_pagepool_r() (0x004064ccU) +#define gr_pd_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) +#define gr_pd_pagepool_valid_true_f() (0x80000000U) +#define gr_pd_dist_skip_table_r(i)\ + (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) +#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_pd_alpha_ratio_table_r(i)\ + (nvgpu_safe_add_u32(0x00406800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_alpha_ratio_table__size_1_v() (0x00000100U) +#define gr_pd_alpha_ratio_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_alpha_ratio_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_alpha_ratio_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_alpha_ratio_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_pd_beta_ratio_table_r(i)\ + (nvgpu_safe_add_u32(0x00406c00U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_beta_ratio_table__size_1_v() (0x00000100U) +#define gr_pd_beta_ratio_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_beta_ratio_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_beta_ratio_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_beta_ratio_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_ds_debug_r() (0x00405800U) +#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) +#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) +#define gr_ds_zbc_color_r_r() (0x00405804U) +#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_g_r() (0x00405808U) +#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_b_r() (0x0040580cU) +#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_a_r() (0x00405810U) +#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_fmt_r() (0x00405814U) +#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) +#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) +#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) +#define gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v() (0x00000004U) +#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) +#define gr_ds_zbc_z_r() (0x00405818U) +#define gr_ds_zbc_z_val_s() (32U) +#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_ds_zbc_z_val__init_v() (0x00000000U) +#define gr_ds_zbc_z_val__init_f() (0x0U) +#define gr_ds_zbc_z_fmt_r() (0x0040581cU) +#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) +#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) +#define gr_ds_zbc_tbl_index_r() (0x00405820U) +#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) +#define gr_ds_zbc_tbl_ld_r() (0x00405824U) +#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) +#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) +#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) +#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) +#define gr_ds_tga_constraintlogic_r() (0x00405830U) +#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0xfffU) << 16U) +#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xfffU) << 0U) +#define gr_ds_hww_esr_r() (0x00405840U) +#define gr_ds_hww_esr_reset_s() (1U) +#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) +#define gr_ds_hww_report_mask_r() (0x00405844U) +#define gr_ds_hww_report_mask_sph0_err_report_f() (0x1U) +#define gr_ds_hww_report_mask_sph1_err_report_f() (0x2U) +#define gr_ds_hww_report_mask_sph2_err_report_f() (0x4U) +#define gr_ds_hww_report_mask_sph3_err_report_f() (0x8U) +#define gr_ds_hww_report_mask_sph4_err_report_f() (0x10U) +#define gr_ds_hww_report_mask_sph5_err_report_f() (0x20U) +#define gr_ds_hww_report_mask_sph6_err_report_f() (0x40U) +#define gr_ds_hww_report_mask_sph7_err_report_f() (0x80U) +#define gr_ds_hww_report_mask_sph8_err_report_f() (0x100U) +#define gr_ds_hww_report_mask_sph9_err_report_f() (0x200U) +#define gr_ds_hww_report_mask_sph10_err_report_f() (0x400U) +#define gr_ds_hww_report_mask_sph11_err_report_f() (0x800U) +#define gr_ds_hww_report_mask_sph12_err_report_f() (0x1000U) +#define gr_ds_hww_report_mask_sph13_err_report_f() (0x2000U) +#define gr_ds_hww_report_mask_sph14_err_report_f() (0x4000U) +#define gr_ds_hww_report_mask_sph15_err_report_f() (0x8000U) +#define gr_ds_hww_report_mask_sph16_err_report_f() (0x10000U) +#define gr_ds_hww_report_mask_sph17_err_report_f() (0x20000U) +#define gr_ds_hww_report_mask_sph18_err_report_f() (0x40000U) +#define gr_ds_hww_report_mask_sph19_err_report_f() (0x80000U) +#define gr_ds_hww_report_mask_sph20_err_report_f() (0x100000U) +#define gr_ds_hww_report_mask_sph21_err_report_f() (0x200000U) +#define gr_ds_hww_report_mask_sph22_err_report_f() (0x400000U) +#define gr_ds_hww_report_mask_sph23_err_report_f() (0x800000U) +#define gr_ds_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_scc_bundle_cb_base_r() (0x00408004U) +#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_bundle_cb_size_r() (0x00408008U) +#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U) +#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) +#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_scc_pagepool_base_r() (0x0040800cU) +#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_pagepool_r() (0x00408010U) +#define gr_scc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) +#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) +#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000080U) +#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) +#define gr_scc_pagepool_max_valid_pages_s() (8U) +#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0xffU) << 8U) +#define gr_scc_pagepool_max_valid_pages_m() (U32(0xffU) << 8U) +#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 8U) & 0xffU) +#define gr_scc_pagepool_valid_true_f() (0x80000000U) +#define gr_scc_hww_esr_r() (0x00408030U) +#define gr_scc_hww_esr_reset_active_f() (0x40000000U) +#define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) +#define gr_cwd_fs_r() (0x00405b00U) +#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) +#define gr_gpc0_fs_gpc_r() (0x00502608U) +#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) +#define gr_gpc0_cfg_r() (0x00502620U) +#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpccs_rc_lanes_r() (0x00502880U) +#define gr_gpccs_rc_lanes_num_chains_s() (6U) +#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_rc_lane_size_r(i)\ + (nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32((i), 0U))) +#define gr_gpccs_rc_lane_size__size_1_v() (0x00000010U) +#define gr_gpccs_rc_lane_size_v_s() (24U) +#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) +#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) +#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) +#define gr_gpc0_zcull_fs_r() (0x00500910U) +#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) +#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) +#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ + (((v)&0xfU) << 0U) +#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) +#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) +#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) +#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) +#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_zcull_zcsize_r(i)\ + (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) +#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) +#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) +#define gr_gpc0_gpm_pd_active_tpcs_r() (0x00500c08U) +#define gr_gpc0_gpm_pd_active_tpcs_num_f(v) (((v)&0x7U) << 0U) +#define gr_gpc0_gpm_pd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ + (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_gpm_sd_active_tpcs_r() (0x00500c8cU) +#define gr_gpc0_gpm_sd_active_tpcs_num_f(v) (((v)&0x7U) << 0U) +#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) +#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_l1c_cfg_smid_r() (0x005044e8U) +#define gr_gpc0_tpc0_l1c_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) +#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) +#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfU) +#define gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v() (0x0000000cU) +#define gr_gpc0_ppc0_pes_vsc_strem_r() (0x00503018U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) +#define gr_gpc0_ppc0_cbm_cfg_r() (0x005030c0U) +#define gr_gpc0_ppc0_cbm_cfg_start_offset_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_cfg_start_offset_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_cfg_start_offset_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_ppc0_cbm_cfg_size_f(v) (((v)&0xfffU) << 16U) +#define gr_gpc0_ppc0_cbm_cfg_size_m() (U32(0xfffU) << 16U) +#define gr_gpc0_ppc0_cbm_cfg_size_v(r) (((r) >> 16U) & 0xfffU) +#define gr_gpc0_ppc0_cbm_cfg_size_default_v() (0x00000240U) +#define gr_gpc0_ppc0_cbm_cfg_size_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(v) (((v)&0x1U) << 28U) +#define gr_gpc0_ppc0_cbm_cfg2_r() (0x005030e4U) +#define gr_gpc0_ppc0_cbm_cfg2_start_offset_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_cfg2_size_f(v) (((v)&0xfffU) << 16U) +#define gr_gpc0_ppc0_cbm_cfg2_size_m() (U32(0xfffU) << 16U) +#define gr_gpc0_ppc0_cbm_cfg2_size_v(r) (((r) >> 16U) & 0xfffU) +#define gr_gpc0_ppc0_cbm_cfg2_size_default_v() (0x00000648U) +#define gr_gpc0_ppc0_cbm_cfg2_size_granularity_v() (0x00000020U) +#define gr_gpccs_falcon_addr_r() (0x0041a0acU) +#define gr_gpccs_falcon_addr_lsb_s() (6U) +#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_msb_s() (6U) +#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) +#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_ext_s() (12U) +#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) +#define gr_gpccs_cpuctl_r() (0x0041a100U) +#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_gpccs_dmactl_r() (0x0041a10cU) +#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_gpccs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt__size_1_v() (0x00000004U) +#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_gpccs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_setup_bundle_cb_base_r() (0x00418808U) +#define gr_gpcs_setup_bundle_cb_base_addr_39_8_s() (32U) +#define gr_gpcs_setup_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_setup_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) +#define gr_gpcs_setup_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v() (0x00000000U) +#define gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f() (0x0U) +#define gr_gpcs_setup_bundle_cb_size_r() (0x0041880cU) +#define gr_gpcs_setup_bundle_cb_size_div_256b_s() (11U) +#define gr_gpcs_setup_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_gpcs_setup_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) +#define gr_gpcs_setup_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_gpcs_setup_bundle_cb_size_div_256b_init_v() (0x00000000U) +#define gr_gpcs_setup_bundle_cb_size_div_256b_init_f() (0x0U) +#define gr_gpcs_setup_bundle_cb_size_div_256b__prod_v() (0x00000018U) +#define gr_gpcs_setup_bundle_cb_size_div_256b__prod_f() (0x18U) +#define gr_gpcs_setup_bundle_cb_size_valid_s() (1U) +#define gr_gpcs_setup_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_setup_bundle_cb_size_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_setup_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_setup_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_gpcs_setup_bundle_cb_size_valid_false_f() (0x0U) +#define gr_gpcs_setup_bundle_cb_size_valid_true_v() (0x00000001U) +#define gr_gpcs_setup_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) +#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) +#define gr_crstr_gpc_map0_r() (0x00418b08U) +#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map1_r() (0x00418b0cU) +#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map2_r() (0x00418b10U) +#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map3_r() (0x00418b14U) +#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map4_r() (0x00418b18U) +#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map5_r() (0x00418b1cU) +#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_map_table_cfg_r() (0x00418bb8U) +#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) +#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) +#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_gcc_pagepool_r() (0x00419008U) +#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) +#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) +#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f()\ + (0x20U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f()\ + (0x80U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\ + (0x200U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f()\ + (0x400U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f()\ + (0x800U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f()\ + (0x1000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f() (0x2000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f() (0x4000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f()\ + (0x8000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f()\ + (0x10000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f()\ + (0x20000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\ + (0x40000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f()\ + (0x80000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f()\ + (0x100000U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() (0x00419e4cU) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f()\ + (0x1U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f()\ + (0x40U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r() (0x00419d0cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f() (0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) +#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) +#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) +#define gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_sm_dbgr_control0_r() (0x00504610U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m() (U32(0x1U) << 0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f() (0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m() (U32(0x1U) << 1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m() (U32(0x1U) << 2U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v()\ + (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v()\ + (0x00000000U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_r() (0x00504614U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_1_r() (0x00504618U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() (0x00504624U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r() (0x00504628U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() (0x00504634U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r() (0x00504638U) +#define gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r() (0x00419e24U) +#define gr_gpc0_tpc0_sm_dbgr_status0_r() (0x0050460cU) +#define gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(r) (((r) >> 4U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_hww_global_esr_r() (0x00419e50U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f() (0x1U) +#define gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() (0x80000000U) +#define gr_gpc0_tpc0_sm_hww_global_esr_r() (0x00504650U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() (0x1U) +#define gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f() (0x2U) +#define gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f()\ + (0x8U) +#define gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f() (0x80000000U) +#define gr_gpc0_tpc0_tex_m_hww_esr_r() (0x00504224U) +#define gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f() (0x1U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_r() (0x00504648U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) +#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) +#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) +#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) +#define gr_ppcs_wwdx_map_gpc_map1_r() (0x0041bf04U) +#define gr_ppcs_wwdx_map_gpc_map2_r() (0x0041bf08U) +#define gr_ppcs_wwdx_map_gpc_map3_r() (0x0041bf0cU) +#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) +#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) +#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) +#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ + (((v)&0x1fU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ + (((v)&0x7U) << 21U) +#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) +#define gr_bes_zrop_settings_r() (0x00408850U) +#define gr_bes_zrop_settings_num_active_fbps_f(v) (((v)&0xfU) << 0U) +#define gr_bes_crop_settings_r() (0x00408958U) +#define gr_bes_crop_settings_num_active_fbps_f(v) (((v)&0xfU) << 0U) +#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) +#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) +#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) +#define gr_zcull_subregion_qty_v() (0x00000010U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r() (0x00504604U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r() (0x00504608U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r() (0x0050465cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r() (0x00504660U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r() (0x00504664U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r() (0x00504668U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r() (0x0050466cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r() (0x00504658U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_r() (0x00504670U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r() (0x00504694U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r() (0x00504730U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r() (0x00504734U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r() (0x00504738U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r() (0x0050473cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r() (0x00504740U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r() (0x00504744U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r() (0x00504748U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r() (0x0050474cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_r() (0x00504674U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_r() (0x00504678U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_r() (0x0050467cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_r() (0x00504680U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_r() (0x00504684U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_r() (0x00504688U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_r() (0x0050468cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_r() (0x00504690U) +#define gr_fe_pwr_mode_r() (0x00404170U) +#define gr_fe_pwr_mode_mode_auto_f() (0x0U) +#define gr_fe_pwr_mode_mode_force_on_f() (0x2U) +#define gr_fe_pwr_mode_req_v(r) (((r) >> 4U) & 0x1U) +#define gr_fe_pwr_mode_req_send_f() (0x10U) +#define gr_fe_pwr_mode_req_done_v() (0x00000000U) +#define gr_gpc0_tpc0_l1c_dbg_r() (0x005044b0U) +#define gr_gpc0_tpc0_l1c_dbg_cya15_en_f() (0x8000000U) +#define gr_gpcs_tpcs_sm_sch_texlock_r() (0x00419ec8U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m() (U32(0x1U) << 1U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m() (U32(0x1U) << 2U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m() (U32(0x1U) << 3U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m() (U32(0xffU) << 4U) +#define gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m() (U32(0x1U) << 16U) +#define gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_sch_macro_sched_r() (0x00419eacU) +#define gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(v) (((v)&0x1U) << 2U) +#define gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m() (U32(0x1U) << 2U) +#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m() (U32(0x1U) << 3U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m() (U32(0x1U) << 30U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h index 697a1a2d9..ca8227112 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,400 +59,128 @@ #include #include -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x001410c8U; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00141200U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017ea00U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00141104U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e8c8U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x001410c8U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e8ccU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e8d0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0001ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e8d4U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e8dcU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e91cU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017ea44U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0017ea48U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017ea58U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e924U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e828U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140828U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_intr_r(void) -{ - return 0x00140820U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e820U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x00141020U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e910U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e914U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x00140910U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x00140914U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} +#define ltc_pltcg_base_v() (0x00140000U) +#define ltc_pltcg_extent_v() (0x0017ffffU) +#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x001410c8U) +#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00141200U) +#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017ea00U) +#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00141104U) +#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U) +#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e8c8U) +#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) +#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x001410c8U) +#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e8ccU) +#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x1ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e8d0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x1ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU) +#define ltc_ltcs_ltss_cbc_base_r() (0x0017e8d4U) +#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) +#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define ltc_ltcs_ltss_cbc_param_r() (0x0017e8dcU) +#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(r) (((r) >> 28U) & 0xfU) +#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e91cU) +#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ + (((v)&0x1fU) << 16U) +#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017ea44U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ + (nvgpu_safe_add_u32(0x0017ea48U, nvgpu_safe_mult_u32((i), 4U))) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017ea58U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ + (U32(0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffffffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e924U) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U) +#define ltc_ltcs_ltss_g_elpg_r() (0x0017e828U) +#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_g_elpg_r() (0x00140828U) +#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_intr_r() (0x00140820U) +#define ltc_ltcs_ltss_intr_r() (0x0017e820U) +#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U) +#define ltc_ltc0_lts0_intr_r() (0x00141020U) +#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e910U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\ + (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\ + (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\ + (0x40000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e914U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\ + (((r) >> 16U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U) +#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x00140910U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x00140914U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h index 69f32dfb8..b4a81efb9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,236 +59,63 @@ #include #include -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_0_r(void) -{ - return 0x00000100U; -} -static inline u32 mc_intr_0_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_0_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_0_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_0_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_0_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_0_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_1_r(void) -{ - return 0x00000104U; -} -static inline u32 mc_intr_mask_0_r(void) -{ - return 0x00000640U; -} -static inline u32 mc_intr_mask_0_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_0_r(void) -{ - return 0x00000140U; -} -static inline u32 mc_intr_en_0_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_0_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_intr_mask_1_r(void) -{ - return 0x00000644U; -} -static inline u32 mc_intr_mask_1_pmu_s(void) -{ - return 1U; -} -static inline u32 mc_intr_mask_1_pmu_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 mc_intr_mask_1_pmu_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 mc_intr_mask_1_pmu_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 mc_intr_mask_1_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_1_r(void) -{ - return 0x00000144U; -} -static inline u32 mc_intr_en_1_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_1_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} +#define mc_boot_0_r() (0x00000000U) +#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU) +#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU) +#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU) +#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU) +#define mc_intr_0_r() (0x00000100U) +#define mc_intr_0_pfifo_pending_f() (0x100U) +#define mc_intr_0_pgraph_pending_f() (0x1000U) +#define mc_intr_0_pmu_pending_f() (0x1000000U) +#define mc_intr_0_ltc_pending_f() (0x2000000U) +#define mc_intr_0_priv_ring_pending_f() (0x40000000U) +#define mc_intr_0_pbus_pending_f() (0x10000000U) +#define mc_intr_1_r() (0x00000104U) +#define mc_intr_mask_0_r() (0x00000640U) +#define mc_intr_mask_0_pmu_enabled_f() (0x1000000U) +#define mc_intr_en_0_r() (0x00000140U) +#define mc_intr_en_0_inta_disabled_f() (0x0U) +#define mc_intr_en_0_inta_hardware_f() (0x1U) +#define mc_intr_mask_1_r() (0x00000644U) +#define mc_intr_mask_1_pmu_s() (1U) +#define mc_intr_mask_1_pmu_f(v) (((v)&0x1U) << 24U) +#define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U) +#define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U) +#define mc_intr_mask_1_pmu_enabled_f() (0x1000000U) +#define mc_intr_en_1_r() (0x00000144U) +#define mc_intr_en_1_inta_disabled_f() (0x0U) +#define mc_intr_en_1_inta_hardware_f() (0x1U) +#define mc_enable_r() (0x00000200U) +#define mc_enable_xbar_enabled_f() (0x4U) +#define mc_enable_l2_enabled_f() (0x8U) +#define mc_enable_pmedia_s() (1U) +#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) +#define mc_enable_pmedia_m() (U32(0x1U) << 4U) +#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) +#define mc_enable_priv_ring_enabled_f() (0x20U) +#define mc_enable_ce0_m() (U32(0x1U) << 6U) +#define mc_enable_pfifo_enabled_f() (0x100U) +#define mc_enable_pgraph_enabled_f() (0x1000U) +#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U) +#define mc_enable_pwr_disabled_v() (0x00000000U) +#define mc_enable_pwr_enabled_f() (0x2000U) +#define mc_enable_pfb_enabled_f() (0x100000U) +#define mc_enable_ce2_m() (U32(0x1U) << 21U) +#define mc_enable_ce2_enabled_f() (0x200000U) +#define mc_enable_blg_enabled_f() (0x8000000U) +#define mc_enable_perfmon_enabled_f() (0x10000000U) +#define mc_enable_hub_enabled_f() (0x20000000U) +#define mc_enable_pb_r() (0x00000204U) +#define mc_enable_pb_0_s() (1U) +#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) +#define mc_enable_pb_0_m() (U32(0x1U) << 0U) +#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) +#define mc_enable_pb_0_enabled_v() (0x00000001U) +#define mc_enable_pb_sel_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define mc_elpg_enable_r() (0x0000020cU) +#define mc_elpg_enable_xbar_enabled_f() (0x4U) +#define mc_elpg_enable_pfb_enabled_f() (0x100000U) +#define mc_elpg_enable_hub_enabled_f() (0x20000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h index 42affcc7d..25cdba7b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,520 +59,172 @@ #include #include -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_timeout_period_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method3_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_data0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000U; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} +#define pbdma_gp_entry1_r() (0x10000004U) +#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) +#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) +#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) +#define pbdma_gp_base_r(i)\ + (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base__size_1_v() (0x00000001U) +#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) +#define pbdma_gp_base_rsvd_s() (3U) +#define pbdma_gp_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) +#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) +#define pbdma_gp_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_get_r(i)\ + (nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_put_r(i)\ + (nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout_r(i)\ + (nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout__size_1_v() (0x00000001U) +#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U) +#define pbdma_timeout_period_max_f() (0xffffffffU) +#define pbdma_pb_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_r(i)\ + (nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_r(i)\ + (nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_r(i)\ + (nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_gp_fermi0_f() (0x0U) +#define pbdma_formats_pb_fermi1_f() (0x100U) +#define pbdma_formats_mp_fermi0_f() (0x0U) +#define pbdma_pb_header_r(i)\ + (nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_priv_user_f() (0x0U) +#define pbdma_pb_header_method_zero_f() (0x0U) +#define pbdma_pb_header_subchannel_zero_f() (0x0U) +#define pbdma_pb_header_level_main_f() (0x0U) +#define pbdma_pb_header_first_true_f() (0x400000U) +#define pbdma_pb_header_type_inc_f() (0x20000000U) +#define pbdma_pb_header_type_non_inc_f() (0x60000000U) +#define pbdma_hdr_shadow_r(i)\ + (nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_0_r(i)\ + (nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_1_r(i)\ + (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_r(i)\ + (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) +#define pbdma_subdevice_status_active_f() (0x10000000U) +#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) +#define pbdma_method0_r(i)\ + (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) +#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) +#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) +#define pbdma_method0_first_true_f() (0x400000U) +#define pbdma_method0_valid_true_f() (0x80000000U) +#define pbdma_method1_r(i)\ + (nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method2_r(i)\ + (nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method3_r(i)\ + (nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_data0_r(i)\ + (nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_r(i)\ + (nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_engine_sw_f() (0x1fU) +#define pbdma_acquire_r(i)\ + (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_retry_man_2_f() (0x2U) +#define pbdma_acquire_retry_exp_2_f() (0x100U) +#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) +#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) +#define pbdma_acquire_timeout_exp_max_f() (0x7800U) +#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) +#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) +#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) +#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) +#define pbdma_acquire_timeout_en_disable_f() (0x0U) +#define pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_channel_r(i)\ + (nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_r(i)\ + (nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_hw_valid_f() (0xfaceU) +#define pbdma_signature_sw_zero_f() (0x0U) +#define pbdma_userd_r(i)\ + (nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_target_vid_mem_f() (0x0U) +#define pbdma_userd_target_sys_mem_coh_f() (0x2U) +#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) +#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) +#define pbdma_userd_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) +#define pbdma_hce_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) +#define pbdma_intr_0_r(i)\ + (nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_intr_0_memreq_pending_f() (0x1U) +#define pbdma_intr_0_memack_timeout_pending_f() (0x2U) +#define pbdma_intr_0_memack_extra_pending_f() (0x4U) +#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U) +#define pbdma_intr_0_memdat_extra_pending_f() (0x10U) +#define pbdma_intr_0_memflush_pending_f() (0x20U) +#define pbdma_intr_0_memop_pending_f() (0x40U) +#define pbdma_intr_0_lbconnect_pending_f() (0x80U) +#define pbdma_intr_0_lbreq_pending_f() (0x100U) +#define pbdma_intr_0_lback_timeout_pending_f() (0x200U) +#define pbdma_intr_0_lback_extra_pending_f() (0x400U) +#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U) +#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U) +#define pbdma_intr_0_gpfifo_pending_f() (0x2000U) +#define pbdma_intr_0_gpptr_pending_f() (0x4000U) +#define pbdma_intr_0_gpentry_pending_f() (0x8000U) +#define pbdma_intr_0_gpcrc_pending_f() (0x10000U) +#define pbdma_intr_0_pbptr_pending_f() (0x20000U) +#define pbdma_intr_0_pbentry_pending_f() (0x40000U) +#define pbdma_intr_0_pbcrc_pending_f() (0x80000U) +#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U) +#define pbdma_intr_0_method_pending_f() (0x200000U) +#define pbdma_intr_0_methodcrc_pending_f() (0x400000U) +#define pbdma_intr_0_device_pending_f() (0x800000U) +#define pbdma_intr_0_semaphore_pending_f() (0x2000000U) +#define pbdma_intr_0_acquire_pending_f() (0x4000000U) +#define pbdma_intr_0_pri_pending_f() (0x8000000U) +#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U) +#define pbdma_intr_0_pbseg_pending_f() (0x40000000U) +#define pbdma_intr_0_signature_pending_f() (0x80000000U) +#define pbdma_intr_1_r(i)\ + (nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_r(i)\ + (nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U) +#define pbdma_intr_en_1_r(i)\ + (nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_r(i)\ + (nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_lbreq_enabled_f() (0x100U) +#define pbdma_intr_stall_1_r(i)\ + (nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U) +#define pbdma_udma_nop_r() (0x00000008U) +#define pbdma_syncpointa_r(i)\ + (nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU) +#define pbdma_syncpointb_r(i)\ + (nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_syncpointb_op_v(r) (((r) >> 0U) & 0x3U) +#define pbdma_syncpointb_op_wait_v() (0x00000000U) +#define pbdma_syncpointb_wait_switch_v(r) (((r) >> 4U) & 0x1U) +#define pbdma_syncpointb_wait_switch_en_v() (0x00000001U) +#define pbdma_syncpointb_syncpt_index_v(r) (((r) >> 8U) & 0xffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h index 6c7ee62b1..e8f8ec2ce 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,156 +59,42 @@ #include #include -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} +#define perf_pmasys_control_r() (0x001b4000U) +#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) +#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) +#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) +#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) +#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) +#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) +#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_mem_block_r() (0x001b4070U) +#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) +#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) +#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) +#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) +#define perf_pmasys_mem_block_target_lfb_f() (0x0U) +#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U) +#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) +#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) +#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) +#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) +#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) +#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) +#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) +#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) +#define perf_pmasys_mem_block_valid_false_f() (0x0U) +#define perf_pmasys_outbase_r() (0x001b4074U) +#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_outbaseupper_r() (0x001b4078U) +#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) +#define perf_pmasys_outsize_r() (0x001b407cU) +#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_mem_bytes_r() (0x001b4084U) +#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_mem_bump_r() (0x001b4088U) +#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_enginestatus_r() (0x001b40a4U) +#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) +#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) +#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h index 87b332e08..48c61cb30 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pram_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pram_data032_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U)); -} +#define pram_data032_r(i)\ + (nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h index 475d69856..47035b82e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,104 +59,31 @@ #include #include -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} +#define pri_ringmaster_command_r() (0x0012004cU) +#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U) +#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU) +#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U) +#define pri_ringmaster_command_cmd_start_ring_f() (0x1U) +#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U) +#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U) +#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U) +#define pri_ringmaster_command_data_r() (0x00120048U) +#define pri_ringmaster_start_results_r() (0x00120050U) +#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U) +#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U) +#define pri_ringmaster_intr_status0_r() (0x00120058U) +#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\ + (((r) >> 0U) & 0x1U) +#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U) +#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U) +#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\ + (((r) >> 8U) & 0x1U) +#define pri_ringmaster_intr_status1_r() (0x0012005cU) +#define pri_ringmaster_global_ctl_r() (0x00120060U) +#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U) +#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U) +#define pri_ringmaster_enum_fbp_r() (0x00120074U) +#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_gpc_r() (0x00120078U) +#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h index 0f89ed877..45eda2318 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,24 +59,10 @@ #include #include -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} +#define pri_ringstation_gpc_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U) +#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) +#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) +#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h index f393aeb7c..071e8565b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,36 +59,14 @@ #include #include -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} +#define pri_ringstation_sys_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_sys_decode_config_r() (0x00122204U) +#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U) +#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\ + (0x1U) +#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U) +#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) +#define pri_ringstation_sys_priv_error_info_r() (0x00122128U) +#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h index 5bb0c01ea..00313274b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_proj_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,112 +59,31 @@ #include #include -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00001000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} +#define proj_gpc_base_v() (0x00500000U) +#define proj_gpc_shared_base_v() (0x00418000U) +#define proj_gpc_stride_v() (0x00008000U) +#define proj_gpc_priv_stride_v() (0x00000800U) +#define proj_ltc_stride_v() (0x00002000U) +#define proj_lts_stride_v() (0x00000400U) +#define proj_fbpa_stride_v() (0x00001000U) +#define proj_ppc_in_gpc_base_v() (0x00003000U) +#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U) +#define proj_ppc_in_gpc_stride_v() (0x00000200U) +#define proj_rop_base_v() (0x00410000U) +#define proj_rop_shared_base_v() (0x00408800U) +#define proj_rop_stride_v() (0x00000400U) +#define proj_tpc_in_gpc_base_v() (0x00004000U) +#define proj_tpc_in_gpc_stride_v() (0x00000800U) +#define proj_tpc_in_gpc_shared_base_v() (0x00001800U) +#define proj_host_num_engines_v() (0x00000002U) +#define proj_host_num_pbdma_v() (0x00000001U) +#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000001U) +#define proj_scal_litter_num_fbps_v() (0x00000001U) +#define proj_scal_litter_num_fbpas_v() (0x00000001U) +#define proj_scal_litter_num_gpcs_v() (0x00000001U) +#define proj_scal_litter_num_pes_per_gpc_v() (0x00000001U) +#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000001U) +#define proj_scal_litter_num_zcull_banks_v() (0x00000004U) +#define proj_scal_max_gpcs_v() (0x00000020U) +#define proj_scal_max_tpc_per_gpc_v() (0x00000008U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h index f14e916be..2bc6f5636 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,792 +59,223 @@ #include #include -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a600U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} +#define pwr_falcon_irqsset_r() (0x0010a000U) +#define pwr_falcon_irqsset_swgen0_set_f() (0x40U) +#define pwr_falcon_irqsclr_r() (0x0010a004U) +#define pwr_falcon_irqstat_r() (0x0010a008U) +#define pwr_falcon_irqstat_halt_true_f() (0x10U) +#define pwr_falcon_irqstat_exterr_true_f() (0x20U) +#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) +#define pwr_falcon_irqmode_r() (0x0010a00cU) +#define pwr_falcon_irqmset_r() (0x0010a010U) +#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_r() (0x0010a014U) +#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmask_r() (0x0010a018U) +#define pwr_falcon_irqdest_r() (0x0010a01cU) +#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pwr_falcon_curctx_r() (0x0010a050U) +#define pwr_falcon_nxtctx_r() (0x0010a054U) +#define pwr_falcon_mailbox0_r() (0x0010a040U) +#define pwr_falcon_mailbox1_r() (0x0010a044U) +#define pwr_falcon_itfen_r() (0x0010a048U) +#define pwr_falcon_itfen_ctxen_enable_f() (0x1U) +#define pwr_falcon_idlestate_r() (0x0010a04cU) +#define pwr_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pwr_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pwr_falcon_os_r() (0x0010a080U) +#define pwr_falcon_engctl_r() (0x0010a0a4U) +#define pwr_falcon_cpuctl_r() (0x0010a100U) +#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pwr_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_bootvec_r() (0x0010a104U) +#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_falcon_dmactl_r() (0x0010a10cU) +#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pwr_falcon_hwcfg_r() (0x0010a108U) +#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pwr_falcon_dmatrfbase_r() (0x0010a110U) +#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) +#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) +#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) +#define pwr_falcon_exterraddr_r() (0x0010a168U) +#define pwr_falcon_exterrstat_r() (0x0010a16cU) +#define pwr_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pwr_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) +#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) +#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) +#define pwr_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_new_instblk_r() (0x0010a480U) +#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define pwr_pmu_new_instblk_target_fb_f() (0x0U) +#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) +#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) +#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) +#define pwr_pmu_mutex_id_r() (0x0010a488U) +#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) +#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) +#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) +#define pwr_pmu_mutex_r(i)\ + (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mutex__size_1_v() (0x00000010U) +#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) +#define pwr_pmu_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_head__size_1_v() (0x00000004U) +#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) +#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_head_r() (0x0010a4c8U) +#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) +#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_idle_mask_r(i)\ + (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U) +#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) +#define pwr_pmu_idle_count_r(i)\ + (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) +#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_idle_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) +#define pwr_pmu_idle_ctrl_value_busy_f() (0x2U) +#define pwr_pmu_idle_ctrl_value_always_f() (0x3U) +#define pwr_pmu_idle_ctrl_filter_m() (U32(0x1U) << 2U) +#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) +#define pwr_pmu_idle_threshold_r(i)\ + (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_intr_r() (0x0010a9e8U) +#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) +#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) +#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) +#define pwr_pmu_idle_mask_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_mask_1_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_ctrl_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_debug_r(i)\ + (nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_debug__size_1_v() (0x00000004U) +#define pwr_pmu_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mailbox__size_1_v() (0x0000000cU) +#define pwr_pmu_bar0_addr_r() (0x0010a7a0U) +#define pwr_pmu_bar0_data_r() (0x0010a7a4U) +#define pwr_pmu_bar0_ctl_r() (0x0010a7acU) +#define pwr_pmu_bar0_timeout_r() (0x0010a7a8U) +#define pwr_pmu_bar0_fecs_error_r() (0x0010a988U) +#define pwr_pmu_bar0_error_status_r() (0x0010a7b0U) +#define pwr_pmu_bar0_error_status_timeout_host_m() (U32(0x1U) << 0U) +#define pwr_pmu_bar0_error_status_timeout_fecs_m() (U32(0x1U) << 1U) +#define pwr_pmu_bar0_error_status_cmd_hwerr_m() (U32(0x1U) << 2U) +#define pwr_pmu_bar0_error_status_err_cmd_m() (U32(0x1U) << 3U) +#define pwr_pmu_bar0_error_status_hosterr_m() (U32(0x1U) << 30U) +#define pwr_pmu_bar0_error_status_fecserr_m() (U32(0x1U) << 31U) +#define pwr_pmu_pg_idlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_ppuidlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_idle_cnt_r(i)\ + (nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_intren_r(i)\ + (nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x0010a600U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_target_local_fb_f() (0x0U) +#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pwr_fbif_transcfg_mem_type_s() (1U) +#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pwr_fbif_transcfg_mem_type_physical_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h index 27b264673..dcf0e2fc2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,396 +59,102 @@ #include #include -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41U; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_fc_pb_timeslice_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_v(u32 r) -{ - return (r >> 14U) & 0xfU; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_v(u32 r) -{ - return (r >> 18U) & 0xffU; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} +#define ram_in_ramfc_s() (4096U) +#define ram_in_ramfc_w() (0U) +#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_page_dir_base_target_w() (128U) +#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) +#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) +#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) +#define ram_in_page_dir_base_vol_w() (128U) +#define ram_in_page_dir_base_vol_true_f() (0x4U) +#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_page_dir_base_lo_w() (128U) +#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_page_dir_base_hi_w() (129U) +#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_adr_limit_lo_w() (130U) +#define ram_in_adr_limit_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_adr_limit_hi_w() (131U) +#define ram_in_engine_cs_w() (132U) +#define ram_in_engine_cs_wfi_v() (0x00000000U) +#define ram_in_engine_cs_wfi_f() (0x0U) +#define ram_in_engine_cs_fg_v() (0x00000001U) +#define ram_in_engine_cs_fg_f() (0x8U) +#define ram_in_gr_cs_w() (132U) +#define ram_in_gr_cs_wfi_f() (0x0U) +#define ram_in_gr_wfi_target_w() (132U) +#define ram_in_gr_wfi_mode_w() (132U) +#define ram_in_gr_wfi_mode_physical_v() (0x00000000U) +#define ram_in_gr_wfi_mode_physical_f() (0x0U) +#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) +#define ram_in_gr_wfi_mode_virtual_f() (0x4U) +#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_gr_wfi_ptr_lo_w() (132U) +#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_gr_wfi_ptr_hi_w() (133U) +#define ram_in_base_shift_v() (0x0000000cU) +#define ram_in_alloc_size_v() (0x00001000U) +#define ram_fc_size_val_v() (0x00000200U) +#define ram_fc_gp_put_w() (0U) +#define ram_fc_userd_w() (2U) +#define ram_fc_userd_hi_w() (3U) +#define ram_fc_signature_w() (4U) +#define ram_fc_gp_get_w() (5U) +#define ram_fc_pb_get_w() (6U) +#define ram_fc_pb_get_hi_w() (7U) +#define ram_fc_pb_top_level_get_w() (8U) +#define ram_fc_pb_top_level_get_hi_w() (9U) +#define ram_fc_acquire_w() (12U) +#define ram_fc_semaphorea_w() (14U) +#define ram_fc_semaphoreb_w() (15U) +#define ram_fc_semaphorec_w() (16U) +#define ram_fc_semaphored_w() (17U) +#define ram_fc_gp_base_w() (18U) +#define ram_fc_gp_base_hi_w() (19U) +#define ram_fc_gp_fetch_w() (20U) +#define ram_fc_pb_fetch_w() (21U) +#define ram_fc_pb_fetch_hi_w() (22U) +#define ram_fc_pb_put_w() (23U) +#define ram_fc_pb_put_hi_w() (24U) +#define ram_fc_pb_header_w() (33U) +#define ram_fc_pb_count_w() (34U) +#define ram_fc_subdevice_w() (37U) +#define ram_fc_formats_w() (39U) +#define ram_fc_syncpointa_w() (41U) +#define ram_fc_syncpointb_w() (42U) +#define ram_fc_target_w() (43U) +#define ram_fc_hce_ctrl_w() (57U) +#define ram_fc_chid_w() (58U) +#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) +#define ram_fc_chid_id_w() (0U) +#define ram_fc_runlist_timeslice_w() (62U) +#define ram_fc_pb_timeslice_w() (63U) +#define ram_userd_base_shift_v() (0x00000009U) +#define ram_userd_chan_size_v() (0x00000200U) +#define ram_userd_put_w() (16U) +#define ram_userd_get_w() (17U) +#define ram_userd_ref_w() (18U) +#define ram_userd_put_hi_w() (19U) +#define ram_userd_ref_threshold_w() (20U) +#define ram_userd_top_level_get_w() (22U) +#define ram_userd_top_level_get_hi_w() (23U) +#define ram_userd_get_hi_w() (24U) +#define ram_userd_gp_get_w() (34U) +#define ram_userd_gp_put_w() (35U) +#define ram_userd_gp_top_level_get_w() (22U) +#define ram_userd_gp_top_level_get_hi_w() (23U) +#define ram_rl_entry_size_v() (0x00000008U) +#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) +#define ram_rl_entry_type_chid_f() (0x0U) +#define ram_rl_entry_type_tsg_f() (0x2000U) +#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) +#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) +#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) +#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) +#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) +#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) +#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h index 7f691921e..77ca78275 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,312 +59,85 @@ #include #include -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_0_priority_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_priority_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_priority_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return U32(0x3U) << 4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return U32(0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return U32(0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return U32(0xfU) << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return U32(0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return U32(0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return U32(0x3fU) << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} +#define therm_use_a_r() (0x00020798U) +#define therm_use_a_ext_therm_0_enable_f() (0x1U) +#define therm_use_a_ext_therm_1_enable_f() (0x2U) +#define therm_use_a_ext_therm_2_enable_f() (0x4U) +#define therm_evt_ext_therm_0_r() (0x00020700U) +#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 8U) +#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U) +#define therm_evt_ext_therm_0_priority_f(v) (((v)&0x1fU) << 24U) +#define therm_evt_ext_therm_1_r() (0x00020704U) +#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 8U) +#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U) +#define therm_evt_ext_therm_1_priority_f(v) (((v)&0x1fU) << 24U) +#define therm_evt_ext_therm_2_r() (0x00020708U) +#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 8U) +#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U) +#define therm_evt_ext_therm_2_priority_f(v) (((v)&0x1fU) << 24U) +#define therm_weight_1_r() (0x00020024U) +#define therm_config1_r() (0x00020050U) +#define therm_config2_r() (0x00020130U) +#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) +#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) +#define therm_gate_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) +#define therm_gate_ctrl_eng_clk_run_f() (0x0U) +#define therm_gate_ctrl_eng_clk_auto_f() (0x1U) +#define therm_gate_ctrl_eng_clk_stop_f() (0x2U) +#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) +#define therm_gate_ctrl_blk_clk_run_f() (0x0U) +#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) +#define therm_gate_ctrl_eng_pwr_m() (U32(0x3U) << 4U) +#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U) +#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U) +#define therm_gate_ctrl_eng_pwr_off_f() (0x20U) +#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) +#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) +#define therm_fecs_idle_filter_r() (0x00020288U) +#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_hubmmu_idle_filter_r() (0x0002028cU) +#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_clk_slowdown_r(i)\ + (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) +#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) +#define therm_grad_stepping_table_r(i)\ + (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) +#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) +#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) +#define therm_grad_stepping0_r() (0x000202c0U) +#define therm_grad_stepping0_feature_s() (1U) +#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) +#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) +#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) +#define therm_grad_stepping0_feature_enable_f() (0x1U) +#define therm_grad_stepping1_r() (0x000202c4U) +#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) +#define therm_clk_timing_r(i)\ + (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h index d2ddbfeac..32a9400ac 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,72 +59,21 @@ #include #include -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} +#define timer_pri_timeout_r() (0x00009080U) +#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) +#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) +#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) +#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) +#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) +#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) +#define timer_pri_timeout_en_en_disabled_f() (0x0U) +#define timer_pri_timeout_save_0_r() (0x00009084U) +#define timer_pri_timeout_save_0_fecs_tgt_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_save_0_addr_v(r) (((r) >> 2U) & 0x3fffffU) +#define timer_pri_timeout_save_0_write_v(r) (((r) >> 1U) & 0x1U) +#define timer_pri_timeout_save_1_r() (0x00009088U) +#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU) +#define timer_time_0_r() (0x00009400U) +#define timer_time_1_r() (0x00009410U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h index ab0387ffb..c9a646700 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_top_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,160 +59,44 @@ #include #include -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_chain_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy0_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_type_enum_copy0_f(void) -{ - return 0x4U; -} -static inline u32 top_device_info_type_enum_copy1_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_type_enum_copy1_f(void) -{ - return 0x8U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_fs_status_fbp_r(void) -{ - return 0x00022548U; -} -static inline u32 top_fs_status_fbp_cluster_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 top_fs_status_fbp_cluster_enable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_fs_status_fbp_cluster_enable_f(void) -{ - return 0x0U; -} -static inline u32 top_fs_status_fbp_cluster_disable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_fs_status_fbp_cluster_disable_f(void) -{ - return 0x1U; -} +#define top_num_gpcs_r() (0x00022430U) +#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_tpc_per_gpc_r() (0x00022434U) +#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbps_r() (0x00022438U) +#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_device_info_r(i)\ + (nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U))) +#define top_device_info__size_1_v() (0x00000040U) +#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U) +#define top_device_info_chain_enable_v() (0x00000001U) +#define top_device_info_chain_disable_v() (0x00000000U) +#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU) +#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU) +#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU) +#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU) +#define top_device_info_type_enum_graphics_v() (0x00000000U) +#define top_device_info_type_enum_graphics_f() (0x0U) +#define top_device_info_type_enum_copy0_v() (0x00000001U) +#define top_device_info_type_enum_copy0_f() (0x4U) +#define top_device_info_type_enum_copy1_v() (0x00000002U) +#define top_device_info_type_enum_copy1_f() (0x8U) +#define top_device_info_type_enum_copy2_v() (0x00000003U) +#define top_device_info_type_enum_copy2_f() (0xcU) +#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U) +#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U) +#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U) +#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) +#define top_device_info_entry_not_valid_v() (0x00000000U) +#define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_engine_type_v() (0x00000003U) +#define top_device_info_entry_data_v() (0x00000001U) +#define top_fs_status_fbp_r() (0x00022548U) +#define top_fs_status_fbp_cluster_v(r) (((r) >> 0U) & 0xffffU) +#define top_fs_status_fbp_cluster_enable_v() (0x00000000U) +#define top_fs_status_fbp_cluster_enable_f() (0x0U) +#define top_fs_status_fbp_cluster_disable_v() (0x00000001U) +#define top_fs_status_fbp_cluster_disable_f() (0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h index a6dd30add..08f5f3df0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,260 +59,71 @@ #include #include -static inline u32 trim_sys_gpcpll_cfg_r(void) -{ - return 0x00137000U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) -{ - return 0x10U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) -{ - return 0x20000U; -} -static inline u32 trim_sys_gpcpll_coeff_r(void) -{ - return 0x00137004U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 trim_sys_sel_vco_r(void) -{ - return 0x00137100U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpc2clk_out_r(void) -{ - return 0x00137250U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) -{ - return 0x3cU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) -{ - return U32(0x3fU) << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 trim_sys_gpcpll_cfg2_r(void) -{ - return 0x0013700cU; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) -{ - return U32(0xffU) << 24U; -} -static inline u32 trim_sys_gpcpll_cfg3_r(void) -{ - return 0x00137018U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) -{ - return 0x0013701cU; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) -{ - return 0x400000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) -{ - return 0x001328a0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} +#define trim_sys_gpcpll_cfg_r() (0x00137000U) +#define trim_sys_gpcpll_cfg_enable_m() (U32(0x1U) << 0U) +#define trim_sys_gpcpll_cfg_enable_v(r) (((r) >> 0U) & 0x1U) +#define trim_sys_gpcpll_cfg_enable_no_f() (0x0U) +#define trim_sys_gpcpll_cfg_enable_yes_f() (0x1U) +#define trim_sys_gpcpll_cfg_iddq_m() (U32(0x1U) << 1U) +#define trim_sys_gpcpll_cfg_iddq_v(r) (((r) >> 1U) & 0x1U) +#define trim_sys_gpcpll_cfg_iddq_power_on_v() (0x00000000U) +#define trim_sys_gpcpll_cfg_enb_lckdet_m() (U32(0x1U) << 4U) +#define trim_sys_gpcpll_cfg_enb_lckdet_power_on_f() (0x0U) +#define trim_sys_gpcpll_cfg_enb_lckdet_power_off_f() (0x10U) +#define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U) +#define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U) +#define trim_sys_gpcpll_coeff_r() (0x00137004U) +#define trim_sys_gpcpll_coeff_mdiv_f(v) (((v)&0xffU) << 0U) +#define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U) +#define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU) +#define trim_sys_gpcpll_coeff_ndiv_f(v) (((v)&0xffU) << 8U) +#define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U) +#define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU) +#define trim_sys_gpcpll_coeff_pldiv_f(v) (((v)&0x3fU) << 16U) +#define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U) +#define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU) +#define trim_sys_sel_vco_r() (0x00137100U) +#define trim_sys_sel_vco_gpc2clk_out_m() (U32(0x1U) << 0U) +#define trim_sys_sel_vco_gpc2clk_out_init_v() (0x00000000U) +#define trim_sys_sel_vco_gpc2clk_out_init_f() (0x0U) +#define trim_sys_sel_vco_gpc2clk_out_bypass_f() (0x0U) +#define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U) +#define trim_sys_gpc2clk_out_r() (0x00137250U) +#define trim_sys_gpc2clk_out_bypdiv_s() (6U) +#define trim_sys_gpc2clk_out_bypdiv_f(v) (((v)&0x3fU) << 0U) +#define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U) +#define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU) +#define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU) +#define trim_sys_gpc2clk_out_vcodiv_s() (6U) +#define trim_sys_gpc2clk_out_vcodiv_f(v) (((v)&0x3fU) << 8U) +#define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U) +#define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU) +#define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U) +#define trim_sys_gpc2clk_out_sdiv14_m() (U32(0x1U) << 31U) +#define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\ + (nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U))) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v) (((v)&0x3fffU) << 0U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U) +#define trim_gpc_clk_cntr_ncgpcclk_cnt_r(i)\ + (nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U))) +#define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU) +#define trim_sys_gpcpll_cfg2_r() (0x0013700cU) +#define trim_sys_gpcpll_cfg2_pll_stepa_f(v) (((v)&0xffU) << 24U) +#define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U) +#define trim_sys_gpcpll_cfg3_r() (0x00137018U) +#define trim_sys_gpcpll_cfg3_pll_stepb_f(v) (((v)&0xffU) << 16U) +#define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U) +#define trim_sys_gpcpll_ndiv_slowdown_r() (0x0013701cU) +#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m() (U32(0x1U) << 22U) +#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f() (0x400000U) +#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f() (0x0U) +#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m() (U32(0x1U) << 31U) +#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f() (0x80000000U) +#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f() (0x0U) +#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r() (0x001328a0U) +#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(r)\ + (((r) >> 24U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h index 99ea4d8fa..fbb11f63d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,184 +59,49 @@ #include #include -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} +#define bus_bar0_window_r() (0x00001700U) +#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) +#define bus_bar0_window_target_vid_mem_f() (0x0U) +#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) +#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) +#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) +#define bus_bar1_block_r() (0x00001704U) +#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar1_block_target_vid_mem_f() (0x0U) +#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar1_block_mode_virtual_f() (0x80000000U) +#define bus_bar2_block_r() (0x00001714U) +#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar2_block_target_vid_mem_f() (0x0U) +#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar2_block_mode_virtual_f() (0x80000000U) +#define bus_bar1_block_ptr_shift_v() (0x0000000cU) +#define bus_bar2_block_ptr_shift_v() (0x0000000cU) +#define bus_bind_status_r() (0x00001710U) +#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U) +#define bus_bind_status_bar1_pending_empty_f() (0x0U) +#define bus_bind_status_bar1_pending_busy_f() (0x1U) +#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define bus_bind_status_bar1_outstanding_false_f() (0x0U) +#define bus_bind_status_bar1_outstanding_true_f() (0x2U) +#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U) +#define bus_bind_status_bar2_pending_empty_v() (0x00000000U) +#define bus_bind_status_bar2_pending_empty_f() (0x0U) +#define bus_bind_status_bar2_pending_busy_v() (0x00000001U) +#define bus_bind_status_bar2_pending_busy_f() (0x4U) +#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U) +#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U) +#define bus_bind_status_bar2_outstanding_false_f() (0x0U) +#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U) +#define bus_bind_status_bar2_outstanding_true_f() (0x8U) +#define bus_intr_0_r() (0x00001100U) +#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U) +#define bus_intr_en_0_r() (0x00001140U) +#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h index d95cc9b14..be019758f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,148 +59,42 @@ #include #include -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_in_use_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 ccsr_channel_status_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acquire_v(void) -{ - return 0x00000003U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_v(void) -{ - return 0x00000005U; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void) -{ - return 0x00000006U; -} -static inline u32 ccsr_channel_status_on_eng_v(void) -{ - return 0x00000007U; -} -static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void) -{ - return 0x00000008U; -} -static inline u32 ccsr_channel_status_on_eng_pending_v(void) -{ - return 0x00000009U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ccsr_channel_busy_true_v(void) -{ - return 0x00000001U; -} +#define ccsr_channel_inst_r(i)\ + (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel_inst__size_1_v() (0x00000200U) +#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define ccsr_channel_inst_target_vid_mem_f() (0x0U) +#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) +#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) +#define ccsr_channel_inst_bind_false_f() (0x0U) +#define ccsr_channel_inst_bind_true_f() (0x80000000U) +#define ccsr_channel_r(i)\ + (nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel__size_1_v() (0x00000200U) +#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) +#define ccsr_channel_enable_in_use_v() (0x00000001U) +#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) +#define ccsr_channel_enable_set_true_f() (0x400U) +#define ccsr_channel_enable_clr_true_f() (0x800U) +#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) +#define ccsr_channel_status_idle_v() (0x00000000U) +#define ccsr_channel_status_pending_v() (0x00000001U) +#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U) +#define ccsr_channel_status_pending_acquire_v() (0x00000003U) +#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U) +#define ccsr_channel_status_on_pbdma_v() (0x00000005U) +#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U) +#define ccsr_channel_status_on_eng_v() (0x00000007U) +#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U) +#define ccsr_channel_status_on_eng_pending_v() (0x00000009U) +#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU) +#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU) +#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU) +#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU) +#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU) +#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) +#define ccsr_channel_next_true_v() (0x00000001U) +#define ccsr_channel_force_ctx_reload_true_f() (0x100U) +#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U) +#define ccsr_channel_busy_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h index 7d3bc3c9e..8df165dea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,11 @@ #include #include -static inline u32 ce2_intr_status_r(void) -{ - return 0x00106908U; -} -static inline u32 ce2_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce2_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce2_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} +#define ce2_intr_status_r() (0x00106908U) +#define ce2_intr_status_blockpipe_pending_f() (0x1U) +#define ce2_intr_status_blockpipe_reset_f() (0x1U) +#define ce2_intr_status_nonblockpipe_pending_f() (0x2U) +#define ce2_intr_status_nonblockpipe_reset_f() (0x2U) +#define ce2_intr_status_launcherr_pending_f() (0x4U) +#define ce2_intr_status_launcherr_reset_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h index 769ae064b..09a94fb7b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,424 +59,136 @@ #include #include -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_gpccs_header_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void) -{ - return 0x400U; -} -static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_pc_sampling_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 ctxsw_prog_main_image_pm_pc_sampling_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000acU; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeefU; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return U32(0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000aU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000bU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000dU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000U; -} -static inline u32 ctxsw_prog_main_image_preemption_options_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void) -{ - return 0x1U; -} +#define ctxsw_prog_fecs_header_v() (0x00000100U) +#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) +#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) +#define ctxsw_prog_main_image_ctl_o() (0x0000000cU) +#define ctxsw_prog_main_image_ctl_cde_enabled_f() (0x400U) +#define ctxsw_prog_main_image_ctl_cde_disabled_f() (0x0U) +#define ctxsw_prog_main_image_patch_count_o() (0x00000010U) +#define ctxsw_prog_main_image_context_id_o() (0x000000f0U) +#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U) +#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U) +#define ctxsw_prog_main_image_zcull_o() (0x0000001cU) +#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U) +#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U) +#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U) +#define ctxsw_prog_main_image_pm_o() (0x00000028U) +#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U) +#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U) +#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) +#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) +#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_pc_sampling_f(v) (((v)&0x1U) << 6U) +#define ctxsw_prog_main_image_pm_pc_sampling_m() (U32(0x1U) << 6U) +#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) +#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) +#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) +#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) +#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) +#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) +#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) +#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) +#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U) +#define ctxsw_prog_local_magic_value_o() (0x000000fcU) +#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU) +#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU) +#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU) +#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U) +#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\ + (0x00000000U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\ + (0x00000002U) +#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ + (((r) >> 0U) & 0x3U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U) +#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U) +#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U) +#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU) +#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U) +#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\ + (((v)&0xffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\ + (U32(0xfffffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m()\ + (U32(0x3U) << 28U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()\ + (0x0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f()\ + (0x20000000U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f()\ + (0x30000000U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U) +#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U) +#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U) +#define ctxsw_prog_record_timestamp_magic_value_lo_v_value_v() (0x00000000U) +#define ctxsw_prog_record_timestamp_magic_value_hi_o() (0x00000004U) +#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v() (0x600dbeefU) +#define ctxsw_prog_record_timestamp_context_id_o() (0x00000008U) +#define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU) +#define ctxsw_prog_record_timestamp_new_context_id_o() (0x00000010U) +#define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U) +#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U) +#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\ + (((r) >> 0U) & 0xffffffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\ + (0x00000001U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f()\ + (0x1000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v() (0x00000002U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f() (0x2000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v()\ + (0x0000000aU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f() (0xa000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v()\ + (0x0000000bU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f()\ + (0xb000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v()\ + (0x0000000cU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f()\ + (0xc000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v()\ + (0x0000000dU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f()\ + (0xd000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v() (0x00000003U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f() (0x3000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v()\ + (0x00000004U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f()\ + (0x4000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v()\ + (0x00000005U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f()\ + (0x5000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\ + (0x000000ffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\ + (0xff000000U) +#define ctxsw_prog_main_image_preemption_options_o() (0x00000060U) +#define ctxsw_prog_main_image_preemption_options_control_f(v) (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_preemption_options_control_cta_enabled_f() (0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h index d920274b4..6e7abfecb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,556 +59,147 @@ #include #include -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg1_r(void) -{ - return 0x0000012cU; -} -static inline u32 falcon_falcon_hwcfg1_imem_ports_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 falcon_falcon_hwcfg1_dmem_ports_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} +#define falcon_falcon_irqsset_r() (0x00000000U) +#define falcon_falcon_irqsset_swgen0_set_f() (0x40U) +#define falcon_falcon_irqsclr_r() (0x00000004U) +#define falcon_falcon_irqstat_r() (0x00000008U) +#define falcon_falcon_irqstat_halt_true_f() (0x10U) +#define falcon_falcon_irqstat_exterr_true_f() (0x20U) +#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) +#define falcon_falcon_irqmode_r() (0x0000000cU) +#define falcon_falcon_irqmset_r() (0x00000010U) +#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_r() (0x00000014U) +#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqmask_r() (0x00000018U) +#define falcon_falcon_irqdest_r() (0x0000001cU) +#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define falcon_falcon_curctx_r() (0x00000050U) +#define falcon_falcon_nxtctx_r() (0x00000054U) +#define falcon_falcon_mailbox0_r() (0x00000040U) +#define falcon_falcon_mailbox1_r() (0x00000044U) +#define falcon_falcon_itfen_r() (0x00000048U) +#define falcon_falcon_itfen_ctxen_enable_f() (0x1U) +#define falcon_falcon_idlestate_r() (0x0000004cU) +#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define falcon_falcon_os_r() (0x00000080U) +#define falcon_falcon_engctl_r() (0x000000a4U) +#define falcon_falcon_cpuctl_r() (0x00000100U) +#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define falcon_falcon_cpuctl_alias_r() (0x00000130U) +#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) +#define falcon_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_sctl_r() (0x00000240U) +#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define falcon_falcon_bootvec_r() (0x00000104U) +#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define falcon_falcon_dmactl_r() (0x0000010cU) +#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_hwcfg_r() (0x00000108U) +#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define falcon_falcon_hwcfg1_r() (0x0000012cU) +#define falcon_falcon_hwcfg1_imem_ports_v(r) (((r) >> 8U) & 0xfU) +#define falcon_falcon_hwcfg1_dmem_ports_v(r) (((r) >> 12U) & 0xfU) +#define falcon_falcon_dmatrfbase_r() (0x00000110U) +#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) +#define falcon_falcon_dmatrfcmd_r() (0x00000118U) +#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) +#define falcon_falcon_imctl_debug_r() (0x0000015cU) +#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) +#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) +#define falcon_falcon_imstat_r() (0x00000144U) +#define falcon_falcon_traceidx_r() (0x00000148U) +#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) +#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) +#define falcon_falcon_tracepc_r() (0x0000014cU) +#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) +#define falcon_falcon_exterraddr_r() (0x0010a168U) +#define falcon_falcon_exterrstat_r() (0x0010a16cU) +#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) +#define falcon_falcon_icd_cmd_r() (0x00000200U) +#define falcon_falcon_icd_cmd_opc_s() (4U) +#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define falcon_falcon_icd_rdata_r() (0x0000020cU) +#define falcon_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define falcon_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_debug1_r() (0x00000090U) +#define falcon_falcon_debug1_ctxsw_mode_s() (1U) +#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define falcon_falcon_debuginfo_r() (0x00000094U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h index 51f41fd88..7cdea89cb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,284 +59,74 @@ #include #include -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_true_f(void) -{ - return 0x1000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_index_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_vpr_info_index_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_wpr_info_r(void) -{ - return 0x00100cd4U; -} -static inline u32 fb_mmu_wpr_info_index_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_mmu_wpr_info_index_allow_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_wpr_info_index_allow_write_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void) -{ - return 0x00000004U; -} -static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void) -{ - return 0x00000005U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} +#define fb_fbhub_num_active_ltcs_r() (0x00100800U) +#define fb_mmu_ctrl_r() (0x00100c80U) +#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) +#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) +#define fb_mmu_ctrl_use_pdb_big_page_size_v(r) (((r) >> 11U) & 0x1U) +#define fb_mmu_ctrl_use_pdb_big_page_size_true_f() (0x800U) +#define fb_mmu_ctrl_use_pdb_big_page_size_false_f() (0x0U) +#define fb_mmu_ctrl_use_full_comp_tag_line_v(r) (((r) >> 12U) & 0x1U) +#define fb_mmu_ctrl_use_full_comp_tag_line_true_f() (0x1000U) +#define fb_priv_mmu_phy_secure_r() (0x00100ce4U) +#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) +#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) +#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_invalidate_r() (0x00100cbcU) +#define fb_mmu_invalidate_all_va_true_f() (0x1U) +#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) +#define fb_mmu_invalidate_trigger_s() (1U) +#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) +#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) +#define fb_mmu_debug_wr_r() (0x00100cc8U) +#define fb_mmu_debug_wr_aperture_s() (2U) +#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_wr_vol_false_f() (0x0U) +#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) +#define fb_mmu_debug_wr_vol_true_f() (0x4U) +#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_rd_r() (0x00100cccU) +#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_rd_vol_false_f() (0x0U) +#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_ctrl_r() (0x00100cc4U) +#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_enabled_f() (0x10000U) +#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U) +#define fb_mmu_vpr_info_r() (0x00100cd0U) +#define fb_mmu_vpr_info_index_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_vpr_info_index_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_vpr_info_index_addr_lo_v() (0x00000000U) +#define fb_mmu_vpr_info_index_addr_hi_v() (0x00000001U) +#define fb_mmu_vpr_info_index_cya_lo_v() (0x00000002U) +#define fb_mmu_vpr_info_index_cya_hi_v() (0x00000003U) +#define fb_mmu_vpr_info_fetch_f(v) (((v)&0x1U) << 2U) +#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U) +#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U) +#define fb_mmu_wpr_info_r() (0x00100cd4U) +#define fb_mmu_wpr_info_index_f(v) (((v)&0xfU) << 0U) +#define fb_mmu_wpr_info_index_allow_read_v() (0x00000000U) +#define fb_mmu_wpr_info_index_allow_write_v() (0x00000001U) +#define fb_mmu_wpr_info_index_wpr1_addr_lo_v() (0x00000002U) +#define fb_mmu_wpr_info_index_wpr1_addr_hi_v() (0x00000003U) +#define fb_mmu_wpr_info_index_wpr2_addr_lo_v() (0x00000004U) +#define fb_mmu_wpr_info_index_wpr2_addr_hi_v() (0x00000005U) +#define fb_niso_flush_sysmem_addr_r() (0x00100c10U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h index ef13206f0..1dc732736 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,524 +59,149 @@ #include #include -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return U32(0x3fffffffU) << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} +#define fifo_bar1_base_r() (0x00002254U) +#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) +#define fifo_bar1_base_valid_false_f() (0x0U) +#define fifo_bar1_base_valid_true_f() (0x10000000U) +#define fifo_runlist_base_r() (0x00002270U) +#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_runlist_base_target_vid_mem_f() (0x0U) +#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) +#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) +#define fifo_runlist_r() (0x00002274U) +#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) +#define fifo_eng_runlist_base_r(i)\ + (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist_base__size_1_v() (0x00000001U) +#define fifo_eng_runlist_r(i)\ + (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist__size_1_v() (0x00000001U) +#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) +#define fifo_eng_runlist_length_max_v() (0x0000ffffU) +#define fifo_eng_runlist_pending_true_f() (0x100000U) +#define fifo_pb_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pb_timeslice_timeout_16_f() (0x10U) +#define fifo_pb_timeslice_timescale_0_f() (0x0U) +#define fifo_pb_timeslice_enable_true_f() (0x10000000U) +#define fifo_pbdma_map_r(i)\ + (nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_0_r() (0x00002100U) +#define fifo_intr_0_bind_error_pending_f() (0x1U) +#define fifo_intr_0_bind_error_reset_f() (0x1U) +#define fifo_intr_0_sched_error_pending_f() (0x100U) +#define fifo_intr_0_sched_error_reset_f() (0x100U) +#define fifo_intr_0_chsw_error_pending_f() (0x10000U) +#define fifo_intr_0_chsw_error_reset_f() (0x10000U) +#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U) +#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U) +#define fifo_intr_0_lb_error_pending_f() (0x1000000U) +#define fifo_intr_0_lb_error_reset_f() (0x1000000U) +#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U) +#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U) +#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U) +#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U) +#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) +#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) +#define fifo_intr_en_0_r() (0x00002140U) +#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) +#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) +#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) +#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) +#define fifo_intr_en_1_r() (0x00002528U) +#define fifo_intr_bind_error_r() (0x0000252cU) +#define fifo_intr_sched_error_r() (0x0000254cU) +#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) +#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) +#define fifo_intr_chsw_error_r() (0x0000256cU) +#define fifo_intr_mmu_fault_id_r() (0x0000259cU) +#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U) +#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U) +#define fifo_intr_mmu_fault_inst_r(i)\ + (nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU) +#define fifo_intr_mmu_fault_lo_r(i)\ + (nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_hi_r(i)\ + (nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_r(i)\ + (nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0xfU) +#define fifo_intr_mmu_fault_info_write_v(r) (((r) >> 7U) & 0x1U) +#define fifo_intr_mmu_fault_info_engine_subid_v(r) (((r) >> 6U) & 0x1U) +#define fifo_intr_mmu_fault_info_engine_subid_gpc_v() (0x00000000U) +#define fifo_intr_mmu_fault_info_engine_subid_hub_v() (0x00000001U) +#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x3fU) +#define fifo_intr_pbdma_id_r() (0x000025a0U) +#define fifo_intr_pbdma_id_status_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_pbdma_id_status_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U) +#define fifo_intr_runlist_r() (0x00002a00U) +#define fifo_fb_timeout_r() (0x00002a04U) +#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U) +#define fifo_fb_timeout_period_max_f() (0x3fffffffU) +#define fifo_error_sched_disable_r() (0x0000262cU) +#define fifo_sched_disable_r() (0x00002630U) +#define fifo_sched_disable_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_sched_disable_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_sched_disable_true_v() (0x00000001U) +#define fifo_preempt_r() (0x00002634U) +#define fifo_preempt_pending_true_f() (0x100000U) +#define fifo_preempt_type_channel_f() (0x0U) +#define fifo_preempt_type_tsg_f() (0x1000000U) +#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) +#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) +#define fifo_trigger_mmu_fault_r(i)\ + (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) +#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) +#define fifo_engine_status_r(i)\ + (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_engine_status__size_1_v() (0x00000002U) +#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_engine_status_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U) +#define fifo_engine_status_ctx_status_valid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U) +#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U) +#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U) +#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_engine_status_next_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U) +#define fifo_engine_status_faulted_true_v() (0x00000001U) +#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U) +#define fifo_engine_status_engine_idle_v() (0x00000000U) +#define fifo_engine_status_engine_busy_v() (0x00000001U) +#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U) +#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U) +#define fifo_pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pbdma_status__size_1_v() (0x00000001U) +#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_pbdma_status_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U) +#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U) +#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U) +#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h index b09052d03..50c45deda 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,132 +59,36 @@ #include #include -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} +#define flush_l2_system_invalidate_r() (0x00070004U) +#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U) +#define flush_l2_system_invalidate_pending_busy_f() (0x1U) +#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U) +#define flush_l2_flush_dirty_r() (0x00070010U) +#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U) +#define flush_l2_flush_dirty_pending_empty_f() (0x0U) +#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U) +#define flush_l2_flush_dirty_pending_busy_f() (0x1U) +#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U) +#define flush_l2_flush_dirty_outstanding_false_f() (0x0U) +#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U) +#define flush_l2_clean_comptags_r() (0x0007000cU) +#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U) +#define flush_l2_clean_comptags_pending_empty_f() (0x0U) +#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U) +#define flush_l2_clean_comptags_pending_busy_f() (0x1U) +#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U) +#define flush_l2_clean_comptags_outstanding_false_f() (0x0U) +#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U) +#define flush_fb_flush_r() (0x00070000U) +#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_fb_flush_pending_busy_v() (0x00000001U) +#define flush_fb_flush_pending_busy_f() (0x1U) +#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_fb_flush_outstanding_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h index 1478b3c44..822a60a79 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,92 +59,30 @@ #include #include -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_sec_debug_en_r(void) -{ - return 0x00021218U; -} -static inline u32 fuse_opt_priv_sec_en_r(void) -{ - return 0x00021434U; -} +#define fuse_status_opt_gpc_r() (0x00021c1cU) +#define fuse_status_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) +#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0x3U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U) +#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) +#define fuse_status_opt_fbio_r() (0x00021c14U) +#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) +#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) +#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) +#define fuse_status_opt_rop_l2_fbp_r(i)\ + (nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_status_opt_fbp_r() (0x00021d38U) +#define fuse_status_opt_fbp_idx_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fuse_opt_sec_debug_en_r() (0x00021218U) +#define fuse_opt_priv_sec_en_r() (0x00021434U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h index f3aa728fa..938be104b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,228 +59,60 @@ #include #include -static inline u32 gmmu_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_big_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_size_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_size_full_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pde_aperture_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_aperture_small_video_memory_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 gmmu_pde_vol_small_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_small_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_vol_big_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pde_address_small_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pde_address_small_sys_w(void) -{ - return 1U; -} -static inline u32 gmmu_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_privilege_true_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_address_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_address_vid_f(u32 v) -{ - return (v & 0x1ffffffU) << 4U; -} -static inline u32 gmmu_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_vol_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_vol_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_pte_read_only_true_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_pte_write_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_write_disable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gmmu_pte_read_disable_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_read_disable_true_f(void) -{ - return 0x40000000U; -} -static inline u32 gmmu_pte_comptagline_s(void) -{ - return 17U; -} -static inline u32 gmmu_pte_comptagline_f(u32 v) -{ - return (v & 0x1ffffU) << 12U; -} -static inline u32 gmmu_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} +#define gmmu_pde_aperture_big_w() (0U) +#define gmmu_pde_aperture_big_invalid_f() (0x0U) +#define gmmu_pde_aperture_big_video_memory_f() (0x1U) +#define gmmu_pde_aperture_big_sys_mem_coh_f() (0x2U) +#define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U) +#define gmmu_pde_size_w() (0U) +#define gmmu_pde_size_full_f() (0x0U) +#define gmmu_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_pde_address_big_sys_w() (0U) +#define gmmu_pde_aperture_small_w() (1U) +#define gmmu_pde_aperture_small_invalid_f() (0x0U) +#define gmmu_pde_aperture_small_video_memory_f() (0x1U) +#define gmmu_pde_aperture_small_sys_mem_coh_f() (0x2U) +#define gmmu_pde_aperture_small_sys_mem_ncoh_f() (0x3U) +#define gmmu_pde_vol_small_w() (1U) +#define gmmu_pde_vol_small_true_f() (0x4U) +#define gmmu_pde_vol_small_false_f() (0x0U) +#define gmmu_pde_vol_big_w() (1U) +#define gmmu_pde_vol_big_true_f() (0x8U) +#define gmmu_pde_vol_big_false_f() (0x0U) +#define gmmu_pde_address_small_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_pde_address_small_sys_w() (1U) +#define gmmu_pde_address_shift_v() (0x0000000cU) +#define gmmu_pde__size_v() (0x00000008U) +#define gmmu_pte__size_v() (0x00000008U) +#define gmmu_pte_valid_w() (0U) +#define gmmu_pte_valid_true_f() (0x1U) +#define gmmu_pte_valid_false_f() (0x0U) +#define gmmu_pte_privilege_w() (0U) +#define gmmu_pte_privilege_true_f() (0x2U) +#define gmmu_pte_privilege_false_f() (0x0U) +#define gmmu_pte_address_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_pte_address_sys_w() (0U) +#define gmmu_pte_address_vid_f(v) (((v)&0x1ffffffU) << 4U) +#define gmmu_pte_address_vid_w() (0U) +#define gmmu_pte_vol_w() (1U) +#define gmmu_pte_vol_true_f() (0x1U) +#define gmmu_pte_vol_false_f() (0x0U) +#define gmmu_pte_aperture_w() (1U) +#define gmmu_pte_aperture_video_memory_f() (0x0U) +#define gmmu_pte_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_pte_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_pte_read_only_w() (0U) +#define gmmu_pte_read_only_true_f() (0x4U) +#define gmmu_pte_write_disable_w() (1U) +#define gmmu_pte_write_disable_true_f() (0x80000000U) +#define gmmu_pte_read_disable_w() (1U) +#define gmmu_pte_read_disable_true_f() (0x40000000U) +#define gmmu_pte_comptagline_s() (17U) +#define gmmu_pte_comptagline_f(v) (((v)&0x1ffffU) << 12U) +#define gmmu_pte_comptagline_w() (1U) +#define gmmu_pte_address_shift_v() (0x0000000cU) +#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) +#define gmmu_pte_kind_w() (1U) +#define gmmu_pte_kind_invalid_v() (0x000000ffU) +#define gmmu_pte_kind_pitch_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index f646c3d27..febc53415 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,3860 +59,1021 @@ #include #include -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_on_status_r(void) -{ - return 0x00404150U; -} -static inline u32 gr_pri_fe_go_idle_check_r(void) -{ - return 0x00404158U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(void) -{ - return 0x004041c4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_irqsset_r(void) -{ - return 0x00409000U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_irqsset_r(void) -{ - return 0x0041a000U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void) -{ - return 0x0000003dU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return U32(0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x000001c0U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000182U; -} -static inline u32 gr_pd_pagepool_r(void) -{ - return 0x004064ccU; -} -static inline u32 gr_pd_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32(i, 0U)); -} -static inline u32 gr_gpccs_rc_lane_size__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000400U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void) -{ - return 0x00419a3cU; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return U32(0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) -{ - return 0x00418e30U; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return U32(0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00504644U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) -{ - return 0x0050461cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) -{ - return 0x00504750U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) -{ - return 0x00504758U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) -{ - return 0x00504654U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return U32(0x3U) << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return U32(0x3U) << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} +#define gr_intr_r() (0x00400100U) +#define gr_intr_notify_pending_f() (0x1U) +#define gr_intr_notify_reset_f() (0x1U) +#define gr_intr_semaphore_pending_f() (0x2U) +#define gr_intr_semaphore_reset_f() (0x2U) +#define gr_intr_illegal_method_pending_f() (0x10U) +#define gr_intr_illegal_method_reset_f() (0x10U) +#define gr_intr_illegal_notify_pending_f() (0x40U) +#define gr_intr_illegal_notify_reset_f() (0x40U) +#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) +#define gr_intr_firmware_method_pending_f() (0x100U) +#define gr_intr_firmware_method_reset_f() (0x100U) +#define gr_intr_illegal_class_pending_f() (0x20U) +#define gr_intr_illegal_class_reset_f() (0x20U) +#define gr_intr_fecs_error_pending_f() (0x80000U) +#define gr_intr_fecs_error_reset_f() (0x80000U) +#define gr_intr_class_error_pending_f() (0x100000U) +#define gr_intr_class_error_reset_f() (0x100000U) +#define gr_intr_exception_pending_f() (0x200000U) +#define gr_intr_exception_reset_f() (0x200000U) +#define gr_fecs_intr_r() (0x00400144U) +#define gr_class_error_r() (0x00400110U) +#define gr_class_error_code_v(r) (((r) >> 0U) & 0xffffU) +#define gr_intr_nonstall_r() (0x00400120U) +#define gr_intr_nonstall_trap_pending_f() (0x2U) +#define gr_intr_en_r() (0x0040013cU) +#define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception1_r() (0x00400118U) +#define gr_exception1_gpc_0_pending_f() (0x1U) +#define gr_exception2_r() (0x0040011cU) +#define gr_exception_en_r() (0x00400138U) +#define gr_exception_en_fe_m() (U32(0x1U) << 0U) +#define gr_exception1_en_r() (0x00400130U) +#define gr_exception2_en_r() (0x00400134U) +#define gr_gpfifo_ctl_r() (0x00400500U) +#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) +#define gr_gpfifo_ctl_access_disabled_f() (0x0U) +#define gr_gpfifo_ctl_access_enabled_f() (0x1U) +#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) +#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) +#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) +#define gr_gpfifo_status_r() (0x00400504U) +#define gr_trapped_addr_r() (0x00400704U) +#define gr_trapped_addr_mthd_v(r) (((r) >> 2U) & 0xfffU) +#define gr_trapped_addr_subch_v(r) (((r) >> 16U) & 0x7U) +#define gr_trapped_addr_mme_generated_v(r) (((r) >> 20U) & 0x1U) +#define gr_trapped_addr_datahigh_v(r) (((r) >> 24U) & 0x1U) +#define gr_trapped_addr_priv_v(r) (((r) >> 28U) & 0x1U) +#define gr_trapped_addr_status_v(r) (((r) >> 31U) & 0x1U) +#define gr_trapped_data_lo_r() (0x00400708U) +#define gr_trapped_data_hi_r() (0x0040070cU) +#define gr_trapped_data_mme_r() (0x00400710U) +#define gr_trapped_data_mme_pc_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_status_r() (0x00400700U) +#define gr_status_fe_method_upper_v(r) (((r) >> 1U) & 0x1U) +#define gr_status_fe_method_lower_v(r) (((r) >> 2U) & 0x1U) +#define gr_status_fe_method_lower_idle_v() (0x00000000U) +#define gr_status_fe_gi_v(r) (((r) >> 21U) & 0x1U) +#define gr_status_mask_r() (0x00400610U) +#define gr_status_1_r() (0x00400604U) +#define gr_status_2_r() (0x00400608U) +#define gr_engine_status_r() (0x0040060cU) +#define gr_engine_status_value_busy_f() (0x1U) +#define gr_pri_be0_becs_be_exception_r() (0x00410204U) +#define gr_pri_be0_becs_be_exception_en_r() (0x00410208U) +#define gr_pri_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_pri_gpc0_gpccs_gpc_exception_en_r() (0x00502c94U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_activity_0_r() (0x00400380U) +#define gr_activity_1_r() (0x00400384U) +#define gr_activity_2_r() (0x00400388U) +#define gr_activity_4_r() (0x00400390U) +#define gr_pri_gpc0_gcc_dbg_r() (0x00501000U) +#define gr_pri_gpcs_gcc_dbg_r() (0x00419000U) +#define gr_pri_gpcs_gcc_dbg_invalidate_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cache_control_r() (0x005046a4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_r() (0x00419ea4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m() (U32(0x1U) << 0U) +#define gr_pri_sked_activity_r() (0x00407054U) +#define gr_pri_gpc0_gpccs_gpc_activity0_r() (0x00502c80U) +#define gr_pri_gpc0_gpccs_gpc_activity1_r() (0x00502c84U) +#define gr_pri_gpc0_gpccs_gpc_activity2_r() (0x00502c88U) +#define gr_pri_gpc0_gpccs_gpc_activity3_r() (0x00502c8cU) +#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() (0x00504500U) +#define gr_pri_gpcs_gpccs_gpc_activity_0_r() (0x0041ac80U) +#define gr_pri_gpcs_gpccs_gpc_activity_1_r() (0x0041ac84U) +#define gr_pri_gpcs_gpccs_gpc_activity_2_r() (0x0041ac88U) +#define gr_pri_gpcs_gpccs_gpc_activity_3_r() (0x0041ac8cU) +#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r() (0x00419d00U) +#define gr_pri_be0_becs_be_activity0_r() (0x00410200U) +#define gr_pri_bes_becs_be_activity0_r() (0x00408a00U) +#define gr_pri_ds_mpipe_status_r() (0x00405858U) +#define gr_pri_fe_go_idle_on_status_r() (0x00404150U) +#define gr_pri_fe_go_idle_check_r() (0x00404158U) +#define gr_pri_fe_go_idle_info_r() (0x00404194U) +#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r() (0x00504238U) +#define gr_pri_be0_crop_status1_r() (0x00410134U) +#define gr_pri_bes_crop_status1_r() (0x00408934U) +#define gr_pri_be0_zrop_status_r() (0x00410048U) +#define gr_pri_be0_zrop_status2_r() (0x0041004cU) +#define gr_pri_bes_zrop_status_r() (0x00408848U) +#define gr_pri_bes_zrop_status2_r() (0x0040884cU) +#define gr_pipe_bundle_address_r() (0x00400200U) +#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pipe_bundle_data_r() (0x00400204U) +#define gr_pipe_bundle_config_r() (0x00400208U) +#define gr_pipe_bundle_config_override_pipe_mode_disabled_f() (0x0U) +#define gr_pipe_bundle_config_override_pipe_mode_enabled_f() (0x80000000U) +#define gr_fe_hww_esr_r() (0x00404000U) +#define gr_fe_hww_esr_reset_active_f() (0x40000000U) +#define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) +#define gr_fe_go_idle_timeout_r() (0x00404154U) +#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) +#define gr_fe_go_idle_timeout_count_prod_f() (0x800U) +#define gr_fe_object_table_r(i)\ + (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) +#define gr_fe_tpc_fs_r() (0x004041c4U) +#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) +#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_mme_hww_esr_r() (0x00404490U) +#define gr_mme_hww_esr_reset_active_f() (0x40000000U) +#define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) +#define gr_memfmt_hww_esr_r() (0x00404600U) +#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) +#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) +#define gr_fecs_cpuctl_r() (0x00409100U) +#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_cpuctl_alias_r() (0x00409130U) +#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_dmactl_r() (0x0040910cU) +#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_fecs_os_r() (0x00409080U) +#define gr_fecs_idlestate_r() (0x0040904cU) +#define gr_fecs_mailbox0_r() (0x00409040U) +#define gr_fecs_mailbox1_r() (0x00409044U) +#define gr_fecs_irqstat_r() (0x00409008U) +#define gr_fecs_irqmode_r() (0x0040900cU) +#define gr_fecs_irqmask_r() (0x00409018U) +#define gr_fecs_irqdest_r() (0x0040901cU) +#define gr_fecs_curctx_r() (0x00409050U) +#define gr_fecs_nxtctx_r() (0x00409054U) +#define gr_fecs_engctl_r() (0x004090a4U) +#define gr_fecs_debug1_r() (0x00409090U) +#define gr_fecs_debuginfo_r() (0x00409094U) +#define gr_fecs_icd_cmd_r() (0x00409200U) +#define gr_fecs_icd_cmd_opc_s() (4U) +#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) +#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) +#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define gr_fecs_icd_rdata_r() (0x0040920cU) +#define gr_fecs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmemc_offs_s() (6U) +#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) +#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmatrfbase_r() (0x00409110U) +#define gr_fecs_dmatrfmoffs_r() (0x00409114U) +#define gr_fecs_dmatrffboffs_r() (0x0040911cU) +#define gr_fecs_dmatrfcmd_r() (0x00409118U) +#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define gr_fecs_bootvec_r() (0x00409104U) +#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_irqsset_r() (0x00409000U) +#define gr_fecs_falcon_hwcfg_r() (0x00409108U) +#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) +#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) +#define gr_fecs_falcon_rm_r() (0x00409084U) +#define gr_fecs_current_ctx_r() (0x00409b00U) +#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_current_ctx_target_s() (2U) +#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_current_ctx_valid_s() (1U) +#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_current_ctx_valid_false_f() (0x0U) +#define gr_fecs_method_data_r() (0x00409500U) +#define gr_fecs_method_push_r() (0x00409504U) +#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) +#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) +#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) +#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) +#define gr_fecs_method_push_adr_wfi_golden_save_v() (0x00000009U) +#define gr_fecs_method_push_adr_restore_golden_v() (0x00000015U) +#define gr_fecs_method_push_adr_discover_zcull_image_size_v() (0x00000016U) +#define gr_fecs_method_push_adr_discover_pm_image_size_v() (0x00000025U) +#define gr_fecs_method_push_adr_discover_reglist_image_size_v() (0x00000030U) +#define gr_fecs_method_push_adr_set_reglist_bind_instance_v() (0x00000031U) +#define gr_fecs_method_push_adr_set_reglist_virtual_address_v() (0x00000032U) +#define gr_fecs_method_push_adr_stop_ctxsw_v() (0x00000038U) +#define gr_fecs_method_push_adr_start_ctxsw_v() (0x00000039U) +#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) +#define gr_fecs_method_push_adr_write_timestamp_record_v() (0x0000003dU) +#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) +#define gr_fecs_host_int_status_r() (0x00409c18U) +#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) +#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) +#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) +#define gr_fecs_host_int_status_watchdog_active_f() (0x80000U) +#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_host_int_clear_r() (0x00409c20U) +#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) +#define gr_fecs_host_int_enable_r() (0x00409c24U) +#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) +#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) +#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f() (0x20000U) +#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f() (0x40000U) +#define gr_fecs_host_int_enable_watchdog_enable_f() (0x80000U) +#define gr_fecs_ctxsw_reset_ctl_r() (0x00409614U) +#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() (0x10U) +#define gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() (0x20U) +#define gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() (0x40U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() (0x100U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f() (0x400U) +#define gr_fecs_ctx_state_store_major_rev_id_r() (0x0040960cU) +#define gr_fecs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) +#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) +#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) +#define gr_fecs_ctxsw_mailbox_set_r(i)\ + (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_clear_r(i)\ + (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_fs_r() (0x00409604U) +#define gr_fecs_fs_num_available_gpcs_s() (5U) +#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_fs_num_available_fbps_s() (5U) +#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) +#define gr_fecs_cfg_r() (0x00409620U) +#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_fecs_rc_lanes_r() (0x00409880U) +#define gr_fecs_rc_lanes_num_chains_s() (6U) +#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_fecs_ctxsw_status_1_r() (0x00409400U) +#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) +#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) +#define gr_fecs_new_ctx_r() (0x00409b04U) +#define gr_fecs_new_ctx_ptr_s() (28U) +#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_new_ctx_target_s() (2U) +#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_new_ctx_valid_s() (1U) +#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) +#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) +#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_arb_ctx_ptr_target_s() (2U) +#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) +#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) +#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) +#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r() (0x00502c04U) +#define gr_gpc0_gpccs_ctxsw_status_1_r() (0x00502400U) +#define gr_fecs_ctxsw_idlestate_r() (0x00409420U) +#define gr_gpc0_gpccs_ctxsw_idlestate_r() (0x00502420U) +#define gr_rstr2d_gpc_map0_r() (0x0040780cU) +#define gr_rstr2d_gpc_map1_r() (0x00407810U) +#define gr_rstr2d_gpc_map2_r() (0x00407814U) +#define gr_rstr2d_gpc_map3_r() (0x00407818U) +#define gr_rstr2d_gpc_map4_r() (0x0040781cU) +#define gr_rstr2d_gpc_map5_r() (0x00407820U) +#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) +#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_pd_hww_esr_r() (0x00406018U) +#define gr_pd_hww_esr_reset_active_f() (0x40000000U) +#define gr_pd_hww_esr_en_enable_f() (0x80000000U) +#define gr_pd_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) +#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) +#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) +#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) +#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) +#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) +#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) +#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) +#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) +#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) +#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) +#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) +#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) +#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) +#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) +#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0xfffU) << 0U) +#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x000001c0U) +#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0xfffU) << 16U) +#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) +#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000182U) +#define gr_pd_pagepool_r() (0x004064ccU) +#define gr_pd_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) +#define gr_pd_pagepool_valid_true_f() (0x80000000U) +#define gr_pd_dist_skip_table_r(i)\ + (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) +#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_ds_debug_r() (0x00405800U) +#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) +#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) +#define gr_ds_zbc_color_r_r() (0x00405804U) +#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_g_r() (0x00405808U) +#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_b_r() (0x0040580cU) +#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_a_r() (0x00405810U) +#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_fmt_r() (0x00405814U) +#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) +#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) +#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) +#define gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v() (0x00000004U) +#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) +#define gr_ds_zbc_z_r() (0x00405818U) +#define gr_ds_zbc_z_val_s() (32U) +#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_ds_zbc_z_val__init_v() (0x00000000U) +#define gr_ds_zbc_z_val__init_f() (0x0U) +#define gr_ds_zbc_z_fmt_r() (0x0040581cU) +#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) +#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) +#define gr_ds_zbc_tbl_index_r() (0x00405820U) +#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) +#define gr_ds_zbc_tbl_ld_r() (0x00405824U) +#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) +#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) +#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) +#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) +#define gr_ds_tga_constraintlogic_r() (0x00405830U) +#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0xffffU) << 16U) +#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) +#define gr_ds_hww_esr_r() (0x00405840U) +#define gr_ds_hww_esr_reset_s() (1U) +#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) +#define gr_ds_hww_esr_2_r() (0x00405848U) +#define gr_ds_hww_esr_2_reset_s() (1U) +#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_2_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_2_en_enabled_f() (0x80000000U) +#define gr_ds_hww_report_mask_r() (0x00405844U) +#define gr_ds_hww_report_mask_sph0_err_report_f() (0x1U) +#define gr_ds_hww_report_mask_sph1_err_report_f() (0x2U) +#define gr_ds_hww_report_mask_sph2_err_report_f() (0x4U) +#define gr_ds_hww_report_mask_sph3_err_report_f() (0x8U) +#define gr_ds_hww_report_mask_sph4_err_report_f() (0x10U) +#define gr_ds_hww_report_mask_sph5_err_report_f() (0x20U) +#define gr_ds_hww_report_mask_sph6_err_report_f() (0x40U) +#define gr_ds_hww_report_mask_sph7_err_report_f() (0x80U) +#define gr_ds_hww_report_mask_sph8_err_report_f() (0x100U) +#define gr_ds_hww_report_mask_sph9_err_report_f() (0x200U) +#define gr_ds_hww_report_mask_sph10_err_report_f() (0x400U) +#define gr_ds_hww_report_mask_sph11_err_report_f() (0x800U) +#define gr_ds_hww_report_mask_sph12_err_report_f() (0x1000U) +#define gr_ds_hww_report_mask_sph13_err_report_f() (0x2000U) +#define gr_ds_hww_report_mask_sph14_err_report_f() (0x4000U) +#define gr_ds_hww_report_mask_sph15_err_report_f() (0x8000U) +#define gr_ds_hww_report_mask_sph16_err_report_f() (0x10000U) +#define gr_ds_hww_report_mask_sph17_err_report_f() (0x20000U) +#define gr_ds_hww_report_mask_sph18_err_report_f() (0x40000U) +#define gr_ds_hww_report_mask_sph19_err_report_f() (0x80000U) +#define gr_ds_hww_report_mask_sph20_err_report_f() (0x100000U) +#define gr_ds_hww_report_mask_sph21_err_report_f() (0x200000U) +#define gr_ds_hww_report_mask_sph22_err_report_f() (0x400000U) +#define gr_ds_hww_report_mask_sph23_err_report_f() (0x800000U) +#define gr_ds_hww_report_mask_2_r() (0x0040584cU) +#define gr_ds_hww_report_mask_2_sph24_err_report_f() (0x1U) +#define gr_ds_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_scc_bundle_cb_base_r() (0x00408004U) +#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_bundle_cb_size_r() (0x00408008U) +#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U) +#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) +#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_scc_pagepool_base_r() (0x0040800cU) +#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_pagepool_r() (0x00408010U) +#define gr_scc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) +#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) +#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000080U) +#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) +#define gr_scc_pagepool_max_valid_pages_s() (8U) +#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0xffU) << 8U) +#define gr_scc_pagepool_max_valid_pages_m() (U32(0xffU) << 8U) +#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 8U) & 0xffU) +#define gr_scc_pagepool_valid_true_f() (0x80000000U) +#define gr_scc_hww_esr_r() (0x00408030U) +#define gr_scc_hww_esr_reset_active_f() (0x40000000U) +#define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) +#define gr_cwd_fs_r() (0x00405b00U) +#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) +#define gr_cwd_gpc_tpc_id_r(i)\ + (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) +#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) +#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) +#define gr_cwd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_sm_id__size_1_v() (0x00000006U) +#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) +#define gr_gpc0_fs_gpc_r() (0x00502608U) +#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) +#define gr_gpc0_cfg_r() (0x00502620U) +#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpccs_rc_lanes_r() (0x00502880U) +#define gr_gpccs_rc_lanes_num_chains_s() (6U) +#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_rc_lane_size_r(i)\ + (nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32((i), 0U))) +#define gr_gpccs_rc_lane_size__size_1_v() (0x00000010U) +#define gr_gpccs_rc_lane_size_v_s() (24U) +#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) +#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) +#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) +#define gr_gpc0_zcull_fs_r() (0x00500910U) +#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) +#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) +#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ + (((v)&0xfU) << 0U) +#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) +#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) +#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) +#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) +#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_zcull_zcsize_r(i)\ + (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) +#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) +#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) +#define gr_gpc0_gpm_pd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ + (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) +#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) +#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) +#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU) +#define gr_gpc0_tpc0_sm_arch_sm_version_v(r) (((r) >> 20U) & 0xfffU) +#define gr_gpc0_ppc0_pes_vsc_strem_r() (0x00503018U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000400U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) +#define gr_gpcs_tpcs_tex_m_dbg2_r() (0x00419a3cU) +#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(v) (((v)&0x1U) << 2U) +#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m() (U32(0x1U) << 2U) +#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(v) (((v)&0x1U) << 4U) +#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m() (U32(0x1U) << 4U) +#define gr_gpccs_falcon_addr_r() (0x0041a0acU) +#define gr_gpccs_falcon_addr_lsb_s() (6U) +#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_msb_s() (6U) +#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) +#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_ext_s() (12U) +#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) +#define gr_gpccs_cpuctl_r() (0x0041a100U) +#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_gpccs_dmactl_r() (0x0041a10cU) +#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_gpccs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt__size_1_v() (0x00000004U) +#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_gpccs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000018U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x18U) +#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ + (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_div3_f(v) (((v)&0xffffU) << 16U) +#define gr_gpcs_swdx_tc_beta_cb_size_div3_m() (U32(0xffffU) << 16U) +#define gr_gpcs_swdx_rm_pagepool_r() (0x00418e30U) +#define gr_gpcs_swdx_rm_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) +#define gr_gpcs_swdx_rm_pagepool_valid_true_f() (0x80000000U) +#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) +#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) +#define gr_crstr_gpc_map0_r() (0x00418b08U) +#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map1_r() (0x00418b0cU) +#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map2_r() (0x00418b10U) +#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map3_r() (0x00418b14U) +#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map4_r() (0x00418b18U) +#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map5_r() (0x00418b1cU) +#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_map_table_cfg_r() (0x00418bb8U) +#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) +#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) +#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_gcc_pagepool_r() (0x00419008U) +#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) +#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) +#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f()\ + (0x20U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f()\ + (0x80U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\ + (0x200U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f()\ + (0x400U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f()\ + (0x800U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f()\ + (0x1000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f() (0x2000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f() (0x4000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f()\ + (0x8000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f()\ + (0x10000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f()\ + (0x20000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\ + (0x40000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f()\ + (0x800000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f()\ + (0x400000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f()\ + (0x80000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f()\ + (0x100000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() (0x00504644U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() (0x00419e4cU) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f()\ + (0x1U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f()\ + (0x40U) +#define gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r() (0x0050464cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r() (0x00419d0cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f() (0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) +#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) +#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) +#define gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm_dbgr_control0_r() (0x00504610U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m() (U32(0x1U) << 0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f() (0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m() (U32(0x1U) << 1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m() (U32(0x1U) << 2U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v()\ + (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v()\ + (0x00000000U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_r() (0x00504614U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_1_r() (0x00504618U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_2_r() (0x0050461cU) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() (0x00504624U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r() (0x00504628U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r() (0x00504750U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() (0x00504634U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r() (0x00504638U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r() (0x00504758U) +#define gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r() (0x00419e24U) +#define gr_gpc0_tpc0_sm_dbgr_status0_r() (0x0050460cU) +#define gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(r) (((r) >> 4U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_hww_global_esr_r() (0x00419e50U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f() (0x1U) +#define gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() (0x80000000U) +#define gr_gpc0_tpc0_sm_hww_global_esr_r() (0x00504650U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() (0x1U) +#define gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f() (0x2U) +#define gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f()\ + (0x8U) +#define gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f() (0x80000000U) +#define gr_gpc0_tpc0_tex_m_hww_esr_r() (0x00504224U) +#define gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f() (0x1U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_r() (0x00504648U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() (0x00504654U) +#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) +#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) +#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) +#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) +#define gr_ppcs_wwdx_map_gpc_map1_r() (0x0041bf04U) +#define gr_ppcs_wwdx_map_gpc_map2_r() (0x0041bf08U) +#define gr_ppcs_wwdx_map_gpc_map3_r() (0x0041bf0cU) +#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) +#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) +#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) +#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ + (((v)&0x1fU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ + (((v)&0x7U) << 21U) +#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) +#define gr_bes_zrop_settings_r() (0x00408850U) +#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_be0_crop_debug3_r() (0x00410108U) +#define gr_bes_crop_debug3_r() (0x00408908U) +#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) +#define gr_bes_crop_settings_r() (0x00408958U) +#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) +#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) +#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) +#define gr_zcull_subregion_qty_v() (0x00000010U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r() (0x00504604U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r() (0x00504608U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r() (0x0050465cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r() (0x00504660U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r() (0x00504664U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r() (0x00504668U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r() (0x0050466cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r() (0x00504658U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r() (0x00504730U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r() (0x00504734U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r() (0x00504738U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r() (0x0050473cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r() (0x00504740U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r() (0x00504744U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r() (0x00504748U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r() (0x0050474cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r() (0x00504678U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r() (0x00504694U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r() (0x005046f0U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r() (0x00504700U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r() (0x005046f4U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r() (0x00504704U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r() (0x005046f8U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r() (0x00504708U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r() (0x005046fcU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r() (0x0050470cU) +#define gr_fe_pwr_mode_r() (0x00404170U) +#define gr_fe_pwr_mode_mode_auto_f() (0x0U) +#define gr_fe_pwr_mode_mode_force_on_f() (0x2U) +#define gr_fe_pwr_mode_req_v(r) (((r) >> 4U) & 0x1U) +#define gr_fe_pwr_mode_req_send_f() (0x10U) +#define gr_fe_pwr_mode_req_done_v() (0x00000000U) +#define gr_gpcs_pri_mmu_ctrl_r() (0x00418880U) +#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() (U32(0x1U) << 0U) +#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() (U32(0x1U) << 11U) +#define gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() (U32(0x1U) << 12U) +#define gr_gpcs_pri_mmu_ctrl_vol_fault_m() (U32(0x1U) << 1U) +#define gr_gpcs_pri_mmu_ctrl_comp_fault_m() (U32(0x1U) << 2U) +#define gr_gpcs_pri_mmu_ctrl_miss_gran_m() (U32(0x3U) << 3U) +#define gr_gpcs_pri_mmu_ctrl_cache_mode_m() (U32(0x3U) << 5U) +#define gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() (U32(0x3U) << 28U) +#define gr_gpcs_pri_mmu_ctrl_mmu_vol_m() (U32(0x1U) << 30U) +#define gr_gpcs_pri_mmu_ctrl_mmu_disable_m() (U32(0x1U) << 31U) +#define gr_gpcs_pri_mmu_pm_unit_mask_r() (0x00418890U) +#define gr_gpcs_pri_mmu_pm_req_mask_r() (0x00418894U) +#define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f() (0x10000U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f() (0x0U) +#define gr_gpcs_pri_mmu_debug_wr_r() (0x004188b4U) +#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) +#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) +#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m() (U32(0x1U) << 3U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m() (U32(0x1U) << 30U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h index 5d46c993a..e5aff5788 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,424 +59,134 @@ #include #include -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0001ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} +#define ltc_pltcg_base_v() (0x00140000U) +#define ltc_pltcg_extent_v() (0x0017ffffU) +#define ltc_ltc0_ltss_v() (0x00140200U) +#define ltc_ltc0_lts0_v() (0x00140400U) +#define ltc_ltcs_ltss_v() (0x0017e200U) +#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U) +#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U) +#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U) +#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U) +#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U) +#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU) +#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) +#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) +#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x1ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x1ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU) +#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) +#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) +#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU) +#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U) +#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U) +#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU) +#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) +#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ + (((v)&0x1fU) << 16U) +#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ + (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ + (U32(0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffffffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U) +#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U) +#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U) +#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltcs_ltss_intr_r() (0x0017e20cU) +#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U) +#define ltc_ltc0_lts0_intr_r() (0x0014040cU) +#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\ + (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\ + (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\ + (0x40000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\ + (((r) >> 16U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U) +#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h index bfbad81d1..45dc1b37b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,232 +59,63 @@ #include #include -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_mask_0_r(void) -{ - return 0x00000640U; -} -static inline u32 mc_intr_mask_0_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_0_r(void) -{ - return 0x00000140U; -} -static inline u32 mc_intr_en_0_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_0_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_intr_mask_1_r(void) -{ - return 0x00000644U; -} -static inline u32 mc_intr_mask_1_pmu_s(void) -{ - return 1U; -} -static inline u32 mc_intr_mask_1_pmu_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 mc_intr_mask_1_pmu_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 mc_intr_mask_1_pmu_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 mc_intr_mask_1_pmu_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_en_1_r(void) -{ - return 0x00000144U; -} -static inline u32 mc_intr_en_1_inta_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_intr_en_1_inta_hardware_f(void) -{ - return 0x1U; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x0000017cU; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} +#define mc_boot_0_r() (0x00000000U) +#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU) +#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU) +#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU) +#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU) +#define mc_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_pfifo_pending_f() (0x100U) +#define mc_intr_pmu_pending_f() (0x1000000U) +#define mc_intr_ltc_pending_f() (0x2000000U) +#define mc_intr_priv_ring_pending_f() (0x40000000U) +#define mc_intr_pbus_pending_f() (0x10000000U) +#define mc_intr_mask_0_r() (0x00000640U) +#define mc_intr_mask_0_pmu_enabled_f() (0x1000000U) +#define mc_intr_en_0_r() (0x00000140U) +#define mc_intr_en_0_inta_disabled_f() (0x0U) +#define mc_intr_en_0_inta_hardware_f() (0x1U) +#define mc_intr_mask_1_r() (0x00000644U) +#define mc_intr_mask_1_pmu_s() (1U) +#define mc_intr_mask_1_pmu_f(v) (((v)&0x1U) << 24U) +#define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U) +#define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U) +#define mc_intr_mask_1_pmu_enabled_f() (0x1000000U) +#define mc_intr_en_1_r() (0x00000144U) +#define mc_intr_en_1_inta_disabled_f() (0x0U) +#define mc_intr_en_1_inta_hardware_f() (0x1U) +#define mc_enable_r() (0x00000200U) +#define mc_enable_xbar_enabled_f() (0x4U) +#define mc_enable_l2_enabled_f() (0x8U) +#define mc_enable_pmedia_s() (1U) +#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) +#define mc_enable_pmedia_m() (U32(0x1U) << 4U) +#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) +#define mc_enable_priv_ring_enabled_f() (0x20U) +#define mc_enable_ce0_m() (U32(0x1U) << 6U) +#define mc_enable_pfifo_enabled_f() (0x100U) +#define mc_enable_pgraph_enabled_f() (0x1000U) +#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U) +#define mc_enable_pwr_disabled_v() (0x00000000U) +#define mc_enable_pwr_enabled_f() (0x2000U) +#define mc_enable_pfb_enabled_f() (0x100000U) +#define mc_enable_ce2_m() (U32(0x1U) << 21U) +#define mc_enable_ce2_enabled_f() (0x200000U) +#define mc_enable_blg_enabled_f() (0x8000000U) +#define mc_enable_perfmon_enabled_f() (0x10000000U) +#define mc_enable_hub_enabled_f() (0x20000000U) +#define mc_intr_ltc_r() (0x0000017cU) +#define mc_enable_pb_r() (0x00000204U) +#define mc_enable_pb_0_s() (1U) +#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) +#define mc_enable_pb_0_m() (U32(0x1U) << 0U) +#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) +#define mc_enable_pb_0_enabled_v() (0x00000001U) +#define mc_enable_pb_sel_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define mc_elpg_enable_r() (0x0000020cU) +#define mc_elpg_enable_xbar_enabled_f() (0x4U) +#define mc_elpg_enable_pfb_enabled_f() (0x100000U) +#define mc_elpg_enable_hub_enabled_f() (0x20000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h index 722346370..860dcfe81 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,540 +59,178 @@ #include #include -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_timeout_period_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method3_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_data0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000U; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} +#define pbdma_gp_entry1_r() (0x10000004U) +#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) +#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) +#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) +#define pbdma_gp_base_r(i)\ + (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base__size_1_v() (0x00000001U) +#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) +#define pbdma_gp_base_rsvd_s() (3U) +#define pbdma_gp_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) +#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) +#define pbdma_gp_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_get_r(i)\ + (nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_put_r(i)\ + (nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout_r(i)\ + (nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout__size_1_v() (0x00000001U) +#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U) +#define pbdma_timeout_period_max_f() (0xffffffffU) +#define pbdma_pb_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_r(i)\ + (nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_r(i)\ + (nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_r(i)\ + (nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_gp_fermi0_f() (0x0U) +#define pbdma_formats_pb_fermi1_f() (0x100U) +#define pbdma_formats_mp_fermi0_f() (0x0U) +#define pbdma_pb_header_r(i)\ + (nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_priv_user_f() (0x0U) +#define pbdma_pb_header_method_zero_f() (0x0U) +#define pbdma_pb_header_subchannel_zero_f() (0x0U) +#define pbdma_pb_header_level_main_f() (0x0U) +#define pbdma_pb_header_first_true_f() (0x400000U) +#define pbdma_pb_header_type_inc_f() (0x20000000U) +#define pbdma_pb_header_type_non_inc_f() (0x60000000U) +#define pbdma_hdr_shadow_r(i)\ + (nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_0_r(i)\ + (nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_1_r(i)\ + (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_r(i)\ + (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) +#define pbdma_subdevice_status_active_f() (0x10000000U) +#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) +#define pbdma_method0_r(i)\ + (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method0_fifo_size_v() (0x00000004U) +#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) +#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) +#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) +#define pbdma_method0_first_true_f() (0x400000U) +#define pbdma_method0_valid_true_f() (0x80000000U) +#define pbdma_method1_r(i)\ + (nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method2_r(i)\ + (nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method3_r(i)\ + (nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_data0_r(i)\ + (nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_r(i)\ + (nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_engine_sw_f() (0x1fU) +#define pbdma_acquire_r(i)\ + (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_retry_man_2_f() (0x2U) +#define pbdma_acquire_retry_exp_2_f() (0x100U) +#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) +#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) +#define pbdma_acquire_timeout_exp_max_f() (0x7800U) +#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) +#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) +#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) +#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) +#define pbdma_acquire_timeout_en_disable_f() (0x0U) +#define pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_channel_r(i)\ + (nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_r(i)\ + (nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_hw_valid_f() (0xfaceU) +#define pbdma_signature_sw_zero_f() (0x0U) +#define pbdma_userd_r(i)\ + (nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_target_vid_mem_f() (0x0U) +#define pbdma_userd_target_sys_mem_coh_f() (0x2U) +#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) +#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) +#define pbdma_userd_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) +#define pbdma_hce_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) +#define pbdma_intr_0_r(i)\ + (nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_intr_0_memreq_pending_f() (0x1U) +#define pbdma_intr_0_memack_timeout_pending_f() (0x2U) +#define pbdma_intr_0_memack_extra_pending_f() (0x4U) +#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U) +#define pbdma_intr_0_memdat_extra_pending_f() (0x10U) +#define pbdma_intr_0_memflush_pending_f() (0x20U) +#define pbdma_intr_0_memop_pending_f() (0x40U) +#define pbdma_intr_0_lbconnect_pending_f() (0x80U) +#define pbdma_intr_0_lbreq_pending_f() (0x100U) +#define pbdma_intr_0_lback_timeout_pending_f() (0x200U) +#define pbdma_intr_0_lback_extra_pending_f() (0x400U) +#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U) +#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U) +#define pbdma_intr_0_gpfifo_pending_f() (0x2000U) +#define pbdma_intr_0_gpptr_pending_f() (0x4000U) +#define pbdma_intr_0_gpentry_pending_f() (0x8000U) +#define pbdma_intr_0_gpcrc_pending_f() (0x10000U) +#define pbdma_intr_0_pbptr_pending_f() (0x20000U) +#define pbdma_intr_0_pbentry_pending_f() (0x40000U) +#define pbdma_intr_0_pbcrc_pending_f() (0x80000U) +#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U) +#define pbdma_intr_0_method_pending_f() (0x200000U) +#define pbdma_intr_0_methodcrc_pending_f() (0x400000U) +#define pbdma_intr_0_device_pending_f() (0x800000U) +#define pbdma_intr_0_semaphore_pending_f() (0x2000000U) +#define pbdma_intr_0_acquire_pending_f() (0x4000000U) +#define pbdma_intr_0_pri_pending_f() (0x8000000U) +#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U) +#define pbdma_intr_0_pbseg_pending_f() (0x40000000U) +#define pbdma_intr_0_signature_pending_f() (0x80000000U) +#define pbdma_intr_1_r(i)\ + (nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_r(i)\ + (nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U) +#define pbdma_intr_en_1_r(i)\ + (nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_r(i)\ + (nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_lbreq_enabled_f() (0x100U) +#define pbdma_intr_stall_1_r(i)\ + (nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U) +#define pbdma_udma_nop_r() (0x00000008U) +#define pbdma_syncpointa_r(i)\ + (nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU) +#define pbdma_syncpointb_r(i)\ + (nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_syncpointb_op_v(r) (((r) >> 0U) & 0x3U) +#define pbdma_syncpointb_op_wait_v() (0x00000000U) +#define pbdma_syncpointb_wait_switch_v(r) (((r) >> 4U) & 0x1U) +#define pbdma_syncpointb_wait_switch_en_v() (0x00000001U) +#define pbdma_syncpointb_syncpt_index_v(r) (((r) >> 8U) & 0xffU) +#define pbdma_runlist_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_runlist_timeslice_timeout_128_f() (0x80U) +#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U) +#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h index 25e966e8a..ce80c97bf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,164 +59,44 @@ #include #include -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x001b0000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x001b0fffU; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} +#define perf_pmmsys_base_v() (0x001b0000U) +#define perf_pmmsys_extent_v() (0x001b0fffU) +#define perf_pmasys_control_r() (0x001b4000U) +#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) +#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) +#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) +#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) +#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) +#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) +#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_mem_block_r() (0x001b4070U) +#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) +#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) +#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) +#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) +#define perf_pmasys_mem_block_target_lfb_f() (0x0U) +#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U) +#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) +#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) +#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) +#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) +#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) +#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) +#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) +#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) +#define perf_pmasys_mem_block_valid_false_f() (0x0U) +#define perf_pmasys_outbase_r() (0x001b4074U) +#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_outbaseupper_r() (0x001b4078U) +#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) +#define perf_pmasys_outsize_r() (0x001b407cU) +#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_mem_bytes_r() (0x001b4084U) +#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_mem_bump_r() (0x001b4088U) +#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_enginestatus_r() (0x001b40a4U) +#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) +#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) +#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h index b9b22f7a9..7bb76e58a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pram_data032_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U)); -} +#define pram_data032_r(i)\ + (nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h index 4015111bc..5aceb9eca 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,112 +59,33 @@ #include #include -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} +#define pri_ringmaster_command_r() (0x0012004cU) +#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U) +#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU) +#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U) +#define pri_ringmaster_command_cmd_start_ring_f() (0x1U) +#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U) +#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U) +#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U) +#define pri_ringmaster_command_data_r() (0x00120048U) +#define pri_ringmaster_start_results_r() (0x00120050U) +#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U) +#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U) +#define pri_ringmaster_intr_status0_r() (0x00120058U) +#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\ + (((r) >> 0U) & 0x1U) +#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U) +#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U) +#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\ + (((r) >> 8U) & 0x1U) +#define pri_ringmaster_intr_status1_r() (0x0012005cU) +#define pri_ringmaster_global_ctl_r() (0x00120060U) +#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U) +#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U) +#define pri_ringmaster_enum_fbp_r() (0x00120074U) +#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_gpc_r() (0x00120078U) +#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_ltc_r() (0x0012006cU) +#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h index e18d0ed45..1986dea79 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,24 +59,10 @@ #include #include -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} +#define pri_ringstation_gpc_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U) +#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) +#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) +#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h index 7cacabe2f..526cfdd88 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,36 +59,14 @@ #include #include -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} +#define pri_ringstation_sys_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_sys_decode_config_r() (0x00122204U) +#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U) +#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\ + (0x1U) +#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U) +#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) +#define pri_ringstation_sys_priv_error_info_r() (0x00122128U) +#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h index d15804b3c..5c3742452 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,116 +59,32 @@ #include #include -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00001000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} +#define proj_gpc_base_v() (0x00500000U) +#define proj_gpc_shared_base_v() (0x00418000U) +#define proj_gpc_stride_v() (0x00008000U) +#define proj_gpc_priv_stride_v() (0x00000800U) +#define proj_ltc_stride_v() (0x00002000U) +#define proj_lts_stride_v() (0x00000200U) +#define proj_fbpa_stride_v() (0x00001000U) +#define proj_ppc_in_gpc_base_v() (0x00003000U) +#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U) +#define proj_ppc_in_gpc_stride_v() (0x00000200U) +#define proj_rop_base_v() (0x00410000U) +#define proj_rop_shared_base_v() (0x00408800U) +#define proj_rop_stride_v() (0x00000400U) +#define proj_tpc_in_gpc_base_v() (0x00004000U) +#define proj_tpc_in_gpc_stride_v() (0x00000800U) +#define proj_tpc_in_gpc_shared_base_v() (0x00001800U) +#define proj_host_num_engines_v() (0x00000002U) +#define proj_host_num_pbdma_v() (0x00000001U) +#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000002U) +#define proj_scal_litter_num_sm_per_tpc_v() (0x00000001U) +#define proj_scal_litter_num_fbps_v() (0x00000001U) +#define proj_scal_litter_num_fbpas_v() (0x00000001U) +#define proj_scal_litter_num_gpcs_v() (0x00000001U) +#define proj_scal_litter_num_pes_per_gpc_v() (0x00000001U) +#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U) +#define proj_scal_litter_num_zcull_banks_v() (0x00000004U) +#define proj_scal_max_gpcs_v() (0x00000020U) +#define proj_scal_max_tpc_per_gpc_v() (0x00000008U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h index 83378b3d7..98e5ae806 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,848 +59,237 @@ #include #include -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_host_error_r(void) -{ - return 0x0010a990U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} +#define pwr_falcon_irqsset_r() (0x0010a000U) +#define pwr_falcon_irqsset_swgen0_set_f() (0x40U) +#define pwr_falcon_irqsclr_r() (0x0010a004U) +#define pwr_falcon_irqstat_r() (0x0010a008U) +#define pwr_falcon_irqstat_halt_true_f() (0x10U) +#define pwr_falcon_irqstat_exterr_true_f() (0x20U) +#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) +#define pwr_falcon_irqmode_r() (0x0010a00cU) +#define pwr_falcon_irqmset_r() (0x0010a010U) +#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_r() (0x0010a014U) +#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmask_r() (0x0010a018U) +#define pwr_falcon_irqdest_r() (0x0010a01cU) +#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pwr_falcon_curctx_r() (0x0010a050U) +#define pwr_falcon_nxtctx_r() (0x0010a054U) +#define pwr_falcon_mailbox0_r() (0x0010a040U) +#define pwr_falcon_mailbox1_r() (0x0010a044U) +#define pwr_falcon_itfen_r() (0x0010a048U) +#define pwr_falcon_itfen_ctxen_enable_f() (0x1U) +#define pwr_falcon_idlestate_r() (0x0010a04cU) +#define pwr_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pwr_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pwr_falcon_os_r() (0x0010a080U) +#define pwr_falcon_engctl_r() (0x0010a0a4U) +#define pwr_falcon_cpuctl_r() (0x0010a100U) +#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) +#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) +#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) +#define pwr_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_sctl_r() (0x0010a240U) +#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pwr_falcon_bootvec_r() (0x0010a104U) +#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_falcon_dmactl_r() (0x0010a10cU) +#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pwr_falcon_hwcfg_r() (0x0010a108U) +#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pwr_falcon_dmatrfbase_r() (0x0010a110U) +#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) +#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) +#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) +#define pwr_falcon_exterraddr_r() (0x0010a168U) +#define pwr_falcon_exterrstat_r() (0x0010a16cU) +#define pwr_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pwr_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) +#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) +#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) +#define pwr_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_new_instblk_r() (0x0010a480U) +#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define pwr_pmu_new_instblk_target_fb_f() (0x0U) +#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) +#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) +#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) +#define pwr_pmu_mutex_id_r() (0x0010a488U) +#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) +#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) +#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) +#define pwr_pmu_mutex_r(i)\ + (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mutex__size_1_v() (0x00000010U) +#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) +#define pwr_pmu_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_head__size_1_v() (0x00000004U) +#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) +#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_head_r() (0x0010a4c8U) +#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) +#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_idle_mask_r(i)\ + (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U) +#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) +#define pwr_pmu_idle_count_r(i)\ + (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) +#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_idle_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) +#define pwr_pmu_idle_ctrl_value_busy_f() (0x2U) +#define pwr_pmu_idle_ctrl_value_always_f() (0x3U) +#define pwr_pmu_idle_ctrl_filter_m() (U32(0x1U) << 2U) +#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) +#define pwr_pmu_idle_threshold_r(i)\ + (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_intr_r() (0x0010a9e8U) +#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) +#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) +#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) +#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_intr_clear_v() (0x00000001U) +#define pwr_pmu_idle_mask_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_mask_1_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_ctrl_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_debug_r(i)\ + (nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_debug__size_1_v() (0x00000004U) +#define pwr_pmu_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mailbox__size_1_v() (0x0000000cU) +#define pwr_pmu_bar0_addr_r() (0x0010a7a0U) +#define pwr_pmu_bar0_data_r() (0x0010a7a4U) +#define pwr_pmu_bar0_ctl_r() (0x0010a7acU) +#define pwr_pmu_bar0_timeout_r() (0x0010a7a8U) +#define pwr_pmu_bar0_fecs_error_r() (0x0010a988U) +#define pwr_pmu_bar0_host_error_r() (0x0010a990U) +#define pwr_pmu_bar0_error_status_r() (0x0010a7b0U) +#define pwr_pmu_bar0_error_status_timeout_host_m() (U32(0x1U) << 0U) +#define pwr_pmu_bar0_error_status_timeout_fecs_m() (U32(0x1U) << 1U) +#define pwr_pmu_bar0_error_status_cmd_hwerr_m() (U32(0x1U) << 2U) +#define pwr_pmu_bar0_error_status_err_cmd_m() (U32(0x1U) << 3U) +#define pwr_pmu_bar0_error_status_hosterr_m() (U32(0x1U) << 30U) +#define pwr_pmu_bar0_error_status_fecserr_m() (U32(0x1U) << 31U) +#define pwr_pmu_pg_idlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_ppuidlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_idle_cnt_r(i)\ + (nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_intren_r(i)\ + (nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_target_local_fb_f() (0x0U) +#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pwr_fbif_transcfg_mem_type_s() (1U) +#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pwr_fbif_transcfg_mem_type_physical_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h index 5ccf0a3dd..3f63c4d64 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,408 +59,105 @@ #include #include -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41U; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_v(u32 r) -{ - return (r >> 14U) & 0xfU; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_v(u32 r) -{ - return (r >> 18U) & 0xffU; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} +#define ram_in_ramfc_s() (4096U) +#define ram_in_ramfc_w() (0U) +#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_page_dir_base_target_w() (128U) +#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) +#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) +#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) +#define ram_in_page_dir_base_vol_w() (128U) +#define ram_in_page_dir_base_vol_true_f() (0x4U) +#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) +#define ram_in_big_page_size_m() (U32(0x1U) << 11U) +#define ram_in_big_page_size_w() (128U) +#define ram_in_big_page_size_128kb_f() (0x0U) +#define ram_in_big_page_size_64kb_f() (0x800U) +#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_page_dir_base_lo_w() (128U) +#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_page_dir_base_hi_w() (129U) +#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_adr_limit_lo_w() (130U) +#define ram_in_adr_limit_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_adr_limit_hi_w() (131U) +#define ram_in_engine_cs_w() (132U) +#define ram_in_engine_cs_wfi_v() (0x00000000U) +#define ram_in_engine_cs_wfi_f() (0x0U) +#define ram_in_engine_cs_fg_v() (0x00000001U) +#define ram_in_engine_cs_fg_f() (0x8U) +#define ram_in_gr_cs_w() (132U) +#define ram_in_gr_cs_wfi_f() (0x0U) +#define ram_in_gr_wfi_target_w() (132U) +#define ram_in_gr_wfi_mode_w() (132U) +#define ram_in_gr_wfi_mode_physical_v() (0x00000000U) +#define ram_in_gr_wfi_mode_physical_f() (0x0U) +#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) +#define ram_in_gr_wfi_mode_virtual_f() (0x4U) +#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_gr_wfi_ptr_lo_w() (132U) +#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_gr_wfi_ptr_hi_w() (133U) +#define ram_in_base_shift_v() (0x0000000cU) +#define ram_in_alloc_size_v() (0x00001000U) +#define ram_fc_size_val_v() (0x00000200U) +#define ram_fc_gp_put_w() (0U) +#define ram_fc_userd_w() (2U) +#define ram_fc_userd_hi_w() (3U) +#define ram_fc_signature_w() (4U) +#define ram_fc_gp_get_w() (5U) +#define ram_fc_pb_get_w() (6U) +#define ram_fc_pb_get_hi_w() (7U) +#define ram_fc_pb_top_level_get_w() (8U) +#define ram_fc_pb_top_level_get_hi_w() (9U) +#define ram_fc_acquire_w() (12U) +#define ram_fc_semaphorea_w() (14U) +#define ram_fc_semaphoreb_w() (15U) +#define ram_fc_semaphorec_w() (16U) +#define ram_fc_semaphored_w() (17U) +#define ram_fc_gp_base_w() (18U) +#define ram_fc_gp_base_hi_w() (19U) +#define ram_fc_gp_fetch_w() (20U) +#define ram_fc_pb_fetch_w() (21U) +#define ram_fc_pb_fetch_hi_w() (22U) +#define ram_fc_pb_put_w() (23U) +#define ram_fc_pb_put_hi_w() (24U) +#define ram_fc_pb_header_w() (33U) +#define ram_fc_pb_count_w() (34U) +#define ram_fc_subdevice_w() (37U) +#define ram_fc_formats_w() (39U) +#define ram_fc_syncpointa_w() (41U) +#define ram_fc_syncpointb_w() (42U) +#define ram_fc_target_w() (43U) +#define ram_fc_hce_ctrl_w() (57U) +#define ram_fc_chid_w() (58U) +#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) +#define ram_fc_chid_id_w() (0U) +#define ram_fc_runlist_timeslice_w() (62U) +#define ram_userd_base_shift_v() (0x00000009U) +#define ram_userd_chan_size_v() (0x00000200U) +#define ram_userd_put_w() (16U) +#define ram_userd_get_w() (17U) +#define ram_userd_ref_w() (18U) +#define ram_userd_put_hi_w() (19U) +#define ram_userd_top_level_get_w() (22U) +#define ram_userd_top_level_get_hi_w() (23U) +#define ram_userd_get_hi_w() (24U) +#define ram_userd_gp_get_w() (34U) +#define ram_userd_gp_put_w() (35U) +#define ram_userd_gp_top_level_get_w() (22U) +#define ram_userd_gp_top_level_get_hi_w() (23U) +#define ram_rl_entry_size_v() (0x00000008U) +#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) +#define ram_rl_entry_type_chid_f() (0x0U) +#define ram_rl_entry_type_tsg_f() (0x2000U) +#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) +#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) +#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) +#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) +#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) +#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) +#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h index e76ed396b..69a7ced05 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,300 +59,82 @@ #include #include -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return U32(0x3U) << 4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return U32(0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return U32(0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return U32(0xfU) << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return U32(0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return U32(0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return U32(0x3fU) << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} +#define therm_use_a_r() (0x00020798U) +#define therm_use_a_ext_therm_0_enable_f() (0x1U) +#define therm_use_a_ext_therm_1_enable_f() (0x2U) +#define therm_use_a_ext_therm_2_enable_f() (0x4U) +#define therm_evt_ext_therm_0_r() (0x00020700U) +#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 8U) +#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U) +#define therm_evt_ext_therm_1_r() (0x00020704U) +#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 8U) +#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U) +#define therm_evt_ext_therm_2_r() (0x00020708U) +#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 8U) +#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U) +#define therm_weight_1_r() (0x00020024U) +#define therm_config1_r() (0x00020050U) +#define therm_config2_r() (0x00020130U) +#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) +#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) +#define therm_gate_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) +#define therm_gate_ctrl_eng_clk_run_f() (0x0U) +#define therm_gate_ctrl_eng_clk_auto_f() (0x1U) +#define therm_gate_ctrl_eng_clk_stop_f() (0x2U) +#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) +#define therm_gate_ctrl_blk_clk_run_f() (0x0U) +#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) +#define therm_gate_ctrl_eng_pwr_m() (U32(0x3U) << 4U) +#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U) +#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U) +#define therm_gate_ctrl_eng_pwr_off_f() (0x20U) +#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) +#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) +#define therm_fecs_idle_filter_r() (0x00020288U) +#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_hubmmu_idle_filter_r() (0x0002028cU) +#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_clk_slowdown_r(i)\ + (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) +#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) +#define therm_grad_stepping_table_r(i)\ + (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) +#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) +#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) +#define therm_grad_stepping0_r() (0x000202c0U) +#define therm_grad_stepping0_feature_s() (1U) +#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) +#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) +#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) +#define therm_grad_stepping0_feature_enable_f() (0x1U) +#define therm_grad_stepping1_r() (0x000202c4U) +#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) +#define therm_clk_timing_r(i)\ + (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h index 1d096028c..d13d9ccd2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,72 +59,21 @@ #include #include -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} +#define timer_pri_timeout_r() (0x00009080U) +#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) +#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) +#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) +#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) +#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) +#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) +#define timer_pri_timeout_en_en_disabled_f() (0x0U) +#define timer_pri_timeout_save_0_r() (0x00009084U) +#define timer_pri_timeout_save_0_fecs_tgt_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_save_0_addr_v(r) (((r) >> 2U) & 0x3fffffU) +#define timer_pri_timeout_save_0_write_v(r) (((r) >> 1U) & 0x1U) +#define timer_pri_timeout_save_1_r() (0x00009088U) +#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU) +#define timer_time_0_r() (0x00009400U) +#define timer_time_1_r() (0x00009410U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h index ebaadebae..51b248a16 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,200 +59,54 @@ #include #include -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_device_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_chain_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy0_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_type_enum_copy0_f(void) -{ - return 0x4U; -} -static inline u32 top_device_info_type_enum_copy1_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_type_enum_copy1_f(void) -{ - return 0x8U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_engine_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_runlist_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_intr_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_reset_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0x7ffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x1fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} +#define top_num_gpcs_r() (0x00022430U) +#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_tpc_per_gpc_r() (0x00022434U) +#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbps_r() (0x00022438U) +#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_ltc_per_fbp_r() (0x00022450U) +#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_slices_per_ltc_r() (0x0002245cU) +#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_ltcs_r() (0x00022454U) +#define top_device_info_r(i)\ + (nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U))) +#define top_device_info__size_1_v() (0x00000040U) +#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U) +#define top_device_info_chain_enable_v() (0x00000001U) +#define top_device_info_chain_disable_v() (0x00000000U) +#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU) +#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU) +#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU) +#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU) +#define top_device_info_type_enum_graphics_v() (0x00000000U) +#define top_device_info_type_enum_graphics_f() (0x0U) +#define top_device_info_type_enum_copy0_v() (0x00000001U) +#define top_device_info_type_enum_copy0_f() (0x4U) +#define top_device_info_type_enum_copy1_v() (0x00000002U) +#define top_device_info_type_enum_copy1_f() (0x8U) +#define top_device_info_type_enum_copy2_v() (0x00000003U) +#define top_device_info_type_enum_copy2_f() (0xcU) +#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U) +#define top_device_info_engine_valid_v() (0x00000001U) +#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U) +#define top_device_info_runlist_valid_v() (0x00000001U) +#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U) +#define top_device_info_intr_valid_v() (0x00000001U) +#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_reset_valid_v() (0x00000001U) +#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) +#define top_device_info_entry_not_valid_v() (0x00000000U) +#define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_engine_type_v() (0x00000003U) +#define top_device_info_entry_data_v() (0x00000001U) +#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U) +#define top_device_info_data_type_enum2_v() (0x00000000U) +#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0x7ffU) +#define top_device_info_data_pri_base_align_v() (0x0000000cU) +#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x1fU) +#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_data_fault_id_valid_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h index 07062c32f..63b9f785c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,448 +59,118 @@ #include #include -static inline u32 trim_sys_gpcpll_cfg_r(void) -{ - return 0x00137000U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void) -{ - return 0x4U; -} -static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) -{ - return 0x10U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) -{ - return 0x20000U; -} -static inline u32 trim_sys_gpcpll_coeff_r(void) -{ - return 0x00137004U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 trim_sys_sel_vco_r(void) -{ - return 0x00137100U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_gpc2clk_out_r(void) -{ - return 0x00137250U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) -{ - return 0x3cU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) -{ - return 6U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) -{ - return U32(0x3fU) << 8U; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000U; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 trim_sys_gpcpll_cfg2_r(void) -{ - return 0x0013700cU; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) -{ - return U32(0xffU) << 24U; -} -static inline u32 trim_sys_gpcpll_cfg3_r(void) -{ - return 0x00137018U; -} -static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void) -{ - return U32(0x1ffU) << 0U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r) -{ - return (r >> 24U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_r(void) -{ - return 0x00137010U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void) -{ - return U32(0x7fU) << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r) -{ - return (r >> 0U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v) -{ - return (v & 0x7fU) << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void) -{ - return U32(0x7fU) << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_dvfs1_r(void) -{ - return 0x00137014U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void) -{ - return U32(0x7fU) << 0U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r) -{ - return (r >> 0U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v) -{ - return (v & 0x7fU) << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void) -{ - return U32(0x7fU) << 8U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v) -{ - return (v & 0xfffU) << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void) -{ - return U32(0xfffU) << 16U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 trim_sys_gpcpll_dvfs2_r(void) -{ - return 0x00137020U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) -{ - return 0x0013701cU; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) -{ - return 0x400000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) -{ - return 0x001328a0U; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void) -{ - return 0x00132820U; -} -static inline u32 trim_sys_bypassctrl_r(void) -{ - return 0x00137340U; -} -static inline u32 trim_sys_bypassctrl_gpcpll_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void) -{ - return 0x1U; -} -static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void) -{ - return 0x0U; -} +#define trim_sys_gpcpll_cfg_r() (0x00137000U) +#define trim_sys_gpcpll_cfg_enable_m() (U32(0x1U) << 0U) +#define trim_sys_gpcpll_cfg_enable_v(r) (((r) >> 0U) & 0x1U) +#define trim_sys_gpcpll_cfg_enable_no_f() (0x0U) +#define trim_sys_gpcpll_cfg_enable_yes_f() (0x1U) +#define trim_sys_gpcpll_cfg_iddq_m() (U32(0x1U) << 1U) +#define trim_sys_gpcpll_cfg_iddq_v(r) (((r) >> 1U) & 0x1U) +#define trim_sys_gpcpll_cfg_iddq_power_on_v() (0x00000000U) +#define trim_sys_gpcpll_cfg_sync_mode_m() (U32(0x1U) << 2U) +#define trim_sys_gpcpll_cfg_sync_mode_v(r) (((r) >> 2U) & 0x1U) +#define trim_sys_gpcpll_cfg_sync_mode_enable_f() (0x4U) +#define trim_sys_gpcpll_cfg_sync_mode_disable_f() (0x0U) +#define trim_sys_gpcpll_cfg_enb_lckdet_m() (U32(0x1U) << 4U) +#define trim_sys_gpcpll_cfg_enb_lckdet_power_on_f() (0x0U) +#define trim_sys_gpcpll_cfg_enb_lckdet_power_off_f() (0x10U) +#define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U) +#define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U) +#define trim_sys_gpcpll_coeff_r() (0x00137004U) +#define trim_sys_gpcpll_coeff_mdiv_f(v) (((v)&0xffU) << 0U) +#define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U) +#define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU) +#define trim_sys_gpcpll_coeff_ndiv_f(v) (((v)&0xffU) << 8U) +#define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U) +#define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU) +#define trim_sys_gpcpll_coeff_pldiv_f(v) (((v)&0x3fU) << 16U) +#define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U) +#define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU) +#define trim_sys_sel_vco_r() (0x00137100U) +#define trim_sys_sel_vco_gpc2clk_out_m() (U32(0x1U) << 0U) +#define trim_sys_sel_vco_gpc2clk_out_init_v() (0x00000000U) +#define trim_sys_sel_vco_gpc2clk_out_init_f() (0x0U) +#define trim_sys_sel_vco_gpc2clk_out_bypass_f() (0x0U) +#define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U) +#define trim_sys_gpc2clk_out_r() (0x00137250U) +#define trim_sys_gpc2clk_out_bypdiv_s() (6U) +#define trim_sys_gpc2clk_out_bypdiv_f(v) (((v)&0x3fU) << 0U) +#define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U) +#define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU) +#define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU) +#define trim_sys_gpc2clk_out_vcodiv_s() (6U) +#define trim_sys_gpc2clk_out_vcodiv_f(v) (((v)&0x3fU) << 8U) +#define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U) +#define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU) +#define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U) +#define trim_sys_gpc2clk_out_sdiv14_m() (U32(0x1U) << 31U) +#define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\ + (nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U))) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v) (((v)&0x3fffU) << 0U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U) +#define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U) +#define trim_gpc_clk_cntr_ncgpcclk_cnt_r(i)\ + (nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U))) +#define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU) +#define trim_sys_gpcpll_cfg2_r() (0x0013700cU) +#define trim_sys_gpcpll_cfg2_sdm_din_f(v) (((v)&0xffU) << 0U) +#define trim_sys_gpcpll_cfg2_sdm_din_m() (U32(0xffU) << 0U) +#define trim_sys_gpcpll_cfg2_sdm_din_v(r) (((r) >> 0U) & 0xffU) +#define trim_sys_gpcpll_cfg2_sdm_din_new_f(v) (((v)&0xffU) << 8U) +#define trim_sys_gpcpll_cfg2_sdm_din_new_m() (U32(0xffU) << 8U) +#define trim_sys_gpcpll_cfg2_sdm_din_new_v(r) (((r) >> 8U) & 0xffU) +#define trim_sys_gpcpll_cfg2_pll_stepa_f(v) (((v)&0xffU) << 24U) +#define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U) +#define trim_sys_gpcpll_cfg3_r() (0x00137018U) +#define trim_sys_gpcpll_cfg3_vco_ctrl_f(v) (((v)&0x1ffU) << 0U) +#define trim_sys_gpcpll_cfg3_vco_ctrl_m() (U32(0x1ffU) << 0U) +#define trim_sys_gpcpll_cfg3_pll_stepb_f(v) (((v)&0xffU) << 16U) +#define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U) +#define trim_sys_gpcpll_cfg3_dfs_testout_v(r) (((r) >> 24U) & 0x7fU) +#define trim_sys_gpcpll_dvfs0_r() (0x00137010U) +#define trim_sys_gpcpll_dvfs0_dfs_coeff_f(v) (((v)&0x7fU) << 0U) +#define trim_sys_gpcpll_dvfs0_dfs_coeff_m() (U32(0x7fU) << 0U) +#define trim_sys_gpcpll_dvfs0_dfs_coeff_v(r) (((r) >> 0U) & 0x7fU) +#define trim_sys_gpcpll_dvfs0_dfs_det_max_f(v) (((v)&0x7fU) << 8U) +#define trim_sys_gpcpll_dvfs0_dfs_det_max_m() (U32(0x7fU) << 8U) +#define trim_sys_gpcpll_dvfs0_dfs_det_max_v(r) (((r) >> 8U) & 0x7fU) +#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(v) (((v)&0x3fU) << 16U) +#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_m() (U32(0x3fU) << 16U) +#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(r) (((r) >> 16U) & 0x3fU) +#define trim_sys_gpcpll_dvfs0_mode_m() (U32(0x1U) << 28U) +#define trim_sys_gpcpll_dvfs0_mode_dvfspll_f() (0x0U) +#define trim_sys_gpcpll_dvfs1_r() (0x00137014U) +#define trim_sys_gpcpll_dvfs1_dfs_ext_det_f(v) (((v)&0x7fU) << 0U) +#define trim_sys_gpcpll_dvfs1_dfs_ext_det_m() (U32(0x7fU) << 0U) +#define trim_sys_gpcpll_dvfs1_dfs_ext_det_v(r) (((r) >> 0U) & 0x7fU) +#define trim_sys_gpcpll_dvfs1_dfs_ext_strb_m() (U32(0x1U) << 7U) +#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(v) (((v)&0x7fU) << 8U) +#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_m() (U32(0x7fU) << 8U) +#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(r) (((r) >> 8U) & 0x7fU) +#define trim_sys_gpcpll_dvfs1_dfs_ext_sel_m() (U32(0x1U) << 15U) +#define trim_sys_gpcpll_dvfs1_dfs_ctrl_f(v) (((v)&0xfffU) << 16U) +#define trim_sys_gpcpll_dvfs1_dfs_ctrl_m() (U32(0xfffU) << 16U) +#define trim_sys_gpcpll_dvfs1_dfs_ctrl_v(r) (((r) >> 16U) & 0xfffU) +#define trim_sys_gpcpll_dvfs1_en_sdm_m() (U32(0x1U) << 28U) +#define trim_sys_gpcpll_dvfs1_en_dfs_m() (U32(0x1U) << 29U) +#define trim_sys_gpcpll_dvfs1_en_dfs_cal_m() (U32(0x1U) << 30U) +#define trim_sys_gpcpll_dvfs1_dfs_cal_done_v(r) (((r) >> 31U) & 0x1U) +#define trim_sys_gpcpll_dvfs2_r() (0x00137020U) +#define trim_sys_gpcpll_ndiv_slowdown_r() (0x0013701cU) +#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m() (U32(0x1U) << 22U) +#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f() (0x400000U) +#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f() (0x0U) +#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m() (U32(0x1U) << 31U) +#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f() (0x80000000U) +#define trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f() (0x0U) +#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r() (0x001328a0U) +#define trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(r)\ + (((r) >> 24U) & 0x1U) +#define trim_gpc_bcast_gpcpll_dvfs2_r() (0x00132820U) +#define trim_sys_bypassctrl_r() (0x00137340U) +#define trim_sys_bypassctrl_gpcpll_m() (U32(0x1U) << 0U) +#define trim_sys_bypassctrl_gpcpll_bypassclk_f() (0x1U) +#define trim_sys_bypassctrl_gpcpll_vco_f() (0x0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h index 6d0feeca4..d96ad70f6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,184 +59,49 @@ #include #include -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} +#define bus_bar0_window_r() (0x00001700U) +#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) +#define bus_bar0_window_target_vid_mem_f() (0x0U) +#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) +#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) +#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) +#define bus_bar1_block_r() (0x00001704U) +#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar1_block_target_vid_mem_f() (0x0U) +#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar1_block_mode_virtual_f() (0x80000000U) +#define bus_bar2_block_r() (0x00001714U) +#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar2_block_target_vid_mem_f() (0x0U) +#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar2_block_mode_virtual_f() (0x80000000U) +#define bus_bar1_block_ptr_shift_v() (0x0000000cU) +#define bus_bar2_block_ptr_shift_v() (0x0000000cU) +#define bus_bind_status_r() (0x00001710U) +#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U) +#define bus_bind_status_bar1_pending_empty_f() (0x0U) +#define bus_bind_status_bar1_pending_busy_f() (0x1U) +#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define bus_bind_status_bar1_outstanding_false_f() (0x0U) +#define bus_bind_status_bar1_outstanding_true_f() (0x2U) +#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U) +#define bus_bind_status_bar2_pending_empty_v() (0x00000000U) +#define bus_bind_status_bar2_pending_empty_f() (0x0U) +#define bus_bind_status_bar2_pending_busy_v() (0x00000001U) +#define bus_bind_status_bar2_pending_busy_f() (0x4U) +#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U) +#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U) +#define bus_bind_status_bar2_outstanding_false_f() (0x0U) +#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U) +#define bus_bind_status_bar2_outstanding_true_f() (0x8U) +#define bus_intr_0_r() (0x00001100U) +#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U) +#define bus_intr_en_0_r() (0x00001140U) +#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h index 2c1a51dd7..0860d15d9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,116 +59,34 @@ #include #include -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_in_use_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ccsr_channel_busy_true_v(void) -{ - return 0x00000001U; -} +#define ccsr_channel_inst_r(i)\ + (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel_inst__size_1_v() (0x00001000U) +#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define ccsr_channel_inst_target_vid_mem_f() (0x0U) +#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) +#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) +#define ccsr_channel_inst_bind_false_f() (0x0U) +#define ccsr_channel_inst_bind_true_f() (0x80000000U) +#define ccsr_channel_r(i)\ + (nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel__size_1_v() (0x00001000U) +#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) +#define ccsr_channel_enable_in_use_v() (0x00000001U) +#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) +#define ccsr_channel_enable_set_true_f() (0x400U) +#define ccsr_channel_enable_clr_true_f() (0x800U) +#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) +#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U) +#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U) +#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU) +#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU) +#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU) +#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU) +#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU) +#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) +#define ccsr_channel_next_true_v() (0x00000001U) +#define ccsr_channel_force_ctx_reload_true_f() (0x100U) +#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U) +#define ccsr_channel_busy_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h index e9695e618..a0d7ebf41 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ce_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,12 @@ #include #include -static inline u32 ce_intr_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32(i, 128U)); -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} +#define ce_intr_status_r(i)\ + (nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U))) +#define ce_intr_status_blockpipe_pending_f() (0x1U) +#define ce_intr_status_blockpipe_reset_f() (0x1U) +#define ce_intr_status_nonblockpipe_pending_f() (0x2U) +#define ce_intr_status_nonblockpipe_reset_f() (0x2U) +#define ce_intr_status_launcherr_pending_f() (0x4U) +#define ce_intr_status_launcherr_reset_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h index 8ab9ec4b5..f8d236929 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,248 +59,72 @@ #include #include -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_gpccs_header_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} +#define ctxsw_prog_fecs_header_v() (0x00000100U) +#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) +#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) +#define ctxsw_prog_main_image_patch_count_o() (0x00000010U) +#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U) +#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U) +#define ctxsw_prog_main_image_zcull_o() (0x0000001cU) +#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U) +#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U) +#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U) +#define ctxsw_prog_main_image_pm_o() (0x00000028U) +#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U) +#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U) +#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) +#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) +#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) +#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) +#define ctxsw_prog_main_image_num_wfi_save_ops_o() (0x000000d0U) +#define ctxsw_prog_main_image_num_cta_save_ops_o() (0x000000d4U) +#define ctxsw_prog_main_image_num_gfxp_save_ops_o() (0x000000d8U) +#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU) +#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) +#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) +#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) +#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) +#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) +#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) +#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U) +#define ctxsw_prog_local_magic_value_o() (0x000000fcU) +#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU) +#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU) +#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU) +#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U) +#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\ + (0x00000000U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\ + (0x00000002U) +#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ + (((r) >> 0U) & 0x3U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U) +#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U) +#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U) +#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU) +#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U) +#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) +#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ + (0x1U) +#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) +#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) +#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h index 84677e00a..1d6a28756 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,548 +59,145 @@ #include #include -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} +#define falcon_falcon_irqsset_r() (0x00000000U) +#define falcon_falcon_irqsset_swgen0_set_f() (0x40U) +#define falcon_falcon_irqsclr_r() (0x00000004U) +#define falcon_falcon_irqstat_r() (0x00000008U) +#define falcon_falcon_irqstat_halt_true_f() (0x10U) +#define falcon_falcon_irqstat_exterr_true_f() (0x20U) +#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) +#define falcon_falcon_irqmode_r() (0x0000000cU) +#define falcon_falcon_irqmset_r() (0x00000010U) +#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_r() (0x00000014U) +#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqmask_r() (0x00000018U) +#define falcon_falcon_irqdest_r() (0x0000001cU) +#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define falcon_falcon_curctx_r() (0x00000050U) +#define falcon_falcon_nxtctx_r() (0x00000054U) +#define falcon_falcon_mailbox0_r() (0x00000040U) +#define falcon_falcon_mailbox1_r() (0x00000044U) +#define falcon_falcon_itfen_r() (0x00000048U) +#define falcon_falcon_itfen_ctxen_enable_f() (0x1U) +#define falcon_falcon_idlestate_r() (0x0000004cU) +#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define falcon_falcon_os_r() (0x00000080U) +#define falcon_falcon_engctl_r() (0x000000a4U) +#define falcon_falcon_cpuctl_r() (0x00000100U) +#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define falcon_falcon_cpuctl_alias_r() (0x00000130U) +#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) +#define falcon_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_sctl_r() (0x00000240U) +#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define falcon_falcon_bootvec_r() (0x00000104U) +#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define falcon_falcon_dmactl_r() (0x0000010cU) +#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_hwcfg_r() (0x00000108U) +#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define falcon_falcon_dmatrfbase_r() (0x00000110U) +#define falcon_falcon_dmatrfbase1_r() (0x00000128U) +#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) +#define falcon_falcon_dmatrfcmd_r() (0x00000118U) +#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) +#define falcon_falcon_imctl_debug_r() (0x0000015cU) +#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) +#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) +#define falcon_falcon_imstat_r() (0x00000144U) +#define falcon_falcon_traceidx_r() (0x00000148U) +#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) +#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) +#define falcon_falcon_tracepc_r() (0x0000014cU) +#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) +#define falcon_falcon_exterraddr_r() (0x0010a168U) +#define falcon_falcon_exterrstat_r() (0x0010a16cU) +#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) +#define falcon_falcon_icd_cmd_r() (0x00000200U) +#define falcon_falcon_icd_cmd_opc_s() (4U) +#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define falcon_falcon_icd_rdata_r() (0x0000020cU) +#define falcon_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define falcon_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_debug1_r() (0x00000090U) +#define falcon_falcon_debug1_ctxsw_mode_s() (1U) +#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define falcon_falcon_debuginfo_r() (0x00000094U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h index d0bd764b1..3181f025e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,508 +59,130 @@ #include #include -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) -{ - return 0x18U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return U32(0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return U32(0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return U32(0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return U32(0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_priv_level_mask_r(void) -{ - return 0x00100cdcU; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_mmu_local_memory_range_r(void) -{ - return 0x00100ce0U; -} -static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) -{ - return (r >> 4U) & 0x3fU; -} -static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_fbpa_fbio_delay_r(void) -{ - return 0x009a065cU; -} -static inline u32 fb_fbpa_fbio_delay_src_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_fbpa_fbio_delay_src_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 fb_fbpa_fbio_delay_src_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_delay_src_max_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_fbpa_fbio_delay_priv_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_delay_priv_max_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_r(void) -{ - return 0x009a08e0U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_scrub_status_r(void) -{ - return 0x00100b20U; -} -static inline u32 fb_niso_scrub_status_flag_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_fbpa_fbio_iref_byte_rx_ctrl_r(void) -{ - return 0x009a0eb0U; -} +#define fb_fbhub_num_active_ltcs_r() (0x00100800U) +#define fb_mmu_ctrl_r() (0x00100c80U) +#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) +#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) +#define fb_priv_mmu_phy_secure_r() (0x00100ce4U) +#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) +#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) +#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_invalidate_r() (0x00100cbcU) +#define fb_mmu_invalidate_all_va_true_f() (0x1U) +#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) +#define fb_mmu_invalidate_hubtlb_only_s() (1U) +#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) +#define fb_mmu_invalidate_replay_s() (3U) +#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) +#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) +#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) +#define fb_mmu_invalidate_replay_none_f() (0x0U) +#define fb_mmu_invalidate_replay_start_f() (0x8U) +#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U) +#define fb_mmu_invalidate_replay_cancel_targeted_f() (0x18U) +#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) +#define fb_mmu_invalidate_replay_cancel_f() (0x20U) +#define fb_mmu_invalidate_sys_membar_s() (1U) +#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) +#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) +#define fb_mmu_invalidate_ack_s() (2U) +#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) +#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) +#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) +#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) +#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) +#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) +#define fb_mmu_invalidate_cancel_client_id_s() (6U) +#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) +#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) +#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) +#define fb_mmu_invalidate_cancel_client_type_s() (1U) +#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) +#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) +#define fb_mmu_invalidate_cancel_cache_level_s() (3U) +#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) +#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) +#define fb_mmu_invalidate_cancel_cache_level_pte_only_f() (0x1000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f() (0x2000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f() (0x3000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f() (0x4000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f() (0x5000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) +#define fb_mmu_invalidate_trigger_s() (1U) +#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) +#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) +#define fb_mmu_debug_wr_r() (0x00100cc8U) +#define fb_mmu_debug_wr_aperture_s() (2U) +#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_wr_vol_false_f() (0x0U) +#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) +#define fb_mmu_debug_wr_vol_true_f() (0x4U) +#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_rd_r() (0x00100cccU) +#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_rd_vol_false_f() (0x0U) +#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_ctrl_r() (0x00100cc4U) +#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_enabled_f() (0x10000U) +#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U) +#define fb_mmu_priv_level_mask_r() (0x00100cdcU) +#define fb_mmu_priv_level_mask_write_violation_m() (U32(0x1U) << 7U) +#define fb_niso_flush_sysmem_addr_r() (0x00100c10U) +#define fb_mmu_local_memory_range_r() (0x00100ce0U) +#define fb_mmu_local_memory_range_lower_scale_v(r) (((r) >> 0U) & 0xfU) +#define fb_mmu_local_memory_range_lower_mag_v(r) (((r) >> 4U) & 0x3fU) +#define fb_mmu_local_memory_range_ecc_mode_v(r) (((r) >> 30U) & 0x1U) +#define fb_fbpa_fbio_delay_r() (0x009a065cU) +#define fb_fbpa_fbio_delay_src_f(v) (((v)&0xfU) << 0U) +#define fb_fbpa_fbio_delay_src_m() (U32(0xfU) << 0U) +#define fb_fbpa_fbio_delay_src_v(r) (((r) >> 0U) & 0xfU) +#define fb_fbpa_fbio_delay_src_max_v() (0x00000002U) +#define fb_fbpa_fbio_delay_priv_f(v) (((v)&0xfU) << 4U) +#define fb_fbpa_fbio_delay_priv_m() (U32(0xfU) << 4U) +#define fb_fbpa_fbio_delay_priv_v(r) (((r) >> 4U) & 0xfU) +#define fb_fbpa_fbio_delay_priv_max_v() (0x00000002U) +#define fb_fbpa_fbio_cmd_delay_r() (0x009a08e0U) +#define fb_fbpa_fbio_cmd_delay_cmd_src_f(v) (((v)&0xfU) << 0U) +#define fb_fbpa_fbio_cmd_delay_cmd_src_m() (U32(0xfU) << 0U) +#define fb_fbpa_fbio_cmd_delay_cmd_src_v(r) (((r) >> 0U) & 0xfU) +#define fb_fbpa_fbio_cmd_delay_cmd_src_max_v() (0x00000001U) +#define fb_fbpa_fbio_cmd_delay_cmd_priv_f(v) (((v)&0xfU) << 4U) +#define fb_fbpa_fbio_cmd_delay_cmd_priv_m() (U32(0xfU) << 4U) +#define fb_fbpa_fbio_cmd_delay_cmd_priv_v(r) (((r) >> 4U) & 0xfU) +#define fb_fbpa_fbio_cmd_delay_cmd_priv_max_v() (0x00000001U) +#define fb_niso_scrub_status_r() (0x00100b20U) +#define fb_niso_scrub_status_flag_v(r) (((r) >> 0U) & 0x1U) +#define fb_fbpa_fbio_iref_byte_rx_ctrl_r() (0x009a0eb0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h index 71b5735b2..7a00092e8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fbpa_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,12 +59,6 @@ #include #include -static inline u32 fbpa_cstatus_r(void) -{ - return 0x009a020cU; -} -static inline u32 fbpa_cstatus_ramamount_v(u32 r) -{ - return (r >> 0U) & 0x1ffffU; -} +#define fbpa_cstatus_r() (0x009a020cU) +#define fbpa_cstatus_ramamount_v(r) (((r) >> 0U) & 0x1ffffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h index 59c332b4c..e36f516de 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,648 +59,184 @@ #include #include -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return U32(0x3fffffffU) << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000009U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_r(void) -{ - return 0x00002a70U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_hi_r(void) -{ - return 0x00002a74U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_size_r(void) -{ - return 0x00002a78U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) -{ - return 0x00001200U; -} -static inline u32 fifo_replay_fault_buffer_get_r(void) -{ - return 0x00002a7cU; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_put_r(void) -{ - return 0x00002a80U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) -{ - return (v & 0x3fffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_r(void) -{ - return 0x00002a84U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) -{ - return 0x00000001U; -} +#define fifo_bar1_base_r() (0x00002254U) +#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) +#define fifo_bar1_base_valid_false_f() (0x0U) +#define fifo_bar1_base_valid_true_f() (0x10000000U) +#define fifo_runlist_base_r() (0x00002270U) +#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_runlist_base_target_vid_mem_f() (0x0U) +#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) +#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) +#define fifo_runlist_r() (0x00002274U) +#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) +#define fifo_eng_runlist_base_r(i)\ + (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist_base__size_1_v() (0x00000007U) +#define fifo_eng_runlist_r(i)\ + (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist__size_1_v() (0x00000007U) +#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) +#define fifo_eng_runlist_length_max_v() (0x0000ffffU) +#define fifo_eng_runlist_pending_true_f() (0x100000U) +#define fifo_pb_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pb_timeslice_timeout_16_f() (0x10U) +#define fifo_pb_timeslice_timescale_0_f() (0x0U) +#define fifo_pb_timeslice_enable_true_f() (0x10000000U) +#define fifo_pbdma_map_r(i)\ + (nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_0_r() (0x00002100U) +#define fifo_intr_0_bind_error_pending_f() (0x1U) +#define fifo_intr_0_bind_error_reset_f() (0x1U) +#define fifo_intr_0_sched_error_pending_f() (0x100U) +#define fifo_intr_0_sched_error_reset_f() (0x100U) +#define fifo_intr_0_chsw_error_pending_f() (0x10000U) +#define fifo_intr_0_chsw_error_reset_f() (0x10000U) +#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U) +#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U) +#define fifo_intr_0_lb_error_pending_f() (0x1000000U) +#define fifo_intr_0_lb_error_reset_f() (0x1000000U) +#define fifo_intr_0_replayable_fault_error_pending_f() (0x2000000U) +#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U) +#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U) +#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U) +#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U) +#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) +#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) +#define fifo_intr_en_0_r() (0x00002140U) +#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) +#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) +#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) +#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) +#define fifo_intr_en_1_r() (0x00002528U) +#define fifo_intr_bind_error_r() (0x0000252cU) +#define fifo_intr_sched_error_r() (0x0000254cU) +#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) +#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) +#define fifo_intr_chsw_error_r() (0x0000256cU) +#define fifo_intr_mmu_fault_id_r() (0x0000259cU) +#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U) +#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U) +#define fifo_intr_mmu_fault_inst_r(i)\ + (nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU) +#define fifo_intr_mmu_fault_lo_r(i)\ + (nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_hi_r(i)\ + (nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_r(i)\ + (nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0x1fU) +#define fifo_intr_mmu_fault_info_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fifo_intr_mmu_fault_info_client_type_gpc_v() (0x00000000U) +#define fifo_intr_mmu_fault_info_client_type_hub_v() (0x00000001U) +#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU) +#define fifo_intr_pbdma_id_r() (0x000025a0U) +#define fifo_intr_pbdma_id_status_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_pbdma_id_status_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_pbdma_id_status__size_1_v() (0x00000004U) +#define fifo_intr_runlist_r() (0x00002a00U) +#define fifo_fb_timeout_r() (0x00002a04U) +#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U) +#define fifo_fb_timeout_period_max_f() (0x3fffffffU) +#define fifo_error_sched_disable_r() (0x0000262cU) +#define fifo_sched_disable_r() (0x00002630U) +#define fifo_sched_disable_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_sched_disable_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_sched_disable_true_v() (0x00000001U) +#define fifo_preempt_r() (0x00002634U) +#define fifo_preempt_pending_true_f() (0x100000U) +#define fifo_preempt_type_channel_f() (0x0U) +#define fifo_preempt_type_tsg_f() (0x1000000U) +#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) +#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) +#define fifo_trigger_mmu_fault_r(i)\ + (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) +#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) +#define fifo_engine_status_r(i)\ + (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_engine_status__size_1_v() (0x00000009U) +#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_engine_status_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U) +#define fifo_engine_status_ctx_status_valid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U) +#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U) +#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U) +#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_engine_status_next_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U) +#define fifo_engine_status_faulted_true_v() (0x00000001U) +#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U) +#define fifo_engine_status_engine_idle_v() (0x00000000U) +#define fifo_engine_status_engine_busy_v() (0x00000001U) +#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U) +#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U) +#define fifo_pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pbdma_status__size_1_v() (0x00000004U) +#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_pbdma_status_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U) +#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U) +#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U) +#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U) +#define fifo_replay_fault_buffer_lo_r() (0x00002a70U) +#define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U) +#define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U) +#define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U) +#define fifo_replay_fault_buffer_lo_base_f(v) (((v)&0xfffffU) << 12U) +#define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U) +#define fifo_replay_fault_buffer_hi_r() (0x00002a74U) +#define fifo_replay_fault_buffer_hi_base_f(v) (((v)&0xffU) << 0U) +#define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U) +#define fifo_replay_fault_buffer_size_r() (0x00002a78U) +#define fifo_replay_fault_buffer_size_hw_f(v) (((v)&0x3fffU) << 0U) +#define fifo_replay_fault_buffer_size_hw_entries_v() (0x00001200U) +#define fifo_replay_fault_buffer_get_r() (0x00002a7cU) +#define fifo_replay_fault_buffer_get_offset_hw_f(v) (((v)&0x3fffU) << 0U) +#define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U) +#define fifo_replay_fault_buffer_put_r() (0x00002a80U) +#define fifo_replay_fault_buffer_put_offset_hw_f(v) (((v)&0x3fffU) << 0U) +#define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U) +#define fifo_replay_fault_buffer_info_r() (0x00002a84U) +#define fifo_replay_fault_buffer_info_overflow_f(v) (((v)&0x1U) << 0U) +#define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U) +#define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_write_nack_f(v) (((v)&0x1U) << 24U) +#define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U) +#define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\ + (((v)&0x1U) << 28U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\ + (0x00000000U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\ + (0x00000001U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v()\ + (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h index 1bd1ebae7..a0f2638d9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_flush_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,132 +59,36 @@ #include #include -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} +#define flush_l2_system_invalidate_r() (0x00070004U) +#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U) +#define flush_l2_system_invalidate_pending_busy_f() (0x1U) +#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U) +#define flush_l2_flush_dirty_r() (0x00070010U) +#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U) +#define flush_l2_flush_dirty_pending_empty_f() (0x0U) +#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U) +#define flush_l2_flush_dirty_pending_busy_f() (0x1U) +#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U) +#define flush_l2_flush_dirty_outstanding_false_f() (0x0U) +#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U) +#define flush_l2_clean_comptags_r() (0x0007000cU) +#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U) +#define flush_l2_clean_comptags_pending_empty_f() (0x0U) +#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U) +#define flush_l2_clean_comptags_pending_busy_f() (0x1U) +#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U) +#define flush_l2_clean_comptags_outstanding_false_f() (0x0U) +#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U) +#define flush_fb_flush_r() (0x00070000U) +#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_fb_flush_pending_busy_v() (0x00000001U) +#define flush_fb_flush_pending_busy_f() (0x1U) +#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_fb_flush_outstanding_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h index 2a2a1bbff..53ffb07a1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,220 +59,62 @@ #include #include -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_vin_cal_fuse_rev_r(void) -{ - return 0x0002164cU; -} -static inline u32 fuse_vin_cal_fuse_rev_data_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fuse_vin_cal_gpc0_r(void) -{ - return 0x00021650U; -} -static inline u32 fuse_vin_cal_gpc0_icpt_int_data_s(void) -{ - return 12U; -} -static inline u32 fuse_vin_cal_gpc0_icpt_int_data_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_s(void) -{ - return 2U; -} -static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_v(u32 r) -{ - return (r >> 14U) & 0x3U; -} -static inline u32 fuse_vin_cal_gpc0_slope_int_data_s(void) -{ - return 4U; -} -static inline u32 fuse_vin_cal_gpc0_slope_int_data_v(u32 r) -{ - return (r >> 10U) & 0xfU; -} -static inline u32 fuse_vin_cal_gpc0_slope_frac_data_s(void) -{ - return 10U; -} -static inline u32 fuse_vin_cal_gpc0_slope_frac_data_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 fuse_vin_cal_gpc1_delta_r(void) -{ - return 0x00021654U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_s(void) -{ - return 8U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_v(u32 r) -{ - return (r >> 14U) & 0xffU; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_s(void) -{ - return 2U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(u32 r) -{ - return (r >> 12U) & 0x3U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_s(void) -{ - return 10U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 fuse_vin_cal_gpc2_delta_r(void) -{ - return 0x00021658U; -} -static inline u32 fuse_vin_cal_gpc3_delta_r(void) -{ - return 0x0002165cU; -} -static inline u32 fuse_vin_cal_gpc4_delta_r(void) -{ - return 0x00021660U; -} -static inline u32 fuse_vin_cal_gpc5_delta_r(void) -{ - return 0x00021664U; -} -static inline u32 fuse_vin_cal_shared_delta_r(void) -{ - return 0x00021668U; -} -static inline u32 fuse_vin_cal_sram_delta_r(void) -{ - return 0x0002166cU; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_s(void) -{ - return 9U; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_v(u32 r) -{ - return (r >> 13U) & 0x1ffU; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_s(void) -{ - return 1U; -} -static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} +#define fuse_status_opt_gpc_r() (0x00021c1cU) +#define fuse_status_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) +#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0x3U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U) +#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) +#define fuse_status_opt_fbio_r() (0x00021c14U) +#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) +#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) +#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) +#define fuse_status_opt_rop_l2_fbp_r(i)\ + (nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_status_opt_fbp_r() (0x00021d38U) +#define fuse_status_opt_fbp_idx_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fuse_vin_cal_fuse_rev_r() (0x0002164cU) +#define fuse_vin_cal_fuse_rev_data_v(r) (((r) >> 0U) & 0x3U) +#define fuse_vin_cal_gpc0_r() (0x00021650U) +#define fuse_vin_cal_gpc0_icpt_int_data_s() (12U) +#define fuse_vin_cal_gpc0_icpt_int_data_v(r) (((r) >> 16U) & 0xfffU) +#define fuse_vin_cal_gpc0_icpt_frac_data_s() (2U) +#define fuse_vin_cal_gpc0_icpt_frac_data_v(r) (((r) >> 14U) & 0x3U) +#define fuse_vin_cal_gpc0_slope_int_data_s() (4U) +#define fuse_vin_cal_gpc0_slope_int_data_v(r) (((r) >> 10U) & 0xfU) +#define fuse_vin_cal_gpc0_slope_frac_data_s() (10U) +#define fuse_vin_cal_gpc0_slope_frac_data_v(r) (((r) >> 0U) & 0x3ffU) +#define fuse_vin_cal_gpc1_delta_r() (0x00021654U) +#define fuse_vin_cal_gpc1_delta_icpt_int_data_s() (8U) +#define fuse_vin_cal_gpc1_delta_icpt_int_data_v(r) (((r) >> 14U) & 0xffU) +#define fuse_vin_cal_gpc1_delta_icpt_frac_data_s() (2U) +#define fuse_vin_cal_gpc1_delta_icpt_frac_data_v(r) (((r) >> 12U) & 0x3U) +#define fuse_vin_cal_gpc1_delta_icpt_sign_data_s() (1U) +#define fuse_vin_cal_gpc1_delta_icpt_sign_data_v(r) (((r) >> 22U) & 0x1U) +#define fuse_vin_cal_gpc1_delta_slope_int_data_s() (1U) +#define fuse_vin_cal_gpc1_delta_slope_int_data_v(r) (((r) >> 10U) & 0x1U) +#define fuse_vin_cal_gpc1_delta_slope_frac_data_s() (10U) +#define fuse_vin_cal_gpc1_delta_slope_frac_data_v(r) (((r) >> 0U) & 0x3ffU) +#define fuse_vin_cal_gpc1_delta_slope_sign_data_s() (1U) +#define fuse_vin_cal_gpc1_delta_slope_sign_data_v(r) (((r) >> 11U) & 0x1U) +#define fuse_vin_cal_gpc2_delta_r() (0x00021658U) +#define fuse_vin_cal_gpc3_delta_r() (0x0002165cU) +#define fuse_vin_cal_gpc4_delta_r() (0x00021660U) +#define fuse_vin_cal_gpc5_delta_r() (0x00021664U) +#define fuse_vin_cal_shared_delta_r() (0x00021668U) +#define fuse_vin_cal_sram_delta_r() (0x0002166cU) +#define fuse_vin_cal_sram_delta_icpt_int_data_s() (9U) +#define fuse_vin_cal_sram_delta_icpt_int_data_v(r) (((r) >> 13U) & 0x1ffU) +#define fuse_vin_cal_sram_delta_icpt_frac_data_s() (1U) +#define fuse_vin_cal_sram_delta_icpt_frac_data_v(r) (((r) >> 12U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h index bbace3b2a..8a57b5b56 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,276 +59,72 @@ #include #include -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} +#define gmmu_new_pde_is_pte_w() (0U) +#define gmmu_new_pde_is_pte_false_f() (0x0U) +#define gmmu_new_pde_aperture_w() (0U) +#define gmmu_new_pde_aperture_invalid_f() (0x0U) +#define gmmu_new_pde_aperture_video_memory_f() (0x2U) +#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pde_address_sys_w() (0U) +#define gmmu_new_pde_vol_w() (0U) +#define gmmu_new_pde_vol_true_f() (0x8U) +#define gmmu_new_pde_vol_false_f() (0x0U) +#define gmmu_new_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_pde__size_v() (0x00000008U) +#define gmmu_new_dual_pde_is_pte_w() (0U) +#define gmmu_new_dual_pde_is_pte_false_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_w() (0U) +#define gmmu_new_dual_pde_aperture_big_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_new_dual_pde_address_big_sys_w() (0U) +#define gmmu_new_dual_pde_aperture_small_w() (2U) +#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_small_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_vol_small_w() (2U) +#define gmmu_new_dual_pde_vol_small_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_small_false_f() (0x0U) +#define gmmu_new_dual_pde_vol_big_w() (0U) +#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) +#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_dual_pde_address_small_sys_w() (2U) +#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) +#define gmmu_new_dual_pde__size_v() (0x00000010U) +#define gmmu_new_pte__size_v() (0x00000008U) +#define gmmu_new_pte_valid_w() (0U) +#define gmmu_new_pte_valid_true_f() (0x1U) +#define gmmu_new_pte_valid_false_f() (0x0U) +#define gmmu_new_pte_privilege_w() (0U) +#define gmmu_new_pte_privilege_true_f() (0x20U) +#define gmmu_new_pte_privilege_false_f() (0x0U) +#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_sys_w() (0U) +#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_vid_w() (0U) +#define gmmu_new_pte_vol_w() (0U) +#define gmmu_new_pte_vol_true_f() (0x8U) +#define gmmu_new_pte_vol_false_f() (0x0U) +#define gmmu_new_pte_aperture_w() (0U) +#define gmmu_new_pte_aperture_video_memory_f() (0x0U) +#define gmmu_new_pte_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pte_read_only_w() (0U) +#define gmmu_new_pte_read_only_true_f() (0x40U) +#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U) +#define gmmu_new_pte_comptagline_w() (1U) +#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) +#define gmmu_new_pte_kind_w() (1U) +#define gmmu_new_pte_address_shift_v() (0x0000000cU) +#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) +#define gmmu_pte_kind_w() (1U) +#define gmmu_pte_kind_invalid_v() (0x000000ffU) +#define gmmu_pte_kind_pitch_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h index ff48085e7..dd40709b9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,4116 +59,1113 @@ #include #include -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x005046b8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) -{ - return 0x80U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) -{ - return 0x005044a0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) -{ - return 0x005046bcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) -{ - return 0x005046c0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) -{ - return 0x005044a4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(void) -{ - return 0x004041c4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_irqsset_r(void) -{ - return 0x00409000U; -} -static inline u32 gr_fecs_irqsclr_r(void) -{ - return 0x00409004U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_irqsset_r(void) -{ - return 0x0041a000U; -} -static inline u32 gr_gpcs_gpccs_irqsclr_r(void) -{ - return 0x0041a004U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return U32(0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000900U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000900U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return U32(0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000320U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00000ba8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000320U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419b00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419b04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return U32(0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return U32(0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000de0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00500100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0050014cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return U32(0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00504644U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return U32(0x3U) << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return U32(0x3U) << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419c84U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return U32(0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419f78U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return U32(0x3U) << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return U32(0x1ffU) << 0U; -} +#define gr_intr_r() (0x00400100U) +#define gr_intr_notify_pending_f() (0x1U) +#define gr_intr_notify_reset_f() (0x1U) +#define gr_intr_semaphore_pending_f() (0x2U) +#define gr_intr_semaphore_reset_f() (0x2U) +#define gr_intr_illegal_method_pending_f() (0x10U) +#define gr_intr_illegal_method_reset_f() (0x10U) +#define gr_intr_illegal_notify_pending_f() (0x40U) +#define gr_intr_illegal_notify_reset_f() (0x40U) +#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) +#define gr_intr_firmware_method_pending_f() (0x100U) +#define gr_intr_firmware_method_reset_f() (0x100U) +#define gr_intr_illegal_class_pending_f() (0x20U) +#define gr_intr_illegal_class_reset_f() (0x20U) +#define gr_intr_fecs_error_pending_f() (0x80000U) +#define gr_intr_fecs_error_reset_f() (0x80000U) +#define gr_intr_class_error_pending_f() (0x100000U) +#define gr_intr_class_error_reset_f() (0x100000U) +#define gr_intr_exception_pending_f() (0x200000U) +#define gr_intr_exception_reset_f() (0x200000U) +#define gr_fecs_intr_r() (0x00400144U) +#define gr_class_error_r() (0x00400110U) +#define gr_class_error_code_v(r) (((r) >> 0U) & 0xffffU) +#define gr_intr_nonstall_r() (0x00400120U) +#define gr_intr_nonstall_trap_pending_f() (0x2U) +#define gr_intr_en_r() (0x0040013cU) +#define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception1_r() (0x00400118U) +#define gr_exception1_gpc_0_pending_f() (0x1U) +#define gr_exception2_r() (0x0040011cU) +#define gr_exception_en_r() (0x00400138U) +#define gr_exception_en_fe_m() (U32(0x1U) << 0U) +#define gr_exception1_en_r() (0x00400130U) +#define gr_exception2_en_r() (0x00400134U) +#define gr_gpfifo_ctl_r() (0x00400500U) +#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) +#define gr_gpfifo_ctl_access_disabled_f() (0x0U) +#define gr_gpfifo_ctl_access_enabled_f() (0x1U) +#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) +#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) +#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) +#define gr_gpfifo_status_r() (0x00400504U) +#define gr_trapped_addr_r() (0x00400704U) +#define gr_trapped_addr_mthd_v(r) (((r) >> 2U) & 0xfffU) +#define gr_trapped_addr_subch_v(r) (((r) >> 16U) & 0x7U) +#define gr_trapped_addr_mme_generated_v(r) (((r) >> 20U) & 0x1U) +#define gr_trapped_addr_datahigh_v(r) (((r) >> 24U) & 0x1U) +#define gr_trapped_addr_priv_v(r) (((r) >> 28U) & 0x1U) +#define gr_trapped_addr_status_v(r) (((r) >> 31U) & 0x1U) +#define gr_trapped_data_lo_r() (0x00400708U) +#define gr_trapped_data_hi_r() (0x0040070cU) +#define gr_trapped_data_mme_r() (0x00400710U) +#define gr_trapped_data_mme_pc_v(r) (((r) >> 0U) & 0xfffU) +#define gr_status_r() (0x00400700U) +#define gr_status_fe_method_upper_v(r) (((r) >> 1U) & 0x1U) +#define gr_status_fe_method_lower_v(r) (((r) >> 2U) & 0x1U) +#define gr_status_fe_method_lower_idle_v() (0x00000000U) +#define gr_status_fe_gi_v(r) (((r) >> 21U) & 0x1U) +#define gr_status_mask_r() (0x00400610U) +#define gr_status_1_r() (0x00400604U) +#define gr_status_2_r() (0x00400608U) +#define gr_engine_status_r() (0x0040060cU) +#define gr_engine_status_value_busy_f() (0x1U) +#define gr_pri_be0_becs_be_exception_r() (0x00410204U) +#define gr_pri_be0_becs_be_exception_en_r() (0x00410208U) +#define gr_pri_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_pri_gpc0_gpccs_gpc_exception_en_r() (0x00502c94U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_activity_0_r() (0x00400380U) +#define gr_activity_1_r() (0x00400384U) +#define gr_activity_2_r() (0x00400388U) +#define gr_activity_4_r() (0x00400390U) +#define gr_activity_4_gpc0_s() (3U) +#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) +#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) +#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) +#define gr_activity_4_gpc0_empty_v() (0x00000000U) +#define gr_activity_4_gpc0_preempted_v() (0x00000004U) +#define gr_pri_gpc0_gcc_dbg_r() (0x00501000U) +#define gr_pri_gpcs_gcc_dbg_r() (0x00419000U) +#define gr_pri_gpcs_gcc_dbg_invalidate_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cache_control_r() (0x005046a4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_r() (0x00419ea4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m() (U32(0x1U) << 0U) +#define gr_pri_sked_activity_r() (0x00407054U) +#define gr_pri_gpc0_gpccs_gpc_activity0_r() (0x00502c80U) +#define gr_pri_gpc0_gpccs_gpc_activity1_r() (0x00502c84U) +#define gr_pri_gpc0_gpccs_gpc_activity2_r() (0x00502c88U) +#define gr_pri_gpc0_gpccs_gpc_activity3_r() (0x00502c8cU) +#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() (0x00504500U) +#define gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r() (0x00504d00U) +#define gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r() (0x00501d00U) +#define gr_pri_gpcs_gpccs_gpc_activity_0_r() (0x0041ac80U) +#define gr_pri_gpcs_gpccs_gpc_activity_1_r() (0x0041ac84U) +#define gr_pri_gpcs_gpccs_gpc_activity_2_r() (0x0041ac88U) +#define gr_pri_gpcs_gpccs_gpc_activity_3_r() (0x0041ac8cU) +#define gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r() (0x0041c500U) +#define gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r() (0x0041cd00U) +#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r() (0x00419d00U) +#define gr_pri_be0_becs_be_activity0_r() (0x00410200U) +#define gr_pri_be1_becs_be_activity0_r() (0x00410600U) +#define gr_pri_bes_becs_be_activity0_r() (0x00408a00U) +#define gr_pri_ds_mpipe_status_r() (0x00405858U) +#define gr_pri_fe_go_idle_info_r() (0x00404194U) +#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r() (0x00504238U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() (0x005046b8U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()\ + (0x10U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()\ + (0x20U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()\ + (0x40U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()\ + (0x80U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()\ + (0x100U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()\ + (0x200U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()\ + (0x400U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()\ + (0x800U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() (0x005044a0U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()\ + (0x1U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()\ + (0x2U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()\ + (0x10U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()\ + (0x20U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()\ + (0x100U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()\ + (0x200U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() (0x005046bcU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() (0x005046c0U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() (0x005044a4U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m()\ + (U32(0xffU) << 0U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(r)\ + (((r) >> 0U) & 0xffU) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()\ + (U32(0xffU) << 8U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(r)\ + (((r) >> 8U) & 0xffU) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()\ + (U32(0xffU) << 16U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(r)\ + (((r) >> 16U) & 0xffU) +#define gr_pri_gpc0_tpc0_tex_m_routing_r() (0x005042c4U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f() (0x0U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f() (0x1U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f() (0x2U) +#define gr_pri_be0_crop_status1_r() (0x00410134U) +#define gr_pri_bes_crop_status1_r() (0x00408934U) +#define gr_pri_be0_zrop_status_r() (0x00410048U) +#define gr_pri_be0_zrop_status2_r() (0x0041004cU) +#define gr_pri_bes_zrop_status_r() (0x00408848U) +#define gr_pri_bes_zrop_status2_r() (0x0040884cU) +#define gr_pipe_bundle_address_r() (0x00400200U) +#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pipe_bundle_data_r() (0x00400204U) +#define gr_pipe_bundle_config_r() (0x00400208U) +#define gr_pipe_bundle_config_override_pipe_mode_disabled_f() (0x0U) +#define gr_pipe_bundle_config_override_pipe_mode_enabled_f() (0x80000000U) +#define gr_fe_hww_esr_r() (0x00404000U) +#define gr_fe_hww_esr_reset_active_f() (0x40000000U) +#define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) +#define gr_fe_go_idle_timeout_r() (0x00404154U) +#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) +#define gr_fe_go_idle_timeout_count_prod_f() (0x1800U) +#define gr_fe_object_table_r(i)\ + (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) +#define gr_fe_tpc_fs_r() (0x004041c4U) +#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) +#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_mme_hww_esr_r() (0x00404490U) +#define gr_mme_hww_esr_reset_active_f() (0x40000000U) +#define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) +#define gr_memfmt_hww_esr_r() (0x00404600U) +#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) +#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) +#define gr_fecs_cpuctl_r() (0x00409100U) +#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_cpuctl_alias_r() (0x00409130U) +#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_dmactl_r() (0x0040910cU) +#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_fecs_os_r() (0x00409080U) +#define gr_fecs_idlestate_r() (0x0040904cU) +#define gr_fecs_mailbox0_r() (0x00409040U) +#define gr_fecs_mailbox1_r() (0x00409044U) +#define gr_fecs_irqstat_r() (0x00409008U) +#define gr_fecs_irqmode_r() (0x0040900cU) +#define gr_fecs_irqmask_r() (0x00409018U) +#define gr_fecs_irqdest_r() (0x0040901cU) +#define gr_fecs_curctx_r() (0x00409050U) +#define gr_fecs_nxtctx_r() (0x00409054U) +#define gr_fecs_engctl_r() (0x004090a4U) +#define gr_fecs_debug1_r() (0x00409090U) +#define gr_fecs_debuginfo_r() (0x00409094U) +#define gr_fecs_icd_cmd_r() (0x00409200U) +#define gr_fecs_icd_cmd_opc_s() (4U) +#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) +#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) +#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define gr_fecs_icd_rdata_r() (0x0040920cU) +#define gr_fecs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmemc_offs_s() (6U) +#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) +#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmatrfbase_r() (0x00409110U) +#define gr_fecs_dmatrfmoffs_r() (0x00409114U) +#define gr_fecs_dmatrffboffs_r() (0x0040911cU) +#define gr_fecs_dmatrfcmd_r() (0x00409118U) +#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define gr_fecs_bootvec_r() (0x00409104U) +#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_irqsset_r() (0x00409000U) +#define gr_fecs_irqsclr_r() (0x00409004U) +#define gr_fecs_falcon_hwcfg_r() (0x00409108U) +#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) +#define gr_gpcs_gpccs_irqsclr_r() (0x0041a004U) +#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) +#define gr_fecs_falcon_rm_r() (0x00409084U) +#define gr_fecs_current_ctx_r() (0x00409b00U) +#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_current_ctx_target_s() (2U) +#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_current_ctx_valid_s() (1U) +#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_current_ctx_valid_false_f() (0x0U) +#define gr_fecs_method_data_r() (0x00409500U) +#define gr_fecs_method_push_r() (0x00409504U) +#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) +#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) +#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) +#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) +#define gr_fecs_method_push_adr_wfi_golden_save_v() (0x00000009U) +#define gr_fecs_method_push_adr_restore_golden_v() (0x00000015U) +#define gr_fecs_method_push_adr_discover_zcull_image_size_v() (0x00000016U) +#define gr_fecs_method_push_adr_discover_pm_image_size_v() (0x00000025U) +#define gr_fecs_method_push_adr_discover_reglist_image_size_v() (0x00000030U) +#define gr_fecs_method_push_adr_set_reglist_bind_instance_v() (0x00000031U) +#define gr_fecs_method_push_adr_set_reglist_virtual_address_v() (0x00000032U) +#define gr_fecs_method_push_adr_stop_ctxsw_v() (0x00000038U) +#define gr_fecs_method_push_adr_start_ctxsw_v() (0x00000039U) +#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) +#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU) +#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) +#define gr_fecs_host_int_status_r() (0x00409c18U) +#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) +#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) +#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) +#define gr_fecs_host_int_clear_r() (0x00409c20U) +#define gr_fecs_host_int_enable_r() (0x00409c24U) +#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) +#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f() (0x20000U) +#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f() (0x40000U) +#define gr_fecs_host_int_enable_watchdog_enable_f() (0x80000U) +#define gr_fecs_ctxsw_reset_ctl_r() (0x00409614U) +#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() (0x10U) +#define gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() (0x20U) +#define gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() (0x40U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() (0x100U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f() (0x400U) +#define gr_fecs_ctx_state_store_major_rev_id_r() (0x0040960cU) +#define gr_fecs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) +#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) +#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) +#define gr_fecs_ctxsw_mailbox_set_r(i)\ + (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_clear_r(i)\ + (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_fs_r() (0x00409604U) +#define gr_fecs_fs_num_available_gpcs_s() (5U) +#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_fs_num_available_fbps_s() (5U) +#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) +#define gr_fecs_cfg_r() (0x00409620U) +#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_fecs_rc_lanes_r() (0x00409880U) +#define gr_fecs_rc_lanes_num_chains_s() (6U) +#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_fecs_ctxsw_status_1_r() (0x00409400U) +#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) +#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) +#define gr_fecs_new_ctx_r() (0x00409b04U) +#define gr_fecs_new_ctx_ptr_s() (28U) +#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_new_ctx_target_s() (2U) +#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_new_ctx_valid_s() (1U) +#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) +#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) +#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_arb_ctx_ptr_target_s() (2U) +#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) +#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) +#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) +#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r() (0x00502c04U) +#define gr_gpc0_gpccs_ctxsw_status_1_r() (0x00502400U) +#define gr_fecs_ctxsw_idlestate_r() (0x00409420U) +#define gr_fecs_feature_override_ecc_r() (0x00409658U) +#define gr_gpc0_gpccs_ctxsw_idlestate_r() (0x00502420U) +#define gr_rstr2d_gpc_map0_r() (0x0040780cU) +#define gr_rstr2d_gpc_map1_r() (0x00407810U) +#define gr_rstr2d_gpc_map2_r() (0x00407814U) +#define gr_rstr2d_gpc_map3_r() (0x00407818U) +#define gr_rstr2d_gpc_map4_r() (0x0040781cU) +#define gr_rstr2d_gpc_map5_r() (0x00407820U) +#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) +#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_pd_hww_esr_r() (0x00406018U) +#define gr_pd_hww_esr_reset_active_f() (0x40000000U) +#define gr_pd_hww_esr_en_enable_f() (0x80000000U) +#define gr_pd_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) +#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) +#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) +#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) +#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) +#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) +#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) +#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) +#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) +#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) +#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) +#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) +#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) +#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) +#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) +#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) +#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000900U) +#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) +#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) +#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000900U) +#define gr_pd_dist_skip_table_r(i)\ + (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) +#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_ds_debug_r() (0x00405800U) +#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) +#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) +#define gr_ds_zbc_color_r_r() (0x00405804U) +#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_g_r() (0x00405808U) +#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_b_r() (0x0040580cU) +#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_a_r() (0x00405810U) +#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_fmt_r() (0x00405814U) +#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) +#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) +#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) +#define gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v() (0x00000004U) +#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) +#define gr_ds_zbc_z_r() (0x00405818U) +#define gr_ds_zbc_z_val_s() (32U) +#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_ds_zbc_z_val__init_v() (0x00000000U) +#define gr_ds_zbc_z_val__init_f() (0x0U) +#define gr_ds_zbc_z_fmt_r() (0x0040581cU) +#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) +#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) +#define gr_ds_zbc_tbl_index_r() (0x00405820U) +#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) +#define gr_ds_zbc_tbl_ld_r() (0x00405824U) +#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) +#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) +#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) +#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) +#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) +#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) +#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) +#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) +#define gr_ds_hww_esr_r() (0x00405840U) +#define gr_ds_hww_esr_reset_s() (1U) +#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) +#define gr_ds_hww_esr_2_r() (0x00405848U) +#define gr_ds_hww_esr_2_reset_s() (1U) +#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_2_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_2_en_enabled_f() (0x80000000U) +#define gr_ds_hww_report_mask_r() (0x00405844U) +#define gr_ds_hww_report_mask_sph0_err_report_f() (0x1U) +#define gr_ds_hww_report_mask_sph1_err_report_f() (0x2U) +#define gr_ds_hww_report_mask_sph2_err_report_f() (0x4U) +#define gr_ds_hww_report_mask_sph3_err_report_f() (0x8U) +#define gr_ds_hww_report_mask_sph4_err_report_f() (0x10U) +#define gr_ds_hww_report_mask_sph5_err_report_f() (0x20U) +#define gr_ds_hww_report_mask_sph6_err_report_f() (0x40U) +#define gr_ds_hww_report_mask_sph7_err_report_f() (0x80U) +#define gr_ds_hww_report_mask_sph8_err_report_f() (0x100U) +#define gr_ds_hww_report_mask_sph9_err_report_f() (0x200U) +#define gr_ds_hww_report_mask_sph10_err_report_f() (0x400U) +#define gr_ds_hww_report_mask_sph11_err_report_f() (0x800U) +#define gr_ds_hww_report_mask_sph12_err_report_f() (0x1000U) +#define gr_ds_hww_report_mask_sph13_err_report_f() (0x2000U) +#define gr_ds_hww_report_mask_sph14_err_report_f() (0x4000U) +#define gr_ds_hww_report_mask_sph15_err_report_f() (0x8000U) +#define gr_ds_hww_report_mask_sph16_err_report_f() (0x10000U) +#define gr_ds_hww_report_mask_sph17_err_report_f() (0x20000U) +#define gr_ds_hww_report_mask_sph18_err_report_f() (0x40000U) +#define gr_ds_hww_report_mask_sph19_err_report_f() (0x80000U) +#define gr_ds_hww_report_mask_sph20_err_report_f() (0x100000U) +#define gr_ds_hww_report_mask_sph21_err_report_f() (0x200000U) +#define gr_ds_hww_report_mask_sph22_err_report_f() (0x400000U) +#define gr_ds_hww_report_mask_sph23_err_report_f() (0x800000U) +#define gr_ds_hww_report_mask_2_r() (0x0040584cU) +#define gr_ds_hww_report_mask_2_sph24_err_report_f() (0x1U) +#define gr_ds_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_scc_bundle_cb_base_r() (0x00408004U) +#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_bundle_cb_size_r() (0x00408008U) +#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U) +#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) +#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_scc_pagepool_base_r() (0x0040800cU) +#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_pagepool_r() (0x00408010U) +#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) +#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) +#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) +#define gr_scc_pagepool_max_valid_pages_s() (10U) +#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) +#define gr_scc_pagepool_valid_true_f() (0x80000000U) +#define gr_scc_hww_esr_r() (0x00408030U) +#define gr_scc_hww_esr_reset_active_f() (0x40000000U) +#define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) +#define gr_cwd_fs_r() (0x00405b00U) +#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) +#define gr_cwd_gpc_tpc_id_r(i)\ + (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) +#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) +#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) +#define gr_cwd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_sm_id__size_1_v() (0x00000010U) +#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) +#define gr_gpc0_fs_gpc_r() (0x00502608U) +#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) +#define gr_gpc0_cfg_r() (0x00502620U) +#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpccs_rc_lanes_r() (0x00502880U) +#define gr_gpccs_rc_lanes_num_chains_s() (6U) +#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_rc_lane_size_r() (0x00502910U) +#define gr_gpccs_rc_lane_size_v_s() (24U) +#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) +#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) +#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) +#define gr_gpc0_zcull_fs_r() (0x00500910U) +#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) +#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) +#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ + (((v)&0xfU) << 0U) +#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) +#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) +#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) +#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) +#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_zcull_zcsize_r(i)\ + (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) +#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) +#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) +#define gr_gpc0_gpm_pd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ + (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) +#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) +#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) +#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU) +#define gr_gpc0_tpc0_sm_arch_sm_version_v(r) (((r) >> 20U) & 0xfffU) +#define gr_gpc0_ppc0_pes_vsc_strem_r() (0x00503018U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000320U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00000ba8U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ + (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000320U) +#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419b00U) +#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419b04U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) +#define gr_gpccs_falcon_addr_r() (0x0041a0acU) +#define gr_gpccs_falcon_addr_lsb_s() (6U) +#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_msb_s() (6U) +#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) +#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_ext_s() (12U) +#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) +#define gr_gpccs_cpuctl_r() (0x0041a100U) +#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_gpccs_dmactl_r() (0x0041a10cU) +#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_gpccs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt__size_1_v() (0x00000004U) +#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_gpccs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U) +#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x00000de0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ + (0x00000100U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) +#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ + (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ + (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ + (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ + (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ + (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00500100U) +#define gr_gpcs_swdx_dss_zbc_z_r(i)\ + (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0050014cU) +#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) +#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) +#define gr_crstr_gpc_map0_r() (0x00418b08U) +#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map1_r() (0x00418b0cU) +#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map2_r() (0x00418b10U) +#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map3_r() (0x00418b14U) +#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map4_r() (0x00418b18U) +#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map5_r() (0x00418b1cU) +#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_map_table_cfg_r() (0x00418bb8U) +#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) +#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) +#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_gcc_pagepool_r() (0x00419008U) +#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) +#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f()\ + (0x20U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f()\ + (0x80U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\ + (0x200U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f()\ + (0x400U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f()\ + (0x800U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f()\ + (0x1000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f() (0x2000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f() (0x4000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f()\ + (0x8000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f()\ + (0x10000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f()\ + (0x20000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\ + (0x40000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f()\ + (0x800000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f()\ + (0x400000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f()\ + (0x80000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f()\ + (0x100000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() (0x00504644U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() (0x00419e4cU) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f()\ + (0x1U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f()\ + (0x20000000U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f()\ + (0x40000000U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f()\ + (0x40U) +#define gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r() (0x0050464cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r() (0x00419d0cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f() (0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) +#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) +#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) +#define gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_sm_dbgr_control0_r() (0x00504610U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m() (U32(0x1U) << 0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f() (0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m() (U32(0x1U) << 1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m() (U32(0x1U) << 2U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_r() (0x00504614U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_1_r() (0x00504618U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() (0x00504624U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r() (0x00504628U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() (0x00504634U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r() (0x00504638U) +#define gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r() (0x00419e24U) +#define gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_warp_disable_v()\ + (0x00000000U) +#define gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_stop_on_any_sm_disable_v()\ + (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_status0_r() (0x0050460cU) +#define gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(r) (((r) >> 4U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_hww_global_esr_r() (0x00419e50U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_sm_hww_global_esr_r() (0x00504650U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f() (0x20000000U) +#define gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f() (0x40000000U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_tex_m_hww_esr_r() (0x00504224U) +#define gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f() (0x1U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_r() (0x00504648U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) +#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) +#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) +#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) +#define gr_ppcs_wwdx_map_gpc_map1_r() (0x0041bf04U) +#define gr_ppcs_wwdx_map_gpc_map2_r() (0x0041bf08U) +#define gr_ppcs_wwdx_map_gpc_map3_r() (0x0041bf0cU) +#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) +#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) +#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) +#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ + (((v)&0x1fU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ + (((v)&0x7U) << 21U) +#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) +#define gr_bes_zrop_settings_r() (0x00408850U) +#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_be0_crop_debug3_r() (0x00410108U) +#define gr_bes_crop_debug3_r() (0x00408908U) +#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) +#define gr_bes_crop_debug3_blendopt_read_suppress_m() (U32(0x1U) << 1U) +#define gr_bes_crop_debug3_blendopt_read_suppress_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_read_suppress_enabled_f() (0x2U) +#define gr_bes_crop_debug3_blendopt_fill_override_m() (U32(0x1U) << 2U) +#define gr_bes_crop_debug3_blendopt_fill_override_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_fill_override_enabled_f() (0x4U) +#define gr_bes_crop_debug4_r() (0x0040894cU) +#define gr_bes_crop_debug4_clamp_fp_blend_m() (U32(0x1U) << 18U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) +#define gr_bes_crop_settings_r() (0x00408958U) +#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) +#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) +#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) +#define gr_zcull_subregion_qty_v() (0x00000010U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r() (0x00504604U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r() (0x00504608U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r() (0x0050465cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r() (0x00504660U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r() (0x00504664U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r() (0x00504668U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r() (0x0050466cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r() (0x00504658U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r() (0x00504730U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r() (0x00504734U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r() (0x00504738U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r() (0x0050473cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r() (0x00504740U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r() (0x00504744U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r() (0x00504748U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r() (0x0050474cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r() (0x00504678U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r() (0x00504694U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r() (0x005046f0U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r() (0x00504700U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r() (0x005046f4U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r() (0x00504704U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r() (0x005046f8U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r() (0x00504708U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r() (0x005046fcU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r() (0x0050470cU) +#define gr_fe_pwr_mode_r() (0x00404170U) +#define gr_fe_pwr_mode_mode_auto_f() (0x0U) +#define gr_fe_pwr_mode_mode_force_on_f() (0x2U) +#define gr_fe_pwr_mode_req_v(r) (((r) >> 4U) & 0x1U) +#define gr_fe_pwr_mode_req_send_f() (0x10U) +#define gr_fe_pwr_mode_req_done_v() (0x00000000U) +#define gr_gpcs_pri_mmu_ctrl_r() (0x00418880U) +#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() (U32(0x1U) << 0U) +#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() (U32(0x1U) << 11U) +#define gr_gpcs_pri_mmu_ctrl_vol_fault_m() (U32(0x1U) << 1U) +#define gr_gpcs_pri_mmu_ctrl_comp_fault_m() (U32(0x1U) << 2U) +#define gr_gpcs_pri_mmu_ctrl_miss_gran_m() (U32(0x3U) << 3U) +#define gr_gpcs_pri_mmu_ctrl_cache_mode_m() (U32(0x3U) << 5U) +#define gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() (U32(0x3U) << 28U) +#define gr_gpcs_pri_mmu_ctrl_mmu_vol_m() (U32(0x1U) << 30U) +#define gr_gpcs_pri_mmu_ctrl_mmu_disable_m() (U32(0x1U) << 31U) +#define gr_gpcs_pri_mmu_pm_unit_mask_r() (0x00418890U) +#define gr_gpcs_pri_mmu_pm_req_mask_r() (0x00418894U) +#define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define gr_gpcs_pri_mmu_debug_wr_r() (0x004188b4U) +#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) +#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) +#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m() (U32(0x1U) << 30U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) +#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) +#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419c84U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ + (((v)&0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_disp_ctrl_r() (0x00419f78U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) +#define gr_gpcs_tc_debug0_r() (0x00418708U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h index ac6357ef9..9f57311f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,504 +59,155 @@ #include #include -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} +#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U) +#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U) +#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U) +#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U) +#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U) +#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU) +#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) +#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) +#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU) +#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) +#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) +#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU) +#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U) +#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U) +#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param2_r() (0x0017e3f4U) +#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) +#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ + (((v)&0x1fU) << 16U) +#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ + (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ + (U32(0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffffffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U) +#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U) +#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U) +#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc1_ltss_g_elpg_r() (0x00142214U) +#define ltc_ltc1_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc1_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc1_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltcs_ltss_intr_r() (0x0017e20cU) +#define ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() (0x100U) +#define ltc_ltcs_ltss_intr_ecc_ded_error_pending_f() (0x200U) +#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U) +#define ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() (0x1000000U) +#define ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f() (0x2000000U) +#define ltc_ltc0_lts0_intr_r() (0x0014040cU) +#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU) +#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\ + (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\ + (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\ + (0x40000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\ + (((r) >> 16U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U) +#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltc1_ltss_tstg_cmgmt0_r() (0x001422a0U) +#define ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc1_ltss_tstg_cmgmt1_r() (0x001422a4U) +#define ltc_ltc1_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltc0_lts0_tstg_info_1_r() (0x0014058cU) +#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h index affd0ea5a..7c13a4452 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,196 +59,57 @@ #include #include -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_replayable_fault_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} +#define mc_boot_0_r() (0x00000000U) +#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU) +#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU) +#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU) +#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU) +#define mc_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_pfifo_pending_f() (0x100U) +#define mc_intr_replayable_fault_pending_f() (0x200U) +#define mc_intr_pgraph_pending_f() (0x1000U) +#define mc_intr_pmu_pending_f() (0x1000000U) +#define mc_intr_ltc_pending_f() (0x2000000U) +#define mc_intr_priv_ring_pending_f() (0x40000000U) +#define mc_intr_pbus_pending_f() (0x10000000U) +#define mc_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_clear_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_enable_r() (0x00000200U) +#define mc_enable_xbar_enabled_f() (0x4U) +#define mc_enable_l2_enabled_f() (0x8U) +#define mc_enable_pmedia_s() (1U) +#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) +#define mc_enable_pmedia_m() (U32(0x1U) << 4U) +#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) +#define mc_enable_priv_ring_enabled_f() (0x20U) +#define mc_enable_ce0_m() (U32(0x1U) << 6U) +#define mc_enable_pfifo_enabled_f() (0x100U) +#define mc_enable_pgraph_enabled_f() (0x1000U) +#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U) +#define mc_enable_pwr_disabled_v() (0x00000000U) +#define mc_enable_pwr_enabled_f() (0x2000U) +#define mc_enable_pfb_enabled_f() (0x100000U) +#define mc_enable_ce2_m() (U32(0x1U) << 21U) +#define mc_enable_ce2_enabled_f() (0x200000U) +#define mc_enable_blg_enabled_f() (0x8000000U) +#define mc_enable_perfmon_enabled_f() (0x10000000U) +#define mc_enable_hub_enabled_f() (0x20000000U) +#define mc_intr_ltc_r() (0x000001c0U) +#define mc_enable_pb_r() (0x00000204U) +#define mc_enable_pb_0_s() (1U) +#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) +#define mc_enable_pb_0_m() (U32(0x1U) << 0U) +#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) +#define mc_enable_pb_0_enabled_v() (0x00000001U) +#define mc_enable_pb_sel_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define mc_elpg_enable_r() (0x0000020cU) +#define mc_elpg_enable_xbar_enabled_f() (0x4U) +#define mc_elpg_enable_pfb_enabled_f() (0x100000U) +#define mc_elpg_enable_hub_enabled_f() (0x20000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h index 94b97c6a9..d7a367dc2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,480 +59,161 @@ #include #include -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method3_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_data0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} +#define pbdma_gp_entry1_r() (0x10000004U) +#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) +#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) +#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) +#define pbdma_gp_base_r(i)\ + (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base__size_1_v() (0x00000004U) +#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) +#define pbdma_gp_base_rsvd_s() (3U) +#define pbdma_gp_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) +#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) +#define pbdma_gp_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_get_r(i)\ + (nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_put_r(i)\ + (nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_r(i)\ + (nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_r(i)\ + (nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_r(i)\ + (nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_gp_fermi0_f() (0x0U) +#define pbdma_formats_pb_fermi1_f() (0x100U) +#define pbdma_formats_mp_fermi0_f() (0x0U) +#define pbdma_pb_header_r(i)\ + (nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_priv_user_f() (0x0U) +#define pbdma_pb_header_method_zero_f() (0x0U) +#define pbdma_pb_header_subchannel_zero_f() (0x0U) +#define pbdma_pb_header_level_main_f() (0x0U) +#define pbdma_pb_header_first_true_f() (0x400000U) +#define pbdma_pb_header_type_inc_f() (0x20000000U) +#define pbdma_pb_header_type_non_inc_f() (0x60000000U) +#define pbdma_hdr_shadow_r(i)\ + (nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_0_r(i)\ + (nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_1_r(i)\ + (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_r(i)\ + (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) +#define pbdma_subdevice_status_active_f() (0x10000000U) +#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) +#define pbdma_method0_r(i)\ + (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method0_fifo_size_v() (0x00000004U) +#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) +#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) +#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) +#define pbdma_method0_first_true_f() (0x400000U) +#define pbdma_method0_valid_true_f() (0x80000000U) +#define pbdma_method1_r(i)\ + (nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method2_r(i)\ + (nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method3_r(i)\ + (nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_data0_r(i)\ + (nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_r(i)\ + (nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_engine_sw_f() (0x1fU) +#define pbdma_acquire_r(i)\ + (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_retry_man_2_f() (0x2U) +#define pbdma_acquire_retry_exp_2_f() (0x100U) +#define pbdma_acquire_timeout_exp_max_f() (0x7800U) +#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) +#define pbdma_acquire_timeout_en_disable_f() (0x0U) +#define pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_channel_r(i)\ + (nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_r(i)\ + (nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_hw_valid_f() (0xfaceU) +#define pbdma_signature_sw_zero_f() (0x0U) +#define pbdma_userd_r(i)\ + (nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_target_vid_mem_f() (0x0U) +#define pbdma_userd_target_sys_mem_coh_f() (0x2U) +#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) +#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) +#define pbdma_userd_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) +#define pbdma_config_r(i)\ + (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_config_auth_level_privileged_f() (0x100U) +#define pbdma_hce_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) +#define pbdma_intr_0_r(i)\ + (nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_intr_0_memreq_pending_f() (0x1U) +#define pbdma_intr_0_memack_timeout_pending_f() (0x2U) +#define pbdma_intr_0_memack_extra_pending_f() (0x4U) +#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U) +#define pbdma_intr_0_memdat_extra_pending_f() (0x10U) +#define pbdma_intr_0_memflush_pending_f() (0x20U) +#define pbdma_intr_0_memop_pending_f() (0x40U) +#define pbdma_intr_0_lbconnect_pending_f() (0x80U) +#define pbdma_intr_0_lbreq_pending_f() (0x100U) +#define pbdma_intr_0_lback_timeout_pending_f() (0x200U) +#define pbdma_intr_0_lback_extra_pending_f() (0x400U) +#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U) +#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U) +#define pbdma_intr_0_gpfifo_pending_f() (0x2000U) +#define pbdma_intr_0_gpptr_pending_f() (0x4000U) +#define pbdma_intr_0_gpentry_pending_f() (0x8000U) +#define pbdma_intr_0_gpcrc_pending_f() (0x10000U) +#define pbdma_intr_0_pbptr_pending_f() (0x20000U) +#define pbdma_intr_0_pbentry_pending_f() (0x40000U) +#define pbdma_intr_0_pbcrc_pending_f() (0x80000U) +#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U) +#define pbdma_intr_0_method_pending_f() (0x200000U) +#define pbdma_intr_0_methodcrc_pending_f() (0x400000U) +#define pbdma_intr_0_device_pending_f() (0x800000U) +#define pbdma_intr_0_semaphore_pending_f() (0x2000000U) +#define pbdma_intr_0_acquire_pending_f() (0x4000000U) +#define pbdma_intr_0_pri_pending_f() (0x8000000U) +#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U) +#define pbdma_intr_0_pbseg_pending_f() (0x40000000U) +#define pbdma_intr_0_signature_pending_f() (0x80000000U) +#define pbdma_intr_1_r(i)\ + (nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_r(i)\ + (nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U) +#define pbdma_intr_en_1_r(i)\ + (nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_r(i)\ + (nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_lbreq_enabled_f() (0x100U) +#define pbdma_intr_stall_1_r(i)\ + (nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U) +#define pbdma_udma_nop_r() (0x00000008U) +#define pbdma_runlist_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_runlist_timeslice_timeout_128_f() (0x80U) +#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U) +#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h index ce8f16c0d..62eb8a31a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,164 +59,44 @@ #include #include -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x001b0000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x001b0fffU; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} +#define perf_pmmsys_base_v() (0x001b0000U) +#define perf_pmmsys_extent_v() (0x001b0fffU) +#define perf_pmasys_control_r() (0x001b4000U) +#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) +#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) +#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) +#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) +#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) +#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) +#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_mem_block_r() (0x001b4070U) +#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) +#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) +#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) +#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) +#define perf_pmasys_mem_block_target_lfb_f() (0x0U) +#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U) +#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) +#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) +#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) +#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) +#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) +#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) +#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) +#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) +#define perf_pmasys_mem_block_valid_false_f() (0x0U) +#define perf_pmasys_outbase_r() (0x001b4074U) +#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_outbaseupper_r() (0x001b4078U) +#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) +#define perf_pmasys_outsize_r() (0x001b407cU) +#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_mem_bytes_r() (0x001b4084U) +#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_mem_bump_r() (0x001b4088U) +#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_enginestatus_r() (0x001b40a4U) +#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) +#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) +#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pnvdec_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pnvdec_gp106.h index e3641da41..585e94c9f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pnvdec_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pnvdec_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,12 +59,6 @@ #include #include -static inline u32 pnvdec_falcon_irqsset_r(void) -{ - return 0x00084000U; -} -static inline u32 pnvdec_falcon_irqsclr_r(void) -{ - return 0x00084004U; -} +#define pnvdec_falcon_irqsset_r() (0x00084000U) +#define pnvdec_falcon_irqsclr_r() (0x00084004U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h index df2beaeae..f4ab1c89c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pram_data032_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U)); -} +#define pram_data032_r(i)\ + (nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h index e976461c1..6d522caf8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringmaster_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,96 +59,27 @@ #include #include -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} +#define pri_ringmaster_command_r() (0x0012004cU) +#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U) +#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU) +#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U) +#define pri_ringmaster_command_cmd_start_ring_f() (0x1U) +#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U) +#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U) +#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U) +#define pri_ringmaster_command_data_r() (0x00120048U) +#define pri_ringmaster_start_results_r() (0x00120050U) +#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U) +#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U) +#define pri_ringmaster_intr_status0_r() (0x00120058U) +#define pri_ringmaster_intr_status1_r() (0x0012005cU) +#define pri_ringmaster_global_ctl_r() (0x00120060U) +#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U) +#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U) +#define pri_ringmaster_enum_fbp_r() (0x00120074U) +#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_gpc_r() (0x00120078U) +#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_ltc_r() (0x0012006cU) +#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h index b5b2a3314..8efeef0e4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,24 +59,10 @@ #include #include -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} +#define pri_ringstation_gpc_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U) +#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) +#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) +#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h index fe97fd5d3..0ba16a2e1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,36 +59,14 @@ #include #include -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} +#define pri_ringstation_sys_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_sys_decode_config_r() (0x00122204U) +#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U) +#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\ + (0x1U) +#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U) +#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) +#define pri_ringstation_sys_priv_error_info_r() (0x00122128U) +#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h index 0f871d995..ed2ba95fa 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_proj_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,124 +59,34 @@ #include #include -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000009U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000005U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} +#define proj_gpc_base_v() (0x00500000U) +#define proj_gpc_shared_base_v() (0x00418000U) +#define proj_gpc_stride_v() (0x00008000U) +#define proj_gpc_priv_stride_v() (0x00000800U) +#define proj_ltc_stride_v() (0x00002000U) +#define proj_lts_stride_v() (0x00000200U) +#define proj_fbpa_base_v() (0x00900000U) +#define proj_fbpa_shared_base_v() (0x009a0000U) +#define proj_fbpa_stride_v() (0x00004000U) +#define proj_ppc_in_gpc_base_v() (0x00003000U) +#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U) +#define proj_ppc_in_gpc_stride_v() (0x00000200U) +#define proj_rop_base_v() (0x00410000U) +#define proj_rop_shared_base_v() (0x00408800U) +#define proj_rop_stride_v() (0x00000400U) +#define proj_tpc_in_gpc_base_v() (0x00004000U) +#define proj_tpc_in_gpc_stride_v() (0x00000800U) +#define proj_tpc_in_gpc_shared_base_v() (0x00001800U) +#define proj_host_num_engines_v() (0x00000009U) +#define proj_host_num_pbdma_v() (0x00000004U) +#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000005U) +#define proj_scal_litter_num_sm_per_tpc_v() (0x00000001U) +#define proj_scal_litter_num_fbps_v() (0x00000006U) +#define proj_scal_litter_num_fbpas_v() (0x00000006U) +#define proj_scal_litter_num_gpcs_v() (0x00000006U) +#define proj_scal_litter_num_pes_per_gpc_v() (0x00000003U) +#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U) +#define proj_scal_litter_num_zcull_banks_v() (0x00000004U) +#define proj_scal_max_gpcs_v() (0x00000020U) +#define proj_scal_max_tpc_per_gpc_v() (0x00000008U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h index 5d8a63ff0..5489d8632 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,560 +59,149 @@ #include #include -static inline u32 psec_falcon_irqsset_r(void) -{ - return 0x00087000U; -} -static inline u32 psec_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqsclr_r(void) -{ - return 0x00087004U; -} -static inline u32 psec_falcon_irqstat_r(void) -{ - return 0x00087008U; -} -static inline u32 psec_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 psec_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 psec_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqmode_r(void) -{ - return 0x0008700cU; -} -static inline u32 psec_falcon_irqmset_r(void) -{ - return 0x00087010U; -} -static inline u32 psec_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_r(void) -{ - return 0x00087014U; -} -static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqmask_r(void) -{ - return 0x00087018U; -} -static inline u32 psec_falcon_irqdest_r(void) -{ - return 0x0008701cU; -} -static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 psec_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 psec_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 psec_falcon_curctx_r(void) -{ - return 0x00087050U; -} -static inline u32 psec_falcon_nxtctx_r(void) -{ - return 0x00087054U; -} -static inline u32 psec_falcon_mailbox0_r(void) -{ - return 0x00087040U; -} -static inline u32 psec_falcon_mailbox1_r(void) -{ - return 0x00087044U; -} -static inline u32 psec_falcon_itfen_r(void) -{ - return 0x00087048U; -} -static inline u32 psec_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_idlestate_r(void) -{ - return 0x0008704cU; -} -static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 psec_falcon_os_r(void) -{ - return 0x00087080U; -} -static inline u32 psec_falcon_engctl_r(void) -{ - return 0x000870a4U; -} -static inline u32 psec_falcon_cpuctl_r(void) -{ - return 0x00087100U; -} -static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_alias_r(void) -{ - return 0x00087130U; -} -static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00087180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 psec_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00087184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 psec_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00087188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 psec_falcon_sctl_r(void) -{ - return 0x00087240U; -} -static inline u32 psec_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 psec_falcon_bootvec_r(void) -{ - return 0x00087104U; -} -static inline u32 psec_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_falcon_dmactl_r(void) -{ - return 0x0008710cU; -} -static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_hwcfg_r(void) -{ - return 0x00087108U; -} -static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 psec_falcon_dmatrfbase_r(void) -{ - return 0x00087110U; -} -static inline u32 psec_falcon_dmatrfbase1_r(void) -{ - return 0x00087128U; -} -static inline u32 psec_falcon_dmatrfmoffs_r(void) -{ - return 0x00087114U; -} -static inline u32 psec_falcon_dmatrfcmd_r(void) -{ - return 0x00087118U; -} -static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 psec_falcon_dmatrffboffs_r(void) -{ - return 0x0008711cU; -} -static inline u32 psec_falcon_exterraddr_r(void) -{ - return 0x00087168U; -} -static inline u32 psec_falcon_exterrstat_r(void) -{ - return 0x0008716cU; -} -static inline u32 psec_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 psec_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 psec_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 psec_sec2_falcon_icd_cmd_r(void) -{ - return 0x00087200U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 psec_sec2_falcon_icd_rdata_r(void) -{ - return 0x0008720cU; -} -static inline u32 psec_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000871c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 psec_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 psec_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 psec_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000871c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_falcon_debug1_r(void) -{ - return 0x00087090U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00087600U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 psec_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 psec_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 psec_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 psec_falcon_engine_r(void) -{ - return 0x000873c0U; -} -static inline u32 psec_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_r(void) -{ - return 0x00087624U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void) -{ - return 0x80U; -} +#define psec_falcon_irqsset_r() (0x00087000U) +#define psec_falcon_irqsset_swgen0_set_f() (0x40U) +#define psec_falcon_irqsclr_r() (0x00087004U) +#define psec_falcon_irqstat_r() (0x00087008U) +#define psec_falcon_irqstat_halt_true_f() (0x10U) +#define psec_falcon_irqstat_exterr_true_f() (0x20U) +#define psec_falcon_irqstat_swgen0_true_f() (0x40U) +#define psec_falcon_irqmode_r() (0x0008700cU) +#define psec_falcon_irqmset_r() (0x00087010U) +#define psec_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define psec_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define psec_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define psec_falcon_irqmclr_r() (0x00087014U) +#define psec_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define psec_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define psec_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define psec_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_irqmask_r() (0x00087018U) +#define psec_falcon_irqdest_r() (0x0008701cU) +#define psec_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define psec_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define psec_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define psec_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define psec_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define psec_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define psec_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define psec_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define psec_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define psec_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define psec_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define psec_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define psec_falcon_curctx_r() (0x00087050U) +#define psec_falcon_nxtctx_r() (0x00087054U) +#define psec_falcon_mailbox0_r() (0x00087040U) +#define psec_falcon_mailbox1_r() (0x00087044U) +#define psec_falcon_itfen_r() (0x00087048U) +#define psec_falcon_itfen_ctxen_enable_f() (0x1U) +#define psec_falcon_idlestate_r() (0x0008704cU) +#define psec_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define psec_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define psec_falcon_os_r() (0x00087080U) +#define psec_falcon_engctl_r() (0x000870a4U) +#define psec_falcon_cpuctl_r() (0x00087100U) +#define psec_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define psec_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define psec_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define psec_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define psec_falcon_cpuctl_alias_r() (0x00087130U) +#define psec_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00087180U, nvgpu_safe_mult_u32((i), 16U))) +#define psec_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define psec_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define psec_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00087184U, nvgpu_safe_mult_u32((i), 16U))) +#define psec_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00087188U, nvgpu_safe_mult_u32((i), 16U))) +#define psec_falcon_sctl_r() (0x00087240U) +#define psec_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define psec_falcon_bootvec_r() (0x00087104U) +#define psec_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define psec_falcon_dmactl_r() (0x0008710cU) +#define psec_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define psec_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define psec_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_hwcfg_r() (0x00087108U) +#define psec_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define psec_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define psec_falcon_dmatrfbase_r() (0x00087110U) +#define psec_falcon_dmatrfbase1_r() (0x00087128U) +#define psec_falcon_dmatrfmoffs_r() (0x00087114U) +#define psec_falcon_dmatrfcmd_r() (0x00087118U) +#define psec_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define psec_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define psec_falcon_dmatrffboffs_r() (0x0008711cU) +#define psec_falcon_exterraddr_r() (0x00087168U) +#define psec_falcon_exterrstat_r() (0x0008716cU) +#define psec_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define psec_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define psec_falcon_exterrstat_valid_true_v() (0x00000001U) +#define psec_sec2_falcon_icd_cmd_r() (0x00087200U) +#define psec_sec2_falcon_icd_cmd_opc_s() (4U) +#define psec_sec2_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define psec_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define psec_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define psec_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define psec_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define psec_sec2_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define psec_sec2_falcon_icd_rdata_r() (0x0008720cU) +#define psec_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000871c0U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define psec_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define psec_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define psec_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define psec_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define psec_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000871c4U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_falcon_debug1_r() (0x00087090U) +#define psec_falcon_debug1_ctxsw_mode_s() (1U) +#define psec_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define psec_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define psec_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define psec_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define psec_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x00087600U, nvgpu_safe_mult_u32((i), 4U))) +#define psec_fbif_transcfg_target_local_fb_f() (0x0U) +#define psec_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define psec_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define psec_fbif_transcfg_mem_type_s() (1U) +#define psec_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define psec_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define psec_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define psec_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define psec_fbif_transcfg_mem_type_physical_f() (0x4U) +#define psec_falcon_engine_r() (0x000873c0U) +#define psec_falcon_engine_reset_true_f() (0x1U) +#define psec_falcon_engine_reset_false_f() (0x0U) +#define psec_fbif_ctl_r() (0x00087624U) +#define psec_fbif_ctl_allow_phys_no_ctx_init_f() (0x0U) +#define psec_fbif_ctl_allow_phys_no_ctx_disallow_f() (0x0U) +#define psec_fbif_ctl_allow_phys_no_ctx_allow_f() (0x80U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h index 5b673e99d..eb09bf966 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,868 +59,242 @@ #include #include -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_host_error_r(void) -{ - return 0x0010a990U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 pwr_falcon_engine_r(void) -{ - return 0x0010a3c0U; -} -static inline u32 pwr_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} +#define pwr_falcon_irqsset_r() (0x0010a000U) +#define pwr_falcon_irqsset_swgen0_set_f() (0x40U) +#define pwr_falcon_irqsclr_r() (0x0010a004U) +#define pwr_falcon_irqstat_r() (0x0010a008U) +#define pwr_falcon_irqstat_halt_true_f() (0x10U) +#define pwr_falcon_irqstat_exterr_true_f() (0x20U) +#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) +#define pwr_falcon_irqmode_r() (0x0010a00cU) +#define pwr_falcon_irqmset_r() (0x0010a010U) +#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_r() (0x0010a014U) +#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmask_r() (0x0010a018U) +#define pwr_falcon_irqdest_r() (0x0010a01cU) +#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pwr_falcon_curctx_r() (0x0010a050U) +#define pwr_falcon_nxtctx_r() (0x0010a054U) +#define pwr_falcon_mailbox0_r() (0x0010a040U) +#define pwr_falcon_mailbox1_r() (0x0010a044U) +#define pwr_falcon_itfen_r() (0x0010a048U) +#define pwr_falcon_itfen_ctxen_enable_f() (0x1U) +#define pwr_falcon_idlestate_r() (0x0010a04cU) +#define pwr_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pwr_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pwr_falcon_os_r() (0x0010a080U) +#define pwr_falcon_engctl_r() (0x0010a0a4U) +#define pwr_falcon_cpuctl_r() (0x0010a100U) +#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) +#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) +#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) +#define pwr_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_sctl_r() (0x0010a240U) +#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pwr_falcon_bootvec_r() (0x0010a104U) +#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_falcon_dmactl_r() (0x0010a10cU) +#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pwr_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_hwcfg_r() (0x0010a108U) +#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pwr_falcon_dmatrfbase_r() (0x0010a110U) +#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) +#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) +#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) +#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) +#define pwr_falcon_exterraddr_r() (0x0010a168U) +#define pwr_falcon_exterrstat_r() (0x0010a16cU) +#define pwr_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pwr_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) +#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) +#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) +#define pwr_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_new_instblk_r() (0x0010a480U) +#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define pwr_pmu_new_instblk_target_fb_f() (0x0U) +#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) +#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) +#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) +#define pwr_pmu_mutex_id_r() (0x0010a488U) +#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) +#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) +#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) +#define pwr_pmu_mutex_r(i)\ + (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mutex__size_1_v() (0x00000010U) +#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) +#define pwr_pmu_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_head__size_1_v() (0x00000004U) +#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) +#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_head_r() (0x0010a4c8U) +#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) +#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_idle_mask_r(i)\ + (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U) +#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) +#define pwr_pmu_idle_count_r(i)\ + (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) +#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_idle_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) +#define pwr_pmu_idle_ctrl_value_busy_f() (0x2U) +#define pwr_pmu_idle_ctrl_value_always_f() (0x3U) +#define pwr_pmu_idle_ctrl_filter_m() (U32(0x1U) << 2U) +#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) +#define pwr_pmu_idle_threshold_r(i)\ + (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_intr_r() (0x0010a9e8U) +#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) +#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) +#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) +#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_intr_clear_v() (0x00000001U) +#define pwr_pmu_idle_mask_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_mask_1_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_ctrl_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_debug_r(i)\ + (nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_debug__size_1_v() (0x00000004U) +#define pwr_pmu_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mailbox__size_1_v() (0x0000000cU) +#define pwr_pmu_bar0_addr_r() (0x0010a7a0U) +#define pwr_pmu_bar0_data_r() (0x0010a7a4U) +#define pwr_pmu_bar0_ctl_r() (0x0010a7acU) +#define pwr_pmu_bar0_timeout_r() (0x0010a7a8U) +#define pwr_pmu_bar0_fecs_error_r() (0x0010a988U) +#define pwr_pmu_bar0_host_error_r() (0x0010a990U) +#define pwr_pmu_bar0_error_status_r() (0x0010a7b0U) +#define pwr_pmu_bar0_error_status_timeout_host_m() (U32(0x1U) << 0U) +#define pwr_pmu_bar0_error_status_timeout_fecs_m() (U32(0x1U) << 1U) +#define pwr_pmu_bar0_error_status_cmd_hwerr_m() (U32(0x1U) << 2U) +#define pwr_pmu_bar0_error_status_err_cmd_m() (U32(0x1U) << 3U) +#define pwr_pmu_bar0_error_status_hosterr_m() (U32(0x1U) << 30U) +#define pwr_pmu_bar0_error_status_fecserr_m() (U32(0x1U) << 31U) +#define pwr_pmu_pg_idlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_ppuidlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_idle_cnt_r(i)\ + (nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_intren_r(i)\ + (nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_target_local_fb_f() (0x0U) +#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pwr_fbif_transcfg_mem_type_s() (1U) +#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pwr_fbif_transcfg_mem_type_physical_f() (0x4U) +#define pwr_falcon_engine_r() (0x0010a3c0U) +#define pwr_falcon_engine_reset_true_f() (0x1U) +#define pwr_falcon_engine_reset_false_f() (0x0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h index a19a3eefb..f33fadea2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,456 +59,117 @@ #include #include -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_v(u32 r) -{ - return (r >> 14U) & 0xfU; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_v(u32 r) -{ - return (r >> 18U) & 0xffU; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} +#define ram_in_ramfc_s() (4096U) +#define ram_in_ramfc_w() (0U) +#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_page_dir_base_target_w() (128U) +#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) +#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) +#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) +#define ram_in_page_dir_base_vol_w() (128U) +#define ram_in_page_dir_base_vol_true_f() (0x4U) +#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_w() (128U) +#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) +#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) +#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) +#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) +#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) +#define ram_in_use_ver2_pt_format_w() (128U) +#define ram_in_use_ver2_pt_format_true_f() (0x400U) +#define ram_in_use_ver2_pt_format_false_f() (0x0U) +#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) +#define ram_in_big_page_size_m() (U32(0x1U) << 11U) +#define ram_in_big_page_size_w() (128U) +#define ram_in_big_page_size_128kb_f() (0x0U) +#define ram_in_big_page_size_64kb_f() (0x800U) +#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_page_dir_base_lo_w() (128U) +#define ram_in_page_dir_base_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_page_dir_base_hi_w() (129U) +#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_adr_limit_lo_w() (130U) +#define ram_in_adr_limit_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_adr_limit_hi_w() (131U) +#define ram_in_engine_cs_w() (132U) +#define ram_in_engine_cs_wfi_v() (0x00000000U) +#define ram_in_engine_cs_wfi_f() (0x0U) +#define ram_in_engine_cs_fg_v() (0x00000001U) +#define ram_in_engine_cs_fg_f() (0x8U) +#define ram_in_gr_cs_w() (132U) +#define ram_in_gr_cs_wfi_f() (0x0U) +#define ram_in_gr_wfi_target_w() (132U) +#define ram_in_gr_wfi_mode_w() (132U) +#define ram_in_gr_wfi_mode_physical_v() (0x00000000U) +#define ram_in_gr_wfi_mode_physical_f() (0x0U) +#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) +#define ram_in_gr_wfi_mode_virtual_f() (0x4U) +#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_gr_wfi_ptr_lo_w() (132U) +#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_gr_wfi_ptr_hi_w() (133U) +#define ram_in_base_shift_v() (0x0000000cU) +#define ram_in_alloc_size_v() (0x00001000U) +#define ram_fc_size_val_v() (0x00000200U) +#define ram_fc_gp_put_w() (0U) +#define ram_fc_userd_w() (2U) +#define ram_fc_userd_hi_w() (3U) +#define ram_fc_signature_w() (4U) +#define ram_fc_gp_get_w() (5U) +#define ram_fc_pb_get_w() (6U) +#define ram_fc_pb_get_hi_w() (7U) +#define ram_fc_pb_top_level_get_w() (8U) +#define ram_fc_pb_top_level_get_hi_w() (9U) +#define ram_fc_acquire_w() (12U) +#define ram_fc_semaphorea_w() (14U) +#define ram_fc_semaphoreb_w() (15U) +#define ram_fc_semaphorec_w() (16U) +#define ram_fc_semaphored_w() (17U) +#define ram_fc_gp_base_w() (18U) +#define ram_fc_gp_base_hi_w() (19U) +#define ram_fc_gp_fetch_w() (20U) +#define ram_fc_pb_fetch_w() (21U) +#define ram_fc_pb_fetch_hi_w() (22U) +#define ram_fc_pb_put_w() (23U) +#define ram_fc_pb_put_hi_w() (24U) +#define ram_fc_pb_header_w() (33U) +#define ram_fc_pb_count_w() (34U) +#define ram_fc_subdevice_w() (37U) +#define ram_fc_formats_w() (39U) +#define ram_fc_target_w() (43U) +#define ram_fc_hce_ctrl_w() (57U) +#define ram_fc_chid_w() (58U) +#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) +#define ram_fc_chid_id_w() (0U) +#define ram_fc_config_w() (61U) +#define ram_fc_runlist_timeslice_w() (62U) +#define ram_userd_base_shift_v() (0x00000009U) +#define ram_userd_chan_size_v() (0x00000200U) +#define ram_userd_put_w() (16U) +#define ram_userd_get_w() (17U) +#define ram_userd_ref_w() (18U) +#define ram_userd_put_hi_w() (19U) +#define ram_userd_top_level_get_w() (22U) +#define ram_userd_top_level_get_hi_w() (23U) +#define ram_userd_get_hi_w() (24U) +#define ram_userd_gp_get_w() (34U) +#define ram_userd_gp_put_w() (35U) +#define ram_userd_gp_top_level_get_w() (22U) +#define ram_userd_gp_top_level_get_hi_w() (23U) +#define ram_rl_entry_size_v() (0x00000008U) +#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) +#define ram_rl_entry_type_chid_f() (0x0U) +#define ram_rl_entry_type_tsg_f() (0x2000U) +#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) +#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) +#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) +#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) +#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) +#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) +#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h index 5310c6a71..1d12fb47b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,84 +59,25 @@ #include #include -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return U32(0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return U32(0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return U32(0xfU) << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} +#define therm_gate_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) +#define therm_gate_ctrl_eng_clk_run_f() (0x0U) +#define therm_gate_ctrl_eng_clk_auto_f() (0x1U) +#define therm_gate_ctrl_eng_clk_stop_f() (0x2U) +#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) +#define therm_gate_ctrl_blk_clk_run_f() (0x0U) +#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) +#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) +#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) +#define therm_fecs_idle_filter_r() (0x00020288U) +#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_hubmmu_idle_filter_r() (0x0002028cU) +#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h index 5c8c17ff0..49ba0e4a1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,60 +59,18 @@ #include #include -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} +#define timer_pri_timeout_r() (0x00009080U) +#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) +#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) +#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) +#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) +#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) +#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) +#define timer_pri_timeout_en_en_disabled_f() (0x0U) +#define timer_pri_timeout_save_0_r() (0x00009084U) +#define timer_pri_timeout_save_1_r() (0x00009088U) +#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU) +#define timer_time_0_r() (0x00009400U) +#define timer_time_1_r() (0x00009410U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h index 43d0c0eb0..325ccc345 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,220 +59,59 @@ #include #include -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbpas_r(void) -{ - return 0x0002243cU; -} -static inline u32 top_num_fbpas_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_device_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_chain_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy0_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_type_enum_copy0_f(void) -{ - return 0x4U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_engine_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_runlist_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_intr_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_reset_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x1fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_scratch1_r(void) -{ - return 0x0002240cU; -} -static inline u32 top_scratch1_devinit_completed_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} +#define top_num_gpcs_r() (0x00022430U) +#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_tpc_per_gpc_r() (0x00022434U) +#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbps_r() (0x00022438U) +#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbpas_r() (0x0002243cU) +#define top_num_fbpas_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_ltc_per_fbp_r() (0x00022450U) +#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_slices_per_ltc_r() (0x0002245cU) +#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_ltcs_r() (0x00022454U) +#define top_device_info_r(i)\ + (nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U))) +#define top_device_info__size_1_v() (0x00000040U) +#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U) +#define top_device_info_chain_enable_v() (0x00000001U) +#define top_device_info_chain_disable_v() (0x00000000U) +#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU) +#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU) +#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU) +#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU) +#define top_device_info_type_enum_graphics_v() (0x00000000U) +#define top_device_info_type_enum_graphics_f() (0x0U) +#define top_device_info_type_enum_copy0_v() (0x00000001U) +#define top_device_info_type_enum_copy0_f() (0x4U) +#define top_device_info_type_enum_copy2_v() (0x00000003U) +#define top_device_info_type_enum_copy2_f() (0xcU) +#define top_device_info_type_enum_lce_v() (0x00000013U) +#define top_device_info_type_enum_lce_f() (0x4cU) +#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U) +#define top_device_info_engine_valid_v() (0x00000001U) +#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U) +#define top_device_info_runlist_valid_v() (0x00000001U) +#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U) +#define top_device_info_intr_valid_v() (0x00000001U) +#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_reset_valid_v() (0x00000001U) +#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) +#define top_device_info_entry_not_valid_v() (0x00000000U) +#define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_engine_type_v() (0x00000003U) +#define top_device_info_entry_data_v() (0x00000001U) +#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U) +#define top_device_info_data_type_enum2_v() (0x00000000U) +#define top_device_info_data_inst_id_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0xfffU) +#define top_device_info_data_pri_base_align_v() (0x0000000cU) +#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x1fU) +#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_data_fault_id_valid_v() (0x00000001U) +#define top_scratch1_r() (0x0002240cU) +#define top_scratch1_devinit_completed_v(r) (((r) >> 1U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h index 4e53809be..db1569c5f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,140 +59,41 @@ #include #include -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void) -{ - return 0x00132924U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s(void) -{ - return 16U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s(void) -{ - return 1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s(void) -{ - return 1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s(void) -{ - return 1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(void) -{ - return 0x70000000U; -} -static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(void) -{ - return 0x00132928U; -} -static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void) -{ - return 0x00132128U; -} -static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void) -{ - return 0x30000000U; -} -static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void) -{ - return 0x0013212cU; -} -static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_r(void) -{ - return 0x001373c0U; -} -static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(void) -{ - return 0x20000000U; -} -static inline u32 trim_sys_clk_cntr_ncltcpll_cnt_r(void) -{ - return 0x001373c4U; -} -static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_r(void) -{ - return 0x001373b0U; -} -static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void) -{ - return 0x001373b4U; -} +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r() (0x00132924U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s() (16U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(v)\ + (((v)&0xffffU) << 0U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m() (U32(0xffffU) << 0U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(r)\ + (((r) >> 0U) & 0xffffU) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s() (1U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(v) (((v)&0x1U) << 16U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m() (U32(0x1U) << 16U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(r) (((r) >> 16U) & 0x1U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f() (0x0U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s() (1U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(v) (((v)&0x1U) << 20U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m() (U32(0x1U) << 20U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(r) (((r) >> 20U) & 0x1U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f() (0x0U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s() (1U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(v) (((v)&0x1U) << 24U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m() (U32(0x1U) << 24U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(r) (((r) >> 24U) & 0x1U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() (0x0U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f() (0x70000000U) +#define trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r() (0x00132928U) +#define trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r() (0x00132128U) +#define trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f()\ + (0x30000000U) +#define trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r() (0x0013212cU) +#define trim_sys_clk_cntr_ncltcpll_cfg_r() (0x001373c0U) +#define trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f() (0x20000000U) +#define trim_sys_clk_cntr_ncltcpll_cnt_r() (0x001373c4U) +#define trim_sys_clk_cntr_ncsyspll_cfg_r() (0x001373b0U) +#define trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f() (0x0U) +#define trim_sys_clk_cntr_ncsyspll_cnt_r() (0x001373b4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h index bde0d33e2..13ca74700 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,88 +59,27 @@ #include #include -static inline u32 xp_dl_mgr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 xp_dl_mgr_safe_timing_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 xp_pl_link_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) -{ - return (v & 0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_m(void) -{ - return U32(0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) -{ - return 0x00000002U; -} -static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_m(void) -{ - return U32(0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) -{ - return 0x00000007U; -} -static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) -{ - return 0x00000006U; -} -static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) -{ - return 0x00000005U; -} -static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) -{ - return 0x00000004U; -} -static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) -{ - return 0x00000000U; -} +#define xp_dl_mgr_r(i)\ + (nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32((i), 4U))) +#define xp_dl_mgr_safe_timing_f(v) (((v)&0x1U) << 2U) +#define xp_pl_link_config_r(i)\ + (nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32((i), 4U))) +#define xp_pl_link_config_ltssm_status_f(v) (((v)&0x1U) << 4U) +#define xp_pl_link_config_ltssm_status_idle_v() (0x00000000U) +#define xp_pl_link_config_ltssm_directive_f(v) (((v)&0xfU) << 0U) +#define xp_pl_link_config_ltssm_directive_m() (U32(0xfU) << 0U) +#define xp_pl_link_config_ltssm_directive_normal_operations_v() (0x00000000U) +#define xp_pl_link_config_ltssm_directive_change_speed_v() (0x00000001U) +#define xp_pl_link_config_max_link_rate_f(v) (((v)&0x3U) << 18U) +#define xp_pl_link_config_max_link_rate_m() (U32(0x3U) << 18U) +#define xp_pl_link_config_max_link_rate_2500_mtps_v() (0x00000002U) +#define xp_pl_link_config_max_link_rate_5000_mtps_v() (0x00000001U) +#define xp_pl_link_config_max_link_rate_8000_mtps_v() (0x00000000U) +#define xp_pl_link_config_target_tx_width_f(v) (((v)&0x7U) << 20U) +#define xp_pl_link_config_target_tx_width_m() (U32(0x7U) << 20U) +#define xp_pl_link_config_target_tx_width_x1_v() (0x00000007U) +#define xp_pl_link_config_target_tx_width_x2_v() (0x00000006U) +#define xp_pl_link_config_target_tx_width_x4_v() (0x00000005U) +#define xp_pl_link_config_target_tx_width_x8_v() (0x00000004U) +#define xp_pl_link_config_target_tx_width_x16_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h index 395ec60e2..547763059 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,152 +59,41 @@ #include #include -static inline u32 xve_rom_ctrl_r(void) -{ - return 0x00000050U; -} -static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) -{ - return 0x0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) -{ - return 0x1U; -} -static inline u32 xve_link_control_status_r(void) -{ - return 0x00000088U; -} -static inline u32 xve_link_control_status_link_speed_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 xve_link_control_status_link_speed_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) -{ - return 0x00000003U; -} -static inline u32 xve_link_control_status_link_width_m(void) -{ - return U32(0x3fU) << 20U; -} -static inline u32 xve_link_control_status_link_width_v(u32 r) -{ - return (r >> 20U) & 0x3fU; -} -static inline u32 xve_link_control_status_link_width_x1_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_width_x2_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_width_x4_v(void) -{ - return 0x00000004U; -} -static inline u32 xve_link_control_status_link_width_x8_v(void) -{ - return 0x00000008U; -} -static inline u32 xve_link_control_status_link_width_x16_v(void) -{ - return 0x00000010U; -} -static inline u32 xve_priv_xv_r(void) -{ - return 0x00000150U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 xve_cya_2_r(void) -{ - return 0x00000704U; -} -static inline u32 xve_reset_r(void) -{ - return 0x00000718U; -} -static inline u32 xve_reset_reset_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 xve_reset_gpu_on_sw_reset_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 xve_reset_counter_en_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 xve_reset_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_m(void) -{ - return U32(0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_v(u32 r) -{ - return (r >> 4U) & 0x7ffU; -} -static inline u32 xve_reset_clock_on_sw_reset_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 xve_reset_clock_counter_en_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 xve_reset_clock_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_m(void) -{ - return U32(0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_v(u32 r) -{ - return (r >> 17U) & 0x7ffU; -} +#define xve_rom_ctrl_r() (0x00000050U) +#define xve_rom_ctrl_rom_shadow_f(v) (((v)&0x1U) << 0U) +#define xve_rom_ctrl_rom_shadow_disabled_f() (0x0U) +#define xve_rom_ctrl_rom_shadow_enabled_f() (0x1U) +#define xve_link_control_status_r() (0x00000088U) +#define xve_link_control_status_link_speed_m() (U32(0xfU) << 16U) +#define xve_link_control_status_link_speed_v(r) (((r) >> 16U) & 0xfU) +#define xve_link_control_status_link_speed_link_speed_2p5_v() (0x00000001U) +#define xve_link_control_status_link_speed_link_speed_5p0_v() (0x00000002U) +#define xve_link_control_status_link_speed_link_speed_8p0_v() (0x00000003U) +#define xve_link_control_status_link_width_m() (U32(0x3fU) << 20U) +#define xve_link_control_status_link_width_v(r) (((r) >> 20U) & 0x3fU) +#define xve_link_control_status_link_width_x1_v() (0x00000001U) +#define xve_link_control_status_link_width_x2_v() (0x00000002U) +#define xve_link_control_status_link_width_x4_v() (0x00000004U) +#define xve_link_control_status_link_width_x8_v() (0x00000008U) +#define xve_link_control_status_link_width_x16_v() (0x00000010U) +#define xve_priv_xv_r() (0x00000150U) +#define xve_priv_xv_cya_l0s_enable_f(v) (((v)&0x1U) << 7U) +#define xve_priv_xv_cya_l0s_enable_m() (U32(0x1U) << 7U) +#define xve_priv_xv_cya_l0s_enable_v(r) (((r) >> 7U) & 0x1U) +#define xve_priv_xv_cya_l1_enable_f(v) (((v)&0x1U) << 8U) +#define xve_priv_xv_cya_l1_enable_m() (U32(0x1U) << 8U) +#define xve_priv_xv_cya_l1_enable_v(r) (((r) >> 8U) & 0x1U) +#define xve_cya_2_r() (0x00000704U) +#define xve_reset_r() (0x00000718U) +#define xve_reset_reset_m() (U32(0x1U) << 0U) +#define xve_reset_gpu_on_sw_reset_m() (U32(0x1U) << 1U) +#define xve_reset_counter_en_m() (U32(0x1U) << 2U) +#define xve_reset_counter_val_f(v) (((v)&0x7ffU) << 4U) +#define xve_reset_counter_val_m() (U32(0x7ffU) << 4U) +#define xve_reset_counter_val_v(r) (((r) >> 4U) & 0x7ffU) +#define xve_reset_clock_on_sw_reset_m() (U32(0x1U) << 15U) +#define xve_reset_clock_counter_en_m() (U32(0x1U) << 16U) +#define xve_reset_clock_counter_val_f(v) (((v)&0x7ffU) << 17U) +#define xve_reset_clock_counter_val_m() (U32(0x7ffU) << 17U) +#define xve_reset_clock_counter_val_v(r) (((r) >> 17U) & 0x7ffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h index af634f1f0..e3085ec1f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,184 +59,49 @@ #include #include -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} +#define bus_bar0_window_r() (0x00001700U) +#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) +#define bus_bar0_window_target_vid_mem_f() (0x0U) +#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) +#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) +#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) +#define bus_bar1_block_r() (0x00001704U) +#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar1_block_target_vid_mem_f() (0x0U) +#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar1_block_mode_virtual_f() (0x80000000U) +#define bus_bar2_block_r() (0x00001714U) +#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar2_block_target_vid_mem_f() (0x0U) +#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar2_block_mode_virtual_f() (0x80000000U) +#define bus_bar1_block_ptr_shift_v() (0x0000000cU) +#define bus_bar2_block_ptr_shift_v() (0x0000000cU) +#define bus_bind_status_r() (0x00001710U) +#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U) +#define bus_bind_status_bar1_pending_empty_f() (0x0U) +#define bus_bind_status_bar1_pending_busy_f() (0x1U) +#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define bus_bind_status_bar1_outstanding_false_f() (0x0U) +#define bus_bind_status_bar1_outstanding_true_f() (0x2U) +#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U) +#define bus_bind_status_bar2_pending_empty_v() (0x00000000U) +#define bus_bind_status_bar2_pending_empty_f() (0x0U) +#define bus_bind_status_bar2_pending_busy_v() (0x00000001U) +#define bus_bind_status_bar2_pending_busy_f() (0x4U) +#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U) +#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U) +#define bus_bind_status_bar2_outstanding_false_f() (0x0U) +#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U) +#define bus_bind_status_bar2_outstanding_true_f() (0x8U) +#define bus_intr_0_r() (0x00001100U) +#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U) +#define bus_intr_en_0_r() (0x00001140U) +#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h index 7d8fdcae4..823054760 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,148 +59,42 @@ #include #include -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_in_use_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 ccsr_channel_status_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acquire_v(void) -{ - return 0x00000003U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_v(void) -{ - return 0x00000005U; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void) -{ - return 0x00000006U; -} -static inline u32 ccsr_channel_status_on_eng_v(void) -{ - return 0x00000007U; -} -static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void) -{ - return 0x00000008U; -} -static inline u32 ccsr_channel_status_on_eng_pending_v(void) -{ - return 0x00000009U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ccsr_channel_busy_true_v(void) -{ - return 0x00000001U; -} +#define ccsr_channel_inst_r(i)\ + (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel_inst__size_1_v() (0x00000200U) +#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define ccsr_channel_inst_target_vid_mem_f() (0x0U) +#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) +#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) +#define ccsr_channel_inst_bind_false_f() (0x0U) +#define ccsr_channel_inst_bind_true_f() (0x80000000U) +#define ccsr_channel_r(i)\ + (nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel__size_1_v() (0x00000200U) +#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) +#define ccsr_channel_enable_in_use_v() (0x00000001U) +#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) +#define ccsr_channel_enable_set_true_f() (0x400U) +#define ccsr_channel_enable_clr_true_f() (0x800U) +#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) +#define ccsr_channel_status_idle_v() (0x00000000U) +#define ccsr_channel_status_pending_v() (0x00000001U) +#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U) +#define ccsr_channel_status_pending_acquire_v() (0x00000003U) +#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U) +#define ccsr_channel_status_on_pbdma_v() (0x00000005U) +#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U) +#define ccsr_channel_status_on_eng_v() (0x00000007U) +#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U) +#define ccsr_channel_status_on_eng_pending_v() (0x00000009U) +#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU) +#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU) +#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU) +#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU) +#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU) +#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) +#define ccsr_channel_next_true_v() (0x00000001U) +#define ccsr_channel_force_ctx_reload_true_f() (0x100U) +#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U) +#define ccsr_channel_busy_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h index c44a3f0c5..428763d83 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ce_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,12 @@ #include #include -static inline u32 ce_intr_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32(i, 128U)); -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} +#define ce_intr_status_r(i)\ + (nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U))) +#define ce_intr_status_blockpipe_pending_f() (0x1U) +#define ce_intr_status_blockpipe_reset_f() (0x1U) +#define ce_intr_status_nonblockpipe_pending_f() (0x2U) +#define ce_intr_status_nonblockpipe_reset_f() (0x2U) +#define ce_intr_status_launcherr_pending_f() (0x4U) +#define ce_intr_status_launcherr_reset_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h index 26215554a..c4003d340 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,440 +59,144 @@ #include #include -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_gpccs_header_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pmu_options_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000acU; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4U; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeefU; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return U32(0xffU) << 24U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000aU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000bU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000dU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000U; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ffU; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000U; -} +#define ctxsw_prog_fecs_header_v() (0x00000100U) +#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) +#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) +#define ctxsw_prog_main_image_patch_count_o() (0x00000010U) +#define ctxsw_prog_main_image_context_id_o() (0x000000f0U) +#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U) +#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U) +#define ctxsw_prog_main_image_zcull_o() (0x0000001cU) +#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U) +#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U) +#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U) +#define ctxsw_prog_main_image_pm_o() (0x00000028U) +#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U) +#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U) +#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) +#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) +#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) +#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) +#define ctxsw_prog_main_image_num_wfi_save_ops_o() (0x000000d0U) +#define ctxsw_prog_main_image_num_cta_save_ops_o() (0x000000d4U) +#define ctxsw_prog_main_image_num_gfxp_save_ops_o() (0x000000d8U) +#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU) +#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) +#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) +#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) +#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) +#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) +#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) +#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U) +#define ctxsw_prog_local_magic_value_o() (0x000000fcU) +#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU) +#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU) +#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU) +#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U) +#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\ + (0x00000000U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\ + (0x00000002U) +#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ + (((r) >> 0U) & 0x3U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U) +#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U) +#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U) +#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU) +#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U) +#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) +#define ctxsw_prog_main_image_pmu_options_o() (0x00000070U) +#define ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(v)\ + (((v)&0x1U) << 0U) +#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ + (0x1U) +#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) +#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) +#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU) +#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\ + (((v)&0xffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\ + (U32(0xfffffffU) << 0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m()\ + (U32(0x3U) << 28U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f()\ + (0x0U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f()\ + (0x20000000U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f()\ + (0x30000000U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U) +#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U) +#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U) +#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U) +#define ctxsw_prog_record_timestamp_magic_value_lo_v_value_v() (0x00000000U) +#define ctxsw_prog_record_timestamp_magic_value_hi_o() (0x00000004U) +#define ctxsw_prog_record_timestamp_magic_value_hi_v_value_v() (0x600dbeefU) +#define ctxsw_prog_record_timestamp_context_id_o() (0x00000008U) +#define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU) +#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U) +#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U) +#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\ + (((r) >> 0U) & 0xffffffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\ + (0x00000001U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f()\ + (0x1000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v() (0x00000002U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f() (0x2000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v()\ + (0x0000000aU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f() (0xa000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v()\ + (0x0000000bU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f()\ + (0xb000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v()\ + (0x0000000cU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f()\ + (0xc000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v()\ + (0x0000000dU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f()\ + (0xd000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v() (0x00000003U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f() (0x3000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v()\ + (0x00000004U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f()\ + (0x4000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v()\ + (0x00000005U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f()\ + (0x5000000U) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v()\ + (0x000000ffU) +#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\ + (0xff000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h index 6f34f4594..110ec6b0f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,548 +59,145 @@ #include #include -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} +#define falcon_falcon_irqsset_r() (0x00000000U) +#define falcon_falcon_irqsset_swgen0_set_f() (0x40U) +#define falcon_falcon_irqsclr_r() (0x00000004U) +#define falcon_falcon_irqstat_r() (0x00000008U) +#define falcon_falcon_irqstat_halt_true_f() (0x10U) +#define falcon_falcon_irqstat_exterr_true_f() (0x20U) +#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) +#define falcon_falcon_irqmode_r() (0x0000000cU) +#define falcon_falcon_irqmset_r() (0x00000010U) +#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_r() (0x00000014U) +#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqmask_r() (0x00000018U) +#define falcon_falcon_irqdest_r() (0x0000001cU) +#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define falcon_falcon_curctx_r() (0x00000050U) +#define falcon_falcon_nxtctx_r() (0x00000054U) +#define falcon_falcon_mailbox0_r() (0x00000040U) +#define falcon_falcon_mailbox1_r() (0x00000044U) +#define falcon_falcon_itfen_r() (0x00000048U) +#define falcon_falcon_itfen_ctxen_enable_f() (0x1U) +#define falcon_falcon_idlestate_r() (0x0000004cU) +#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define falcon_falcon_os_r() (0x00000080U) +#define falcon_falcon_engctl_r() (0x000000a4U) +#define falcon_falcon_cpuctl_r() (0x00000100U) +#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define falcon_falcon_cpuctl_alias_r() (0x00000130U) +#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) +#define falcon_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_sctl_r() (0x00000240U) +#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define falcon_falcon_bootvec_r() (0x00000104U) +#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define falcon_falcon_dmactl_r() (0x0000010cU) +#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_hwcfg_r() (0x00000108U) +#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define falcon_falcon_dmatrfbase_r() (0x00000110U) +#define falcon_falcon_dmatrfbase1_r() (0x00000128U) +#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) +#define falcon_falcon_imctl_debug_r() (0x0000015cU) +#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) +#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) +#define falcon_falcon_imstat_r() (0x00000144U) +#define falcon_falcon_traceidx_r() (0x00000148U) +#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) +#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) +#define falcon_falcon_tracepc_r() (0x0000014cU) +#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) +#define falcon_falcon_dmatrfcmd_r() (0x00000118U) +#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) +#define falcon_falcon_exterraddr_r() (0x0010a168U) +#define falcon_falcon_exterrstat_r() (0x0010a16cU) +#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) +#define falcon_falcon_icd_cmd_r() (0x00000200U) +#define falcon_falcon_icd_cmd_opc_s() (4U) +#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define falcon_falcon_icd_rdata_r() (0x0000020cU) +#define falcon_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define falcon_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_debug1_r() (0x00000090U) +#define falcon_falcon_debug1_ctxsw_mode_s() (1U) +#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define falcon_falcon_debuginfo_r() (0x00000094U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h index ea016d345..3380e40b7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,408 +59,105 @@ #include #include -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) -{ - return 0x18U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return U32(0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return U32(0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return U32(0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return U32(0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} +#define fb_fbhub_num_active_ltcs_r() (0x00100800U) +#define fb_mmu_ctrl_r() (0x00100c80U) +#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) +#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) +#define fb_priv_mmu_phy_secure_r() (0x00100ce4U) +#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) +#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) +#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_invalidate_r() (0x00100cbcU) +#define fb_mmu_invalidate_all_va_true_f() (0x1U) +#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) +#define fb_mmu_invalidate_hubtlb_only_s() (1U) +#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) +#define fb_mmu_invalidate_replay_s() (3U) +#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) +#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) +#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) +#define fb_mmu_invalidate_replay_none_f() (0x0U) +#define fb_mmu_invalidate_replay_start_f() (0x8U) +#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U) +#define fb_mmu_invalidate_replay_cancel_targeted_f() (0x18U) +#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) +#define fb_mmu_invalidate_replay_cancel_f() (0x20U) +#define fb_mmu_invalidate_sys_membar_s() (1U) +#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) +#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) +#define fb_mmu_invalidate_ack_s() (2U) +#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) +#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) +#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) +#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) +#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) +#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) +#define fb_mmu_invalidate_cancel_client_id_s() (6U) +#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) +#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) +#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) +#define fb_mmu_invalidate_cancel_client_type_s() (1U) +#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) +#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) +#define fb_mmu_invalidate_cancel_cache_level_s() (3U) +#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) +#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) +#define fb_mmu_invalidate_cancel_cache_level_pte_only_f() (0x1000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f() (0x2000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f() (0x3000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f() (0x4000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f() (0x5000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) +#define fb_mmu_invalidate_trigger_s() (1U) +#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) +#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) +#define fb_mmu_debug_wr_r() (0x00100cc8U) +#define fb_mmu_debug_wr_aperture_s() (2U) +#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_wr_vol_false_f() (0x0U) +#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) +#define fb_mmu_debug_wr_vol_true_f() (0x4U) +#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_rd_r() (0x00100cccU) +#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_rd_vol_false_f() (0x0U) +#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_ctrl_r() (0x00100cc4U) +#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_mmu_vpr_info_r() (0x00100cd0U) +#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U) +#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U) +#define fb_niso_flush_sysmem_addr_r() (0x00100c10U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h index 67828efe4..6f152e251 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,652 +59,185 @@ #include #include -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254U; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000U; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000aU; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259cU; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0U; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fifo_intr_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return U32(0x3fffffffU) << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262cU; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_r(void) -{ - return 0x00002a70U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_hi_r(void) -{ - return 0x00002a74U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_size_r(void) -{ - return 0x00002a78U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) -{ - return 0x000000c0U; -} -static inline u32 fifo_replay_fault_buffer_get_r(void) -{ - return 0x00002a7cU; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_put_r(void) -{ - return 0x00002a80U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_r(void) -{ - return 0x00002a84U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) -{ - return 0x00000001U; -} +#define fifo_bar1_base_r() (0x00002254U) +#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) +#define fifo_bar1_base_valid_false_f() (0x0U) +#define fifo_bar1_base_valid_true_f() (0x10000000U) +#define fifo_runlist_base_r() (0x00002270U) +#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_runlist_base_target_vid_mem_f() (0x0U) +#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) +#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) +#define fifo_runlist_r() (0x00002274U) +#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) +#define fifo_eng_runlist_base_r(i)\ + (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist_base__size_1_v() (0x00000001U) +#define fifo_eng_runlist_r(i)\ + (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist__size_1_v() (0x00000001U) +#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) +#define fifo_eng_runlist_length_max_v() (0x0000ffffU) +#define fifo_eng_runlist_pending_true_f() (0x100000U) +#define fifo_pb_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pb_timeslice_timeout_16_f() (0x10U) +#define fifo_pb_timeslice_timescale_0_f() (0x0U) +#define fifo_pb_timeslice_enable_true_f() (0x10000000U) +#define fifo_pbdma_map_r(i)\ + (nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_0_r() (0x00002100U) +#define fifo_intr_0_bind_error_pending_f() (0x1U) +#define fifo_intr_0_bind_error_reset_f() (0x1U) +#define fifo_intr_0_sched_error_pending_f() (0x100U) +#define fifo_intr_0_sched_error_reset_f() (0x100U) +#define fifo_intr_0_chsw_error_pending_f() (0x10000U) +#define fifo_intr_0_chsw_error_reset_f() (0x10000U) +#define fifo_intr_0_fb_flush_timeout_pending_f() (0x800000U) +#define fifo_intr_0_fb_flush_timeout_reset_f() (0x800000U) +#define fifo_intr_0_lb_error_pending_f() (0x1000000U) +#define fifo_intr_0_lb_error_reset_f() (0x1000000U) +#define fifo_intr_0_replayable_fault_error_pending_f() (0x2000000U) +#define fifo_intr_0_dropped_mmu_fault_pending_f() (0x8000000U) +#define fifo_intr_0_dropped_mmu_fault_reset_f() (0x8000000U) +#define fifo_intr_0_mmu_fault_pending_f() (0x10000000U) +#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U) +#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) +#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) +#define fifo_intr_en_0_r() (0x00002140U) +#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) +#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) +#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) +#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) +#define fifo_intr_en_1_r() (0x00002528U) +#define fifo_intr_bind_error_r() (0x0000252cU) +#define fifo_intr_sched_error_r() (0x0000254cU) +#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) +#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) +#define fifo_intr_chsw_error_r() (0x0000256cU) +#define fifo_intr_mmu_fault_id_r() (0x0000259cU) +#define fifo_intr_mmu_fault_eng_id_graphics_v() (0x00000000U) +#define fifo_intr_mmu_fault_eng_id_graphics_f() (0x0U) +#define fifo_intr_mmu_fault_inst_r(i)\ + (nvgpu_safe_add_u32(0x00002800U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_inst_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define fifo_intr_mmu_fault_inst_ptr_align_shift_v() (0x0000000cU) +#define fifo_intr_mmu_fault_lo_r(i)\ + (nvgpu_safe_add_u32(0x00002804U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_hi_r(i)\ + (nvgpu_safe_add_u32(0x00002808U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_r(i)\ + (nvgpu_safe_add_u32(0x0000280cU, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_intr_mmu_fault_info_type_v(r) (((r) >> 0U) & 0x1fU) +#define fifo_intr_mmu_fault_info_access_type_v(r) (((r) >> 16U) & 0x7U) +#define fifo_intr_mmu_fault_info_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fifo_intr_mmu_fault_info_client_type_gpc_v() (0x00000000U) +#define fifo_intr_mmu_fault_info_client_type_hub_v() (0x00000001U) +#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU) +#define fifo_intr_pbdma_id_r() (0x000025a0U) +#define fifo_intr_pbdma_id_status_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_pbdma_id_status_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U) +#define fifo_intr_runlist_r() (0x00002a00U) +#define fifo_fb_timeout_r() (0x00002a04U) +#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U) +#define fifo_fb_timeout_period_max_f() (0x3fffffffU) +#define fifo_error_sched_disable_r() (0x0000262cU) +#define fifo_sched_disable_r() (0x00002630U) +#define fifo_sched_disable_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_sched_disable_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_sched_disable_true_v() (0x00000001U) +#define fifo_preempt_r() (0x00002634U) +#define fifo_preempt_pending_true_f() (0x100000U) +#define fifo_preempt_type_channel_f() (0x0U) +#define fifo_preempt_type_tsg_f() (0x1000000U) +#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) +#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) +#define fifo_trigger_mmu_fault_r(i)\ + (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) +#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) +#define fifo_engine_status_r(i)\ + (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_engine_status__size_1_v() (0x00000002U) +#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_engine_status_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_engine_status_ctx_status_invalid_v() (0x00000000U) +#define fifo_engine_status_ctx_status_valid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U) +#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U) +#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U) +#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_engine_status_next_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U) +#define fifo_engine_status_faulted_true_v() (0x00000001U) +#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U) +#define fifo_engine_status_engine_idle_v() (0x00000000U) +#define fifo_engine_status_engine_busy_v() (0x00000001U) +#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U) +#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U) +#define fifo_pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pbdma_status__size_1_v() (0x00000001U) +#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_pbdma_status_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U) +#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U) +#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U) +#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U) +#define fifo_replay_fault_buffer_lo_r() (0x00002a70U) +#define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U) +#define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U) +#define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U) +#define fifo_replay_fault_buffer_lo_base_f(v) (((v)&0xfffffU) << 12U) +#define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U) +#define fifo_replay_fault_buffer_hi_r() (0x00002a74U) +#define fifo_replay_fault_buffer_hi_base_f(v) (((v)&0xffU) << 0U) +#define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U) +#define fifo_replay_fault_buffer_size_r() (0x00002a78U) +#define fifo_replay_fault_buffer_size_hw_f(v) (((v)&0x1ffU) << 0U) +#define fifo_replay_fault_buffer_size_hw_entries_v() (0x000000c0U) +#define fifo_replay_fault_buffer_get_r() (0x00002a7cU) +#define fifo_replay_fault_buffer_get_offset_hw_f(v) (((v)&0x1ffU) << 0U) +#define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U) +#define fifo_replay_fault_buffer_put_r() (0x00002a80U) +#define fifo_replay_fault_buffer_put_offset_hw_f(v) (((v)&0x1ffU) << 0U) +#define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U) +#define fifo_replay_fault_buffer_info_r() (0x00002a84U) +#define fifo_replay_fault_buffer_info_overflow_f(v) (((v)&0x1U) << 0U) +#define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U) +#define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_write_nack_f(v) (((v)&0x1U) << 24U) +#define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U) +#define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\ + (((v)&0x1U) << 28U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\ + (0x00000000U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\ + (0x00000001U) +#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v()\ + (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h index eb70e3427..9ed14a8ed 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_flush_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,132 +59,36 @@ #include #include -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} +#define flush_l2_system_invalidate_r() (0x00070004U) +#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U) +#define flush_l2_system_invalidate_pending_busy_f() (0x1U) +#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U) +#define flush_l2_flush_dirty_r() (0x00070010U) +#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U) +#define flush_l2_flush_dirty_pending_empty_f() (0x0U) +#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U) +#define flush_l2_flush_dirty_pending_busy_f() (0x1U) +#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U) +#define flush_l2_flush_dirty_outstanding_false_f() (0x0U) +#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U) +#define flush_l2_clean_comptags_r() (0x0007000cU) +#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U) +#define flush_l2_clean_comptags_pending_empty_f() (0x0U) +#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U) +#define flush_l2_clean_comptags_pending_busy_f() (0x1U) +#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U) +#define flush_l2_clean_comptags_outstanding_false_f() (0x0U) +#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U) +#define flush_fb_flush_r() (0x00070000U) +#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_fb_flush_pending_busy_v() (0x00000001U) +#define flush_fb_flush_pending_busy_f() (0x1U) +#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_fb_flush_outstanding_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h index f9d688a6d..d96d0864b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,100 +59,32 @@ #include #include -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} -static inline u32 fuse_opt_sec_debug_en_r(void) -{ - return 0x00021218U; -} -static inline u32 fuse_opt_priv_sec_en_r(void) -{ - return 0x00021434U; -} +#define fuse_status_opt_gpc_r() (0x00021c1cU) +#define fuse_status_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) +#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0xffU) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU) +#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) +#define fuse_status_opt_fbio_r() (0x00021c14U) +#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) +#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) +#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) +#define fuse_status_opt_rop_l2_fbp_r(i)\ + (nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_status_opt_fbp_r() (0x00021d38U) +#define fuse_status_opt_fbp_idx_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fuse_opt_ecc_en_r() (0x00021228U) +#define fuse_opt_feature_fuses_override_disable_r() (0x000213f0U) +#define fuse_opt_sec_debug_en_r() (0x00021218U) +#define fuse_opt_priv_sec_en_r() (0x00021434U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h index 5fcd087c7..0403a7726 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,276 +59,72 @@ #include #include -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} +#define gmmu_new_pde_is_pte_w() (0U) +#define gmmu_new_pde_is_pte_false_f() (0x0U) +#define gmmu_new_pde_aperture_w() (0U) +#define gmmu_new_pde_aperture_invalid_f() (0x0U) +#define gmmu_new_pde_aperture_video_memory_f() (0x2U) +#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pde_address_sys_w() (0U) +#define gmmu_new_pde_vol_w() (0U) +#define gmmu_new_pde_vol_true_f() (0x8U) +#define gmmu_new_pde_vol_false_f() (0x0U) +#define gmmu_new_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_pde__size_v() (0x00000008U) +#define gmmu_new_dual_pde_is_pte_w() (0U) +#define gmmu_new_dual_pde_is_pte_false_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_w() (0U) +#define gmmu_new_dual_pde_aperture_big_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_new_dual_pde_address_big_sys_w() (0U) +#define gmmu_new_dual_pde_aperture_small_w() (2U) +#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_small_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_vol_small_w() (2U) +#define gmmu_new_dual_pde_vol_small_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_small_false_f() (0x0U) +#define gmmu_new_dual_pde_vol_big_w() (0U) +#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) +#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_dual_pde_address_small_sys_w() (2U) +#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) +#define gmmu_new_dual_pde__size_v() (0x00000010U) +#define gmmu_new_pte__size_v() (0x00000008U) +#define gmmu_new_pte_valid_w() (0U) +#define gmmu_new_pte_valid_true_f() (0x1U) +#define gmmu_new_pte_valid_false_f() (0x0U) +#define gmmu_new_pte_privilege_w() (0U) +#define gmmu_new_pte_privilege_true_f() (0x20U) +#define gmmu_new_pte_privilege_false_f() (0x0U) +#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_sys_w() (0U) +#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_vid_w() (0U) +#define gmmu_new_pte_vol_w() (0U) +#define gmmu_new_pte_vol_true_f() (0x8U) +#define gmmu_new_pte_vol_false_f() (0x0U) +#define gmmu_new_pte_aperture_w() (0U) +#define gmmu_new_pte_aperture_video_memory_f() (0x0U) +#define gmmu_new_pte_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pte_read_only_w() (0U) +#define gmmu_new_pte_read_only_true_f() (0x40U) +#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U) +#define gmmu_new_pte_comptagline_w() (1U) +#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) +#define gmmu_new_pte_kind_w() (1U) +#define gmmu_new_pte_address_shift_v() (0x0000000cU) +#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) +#define gmmu_pte_kind_w() (1U) +#define gmmu_pte_kind_invalid_v() (0x000000ffU) +#define gmmu_pte_kind_pitch_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h index e321d8016..e73e1c53b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,4328 +59,1169 @@ #include #include -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x005046b8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b(void) -{ - return 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) -{ - return 0x80U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b(void) -{ - return 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) -{ - return 0x005044a0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) -{ - return 0x005046bcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) -{ - return 0x005046c0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) -{ - return 0x005044a4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void) -{ - return 0x00504218U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void) -{ - return 0x005042ecU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x7fffffffU; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(void) -{ - return 0x004041c4U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_irqsset_r(void) -{ - return 0x00409000U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_irqsset_r(void) -{ - return 0x0041a000U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void) -{ - return 0x0000003dU; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return U32(0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780cU; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810U; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814U; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818U; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781cU; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820U; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x000001c0U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000182U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return U32(0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469cU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00030000U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00030a00U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00030000U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419b00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419b04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return U32(0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void) -{ - return 0x00419a3cU; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return U32(0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000018U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x00500ee4U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000250U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x00500ee0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x00418eecU; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00500100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0050014cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08U; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0cU; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10U; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14U; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18U; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1cU; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7U) << 5U; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7U) << 15U; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7U) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return U32(0x7U) << 28U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28U) & 0x7U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898cU; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00504644U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4cU; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614U; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) -{ - return 0x00504618U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419e24U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) -{ - return U32(0x7U) << 25U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) -{ - return 0x00504654U; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7cU; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0cU; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 24U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fcU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return U32(0x3U) << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return U32(0x3U) << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_debug_2_r(void) -{ - return 0x00400088U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f(void) -{ - return 0x800000U; -} -static inline u32 gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419c84U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return U32(0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419f78U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return U32(0x3U) << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return U32(0xffU) << 0U; -} +#define gr_intr_r() (0x00400100U) +#define gr_intr_notify_pending_f() (0x1U) +#define gr_intr_notify_reset_f() (0x1U) +#define gr_intr_semaphore_pending_f() (0x2U) +#define gr_intr_semaphore_reset_f() (0x2U) +#define gr_intr_illegal_method_pending_f() (0x10U) +#define gr_intr_illegal_method_reset_f() (0x10U) +#define gr_intr_illegal_notify_pending_f() (0x40U) +#define gr_intr_illegal_notify_reset_f() (0x40U) +#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) +#define gr_intr_firmware_method_pending_f() (0x100U) +#define gr_intr_firmware_method_reset_f() (0x100U) +#define gr_intr_illegal_class_pending_f() (0x20U) +#define gr_intr_illegal_class_reset_f() (0x20U) +#define gr_intr_fecs_error_pending_f() (0x80000U) +#define gr_intr_fecs_error_reset_f() (0x80000U) +#define gr_intr_class_error_pending_f() (0x100000U) +#define gr_intr_class_error_reset_f() (0x100000U) +#define gr_intr_exception_pending_f() (0x200000U) +#define gr_intr_exception_reset_f() (0x200000U) +#define gr_fecs_intr_r() (0x00400144U) +#define gr_class_error_r() (0x00400110U) +#define gr_class_error_code_v(r) (((r) >> 0U) & 0xffffU) +#define gr_intr_nonstall_r() (0x00400120U) +#define gr_intr_nonstall_trap_pending_f() (0x2U) +#define gr_intr_en_r() (0x0040013cU) +#define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception1_r() (0x00400118U) +#define gr_exception1_gpc_0_pending_f() (0x1U) +#define gr_exception2_r() (0x0040011cU) +#define gr_exception_en_r() (0x00400138U) +#define gr_exception_en_fe_m() (U32(0x1U) << 0U) +#define gr_exception1_en_r() (0x00400130U) +#define gr_exception2_en_r() (0x00400134U) +#define gr_gpfifo_ctl_r() (0x00400500U) +#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) +#define gr_gpfifo_ctl_access_disabled_f() (0x0U) +#define gr_gpfifo_ctl_access_enabled_f() (0x1U) +#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) +#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) +#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) +#define gr_gpfifo_status_r() (0x00400504U) +#define gr_trapped_addr_r() (0x00400704U) +#define gr_trapped_addr_mthd_v(r) (((r) >> 2U) & 0xfffU) +#define gr_trapped_addr_subch_v(r) (((r) >> 16U) & 0x7U) +#define gr_trapped_addr_mme_generated_v(r) (((r) >> 20U) & 0x1U) +#define gr_trapped_addr_datahigh_v(r) (((r) >> 24U) & 0x1U) +#define gr_trapped_addr_priv_v(r) (((r) >> 28U) & 0x1U) +#define gr_trapped_addr_status_v(r) (((r) >> 31U) & 0x1U) +#define gr_trapped_data_lo_r() (0x00400708U) +#define gr_trapped_data_hi_r() (0x0040070cU) +#define gr_trapped_data_mme_r() (0x00400710U) +#define gr_trapped_data_mme_pc_v(r) (((r) >> 0U) & 0xfffU) +#define gr_status_r() (0x00400700U) +#define gr_status_fe_method_upper_v(r) (((r) >> 1U) & 0x1U) +#define gr_status_fe_method_lower_v(r) (((r) >> 2U) & 0x1U) +#define gr_status_fe_method_lower_idle_v() (0x00000000U) +#define gr_status_fe_gi_v(r) (((r) >> 21U) & 0x1U) +#define gr_status_mask_r() (0x00400610U) +#define gr_status_1_r() (0x00400604U) +#define gr_status_2_r() (0x00400608U) +#define gr_engine_status_r() (0x0040060cU) +#define gr_engine_status_value_busy_f() (0x1U) +#define gr_pri_be0_becs_be_exception_r() (0x00410204U) +#define gr_pri_be0_becs_be_exception_en_r() (0x00410208U) +#define gr_pri_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_pri_gpc0_gpccs_gpc_exception_en_r() (0x00502c94U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_activity_0_r() (0x00400380U) +#define gr_activity_1_r() (0x00400384U) +#define gr_activity_2_r() (0x00400388U) +#define gr_activity_4_r() (0x00400390U) +#define gr_activity_4_gpc0_s() (3U) +#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) +#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) +#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) +#define gr_activity_4_gpc0_empty_v() (0x00000000U) +#define gr_activity_4_gpc0_preempted_v() (0x00000004U) +#define gr_pri_gpc0_gcc_dbg_r() (0x00501000U) +#define gr_pri_gpcs_gcc_dbg_r() (0x00419000U) +#define gr_pri_gpcs_gcc_dbg_invalidate_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cache_control_r() (0x005046a4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_r() (0x00419ea4U) +#define gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m() (U32(0x1U) << 0U) +#define gr_pri_sked_activity_r() (0x00407054U) +#define gr_pri_gpc0_gpccs_gpc_activity0_r() (0x00502c80U) +#define gr_pri_gpc0_gpccs_gpc_activity1_r() (0x00502c84U) +#define gr_pri_gpc0_gpccs_gpc_activity2_r() (0x00502c88U) +#define gr_pri_gpc0_gpccs_gpc_activity3_r() (0x00502c8cU) +#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() (0x00504500U) +#define gr_pri_gpcs_gpccs_gpc_activity_0_r() (0x0041ac80U) +#define gr_pri_gpcs_gpccs_gpc_activity_1_r() (0x0041ac84U) +#define gr_pri_gpcs_gpccs_gpc_activity_2_r() (0x0041ac88U) +#define gr_pri_gpcs_gpccs_gpc_activity_3_r() (0x0041ac8cU) +#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r() (0x00419d00U) +#define gr_pri_be0_becs_be_activity0_r() (0x00410200U) +#define gr_pri_bes_becs_be_activity0_r() (0x00408a00U) +#define gr_pri_ds_mpipe_status_r() (0x00405858U) +#define gr_pri_fe_go_idle_info_r() (0x00404194U) +#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r() (0x00504238U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() (0x005046b8U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_b() (4U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()\ + (0x10U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()\ + (0x20U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()\ + (0x40U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()\ + (0x80U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_b() (8U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()\ + (0x100U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()\ + (0x200U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()\ + (0x400U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()\ + (0x800U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() (0x005044a0U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()\ + (0x1U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()\ + (0x2U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()\ + (0x10U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()\ + (0x20U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()\ + (0x100U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()\ + (0x200U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() (0x005046bcU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() (0x005046c0U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() (0x005044a4U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m()\ + (U32(0xffU) << 0U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(r)\ + (((r) >> 0U) & 0xffU) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()\ + (U32(0xffU) << 8U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(r)\ + (((r) >> 8U) & 0xffU) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()\ + (U32(0xffU) << 16U) +#define gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(r)\ + (((r) >> 16U) & 0xffU) +#define gr_pri_gpc0_tpc0_tex_m_routing_r() (0x005042c4U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f() (0x0U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f() (0x1U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f() (0x2U) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() (0x00504218U) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m() (U32(0xffffU) << 0U) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m() (U32(0xffffU) << 16U) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(r) (((r) >> 16U) & 0xffffU) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() (0x005042ecU) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m() (U32(0xffffU) << 0U) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m() (U32(0xffffU) << 16U) +#define gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(r) (((r) >> 16U) & 0xffffU) +#define gr_pri_be0_crop_status1_r() (0x00410134U) +#define gr_pri_bes_crop_status1_r() (0x00408934U) +#define gr_pri_be0_zrop_status_r() (0x00410048U) +#define gr_pri_be0_zrop_status2_r() (0x0041004cU) +#define gr_pri_bes_zrop_status_r() (0x00408848U) +#define gr_pri_bes_zrop_status2_r() (0x0040884cU) +#define gr_pipe_bundle_address_r() (0x00400200U) +#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pipe_bundle_data_r() (0x00400204U) +#define gr_pipe_bundle_config_r() (0x00400208U) +#define gr_pipe_bundle_config_override_pipe_mode_disabled_f() (0x0U) +#define gr_pipe_bundle_config_override_pipe_mode_enabled_f() (0x80000000U) +#define gr_fe_hww_esr_r() (0x00404000U) +#define gr_fe_hww_esr_reset_active_f() (0x40000000U) +#define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) +#define gr_fe_go_idle_timeout_r() (0x00404154U) +#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) +#define gr_fe_go_idle_timeout_count_prod_f() (0x7fffffffU) +#define gr_fe_object_table_r(i)\ + (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) +#define gr_fe_tpc_fs_r() (0x004041c4U) +#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) +#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_mme_hww_esr_r() (0x00404490U) +#define gr_mme_hww_esr_reset_active_f() (0x40000000U) +#define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) +#define gr_memfmt_hww_esr_r() (0x00404600U) +#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) +#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) +#define gr_fecs_cpuctl_r() (0x00409100U) +#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_cpuctl_alias_r() (0x00409130U) +#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_dmactl_r() (0x0040910cU) +#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_fecs_os_r() (0x00409080U) +#define gr_fecs_idlestate_r() (0x0040904cU) +#define gr_fecs_mailbox0_r() (0x00409040U) +#define gr_fecs_mailbox1_r() (0x00409044U) +#define gr_fecs_irqstat_r() (0x00409008U) +#define gr_fecs_irqmode_r() (0x0040900cU) +#define gr_fecs_irqmask_r() (0x00409018U) +#define gr_fecs_irqdest_r() (0x0040901cU) +#define gr_fecs_curctx_r() (0x00409050U) +#define gr_fecs_nxtctx_r() (0x00409054U) +#define gr_fecs_engctl_r() (0x004090a4U) +#define gr_fecs_debug1_r() (0x00409090U) +#define gr_fecs_debuginfo_r() (0x00409094U) +#define gr_fecs_icd_cmd_r() (0x00409200U) +#define gr_fecs_icd_cmd_opc_s() (4U) +#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) +#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) +#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define gr_fecs_icd_rdata_r() (0x0040920cU) +#define gr_fecs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmemc_offs_s() (6U) +#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) +#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmatrfbase_r() (0x00409110U) +#define gr_fecs_dmatrfmoffs_r() (0x00409114U) +#define gr_fecs_dmatrffboffs_r() (0x0040911cU) +#define gr_fecs_dmatrfcmd_r() (0x00409118U) +#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define gr_fecs_bootvec_r() (0x00409104U) +#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_irqsset_r() (0x00409000U) +#define gr_fecs_falcon_hwcfg_r() (0x00409108U) +#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) +#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) +#define gr_fecs_falcon_rm_r() (0x00409084U) +#define gr_fecs_current_ctx_r() (0x00409b00U) +#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_current_ctx_target_s() (2U) +#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_current_ctx_valid_s() (1U) +#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_current_ctx_valid_false_f() (0x0U) +#define gr_fecs_method_data_r() (0x00409500U) +#define gr_fecs_method_push_r() (0x00409504U) +#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) +#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) +#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) +#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) +#define gr_fecs_method_push_adr_wfi_golden_save_v() (0x00000009U) +#define gr_fecs_method_push_adr_restore_golden_v() (0x00000015U) +#define gr_fecs_method_push_adr_discover_zcull_image_size_v() (0x00000016U) +#define gr_fecs_method_push_adr_discover_pm_image_size_v() (0x00000025U) +#define gr_fecs_method_push_adr_discover_reglist_image_size_v() (0x00000030U) +#define gr_fecs_method_push_adr_set_reglist_bind_instance_v() (0x00000031U) +#define gr_fecs_method_push_adr_set_reglist_virtual_address_v() (0x00000032U) +#define gr_fecs_method_push_adr_stop_ctxsw_v() (0x00000038U) +#define gr_fecs_method_push_adr_start_ctxsw_v() (0x00000039U) +#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) +#define gr_fecs_method_push_adr_write_timestamp_record_v() (0x0000003dU) +#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU) +#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) +#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\ + (0x0000003aU) +#define gr_fecs_host_int_status_r() (0x00409c18U) +#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) +#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) +#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) +#define gr_fecs_host_int_status_watchdog_active_f() (0x80000U) +#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_host_int_clear_r() (0x00409c20U) +#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) +#define gr_fecs_host_int_enable_r() (0x00409c24U) +#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) +#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) +#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f() (0x20000U) +#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f() (0x40000U) +#define gr_fecs_host_int_enable_watchdog_enable_f() (0x80000U) +#define gr_fecs_ctxsw_reset_ctl_r() (0x00409614U) +#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() (0x10U) +#define gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() (0x20U) +#define gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() (0x40U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() (0x100U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f() (0x400U) +#define gr_fecs_ctx_state_store_major_rev_id_r() (0x0040960cU) +#define gr_fecs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) +#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) +#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) +#define gr_fecs_ctxsw_mailbox_set_r(i)\ + (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_clear_r(i)\ + (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_fs_r() (0x00409604U) +#define gr_fecs_fs_num_available_gpcs_s() (5U) +#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_fs_num_available_fbps_s() (5U) +#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) +#define gr_fecs_cfg_r() (0x00409620U) +#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_fecs_rc_lanes_r() (0x00409880U) +#define gr_fecs_rc_lanes_num_chains_s() (6U) +#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_fecs_ctxsw_status_1_r() (0x00409400U) +#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) +#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) +#define gr_fecs_new_ctx_r() (0x00409b04U) +#define gr_fecs_new_ctx_ptr_s() (28U) +#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_new_ctx_target_s() (2U) +#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_new_ctx_valid_s() (1U) +#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) +#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) +#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_arb_ctx_ptr_target_s() (2U) +#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) +#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) +#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) +#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r() (0x00502c04U) +#define gr_gpc0_gpccs_ctxsw_status_1_r() (0x00502400U) +#define gr_fecs_ctxsw_idlestate_r() (0x00409420U) +#define gr_fecs_feature_override_ecc_r() (0x00409658U) +#define gr_fecs_feature_override_ecc_sm_lrf_override_v(r) (((r) >> 3U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_shm_override_v(r) (((r) >> 7U) & 0x1U) +#define gr_fecs_feature_override_ecc_tex_override_v(r) (((r) >> 11U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_override_v(r) (((r) >> 15U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_lrf_v(r) (((r) >> 0U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_shm_v(r) (((r) >> 4U) & 0x1U) +#define gr_fecs_feature_override_ecc_tex_v(r) (((r) >> 8U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_v(r) (((r) >> 12U) & 0x1U) +#define gr_gpc0_gpccs_ctxsw_idlestate_r() (0x00502420U) +#define gr_rstr2d_gpc_map0_r() (0x0040780cU) +#define gr_rstr2d_gpc_map1_r() (0x00407810U) +#define gr_rstr2d_gpc_map2_r() (0x00407814U) +#define gr_rstr2d_gpc_map3_r() (0x00407818U) +#define gr_rstr2d_gpc_map4_r() (0x0040781cU) +#define gr_rstr2d_gpc_map5_r() (0x00407820U) +#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) +#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_pd_hww_esr_r() (0x00406018U) +#define gr_pd_hww_esr_reset_active_f() (0x40000000U) +#define gr_pd_hww_esr_en_enable_f() (0x80000000U) +#define gr_pd_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) +#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) +#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) +#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) +#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) +#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) +#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) +#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) +#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) +#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) +#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) +#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) +#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) +#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) +#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) +#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) +#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x000001c0U) +#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) +#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) +#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000182U) +#define gr_pd_dist_skip_table_r(i)\ + (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) +#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_ds_debug_r() (0x00405800U) +#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) +#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) +#define gr_ds_zbc_color_r_r() (0x00405804U) +#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_g_r() (0x00405808U) +#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_b_r() (0x0040580cU) +#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_a_r() (0x00405810U) +#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_fmt_r() (0x00405814U) +#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) +#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) +#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) +#define gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v() (0x00000004U) +#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) +#define gr_ds_zbc_z_r() (0x00405818U) +#define gr_ds_zbc_z_val_s() (32U) +#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_ds_zbc_z_val__init_v() (0x00000000U) +#define gr_ds_zbc_z_val__init_f() (0x0U) +#define gr_ds_zbc_z_fmt_r() (0x0040581cU) +#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) +#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) +#define gr_ds_zbc_tbl_index_r() (0x00405820U) +#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) +#define gr_ds_zbc_tbl_ld_r() (0x00405824U) +#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) +#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) +#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) +#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) +#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) +#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) +#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) +#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) +#define gr_ds_hww_esr_r() (0x00405840U) +#define gr_ds_hww_esr_reset_s() (1U) +#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) +#define gr_ds_hww_esr_2_r() (0x00405848U) +#define gr_ds_hww_esr_2_reset_s() (1U) +#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_2_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_2_en_enabled_f() (0x80000000U) +#define gr_ds_hww_report_mask_r() (0x00405844U) +#define gr_ds_hww_report_mask_sph0_err_report_f() (0x1U) +#define gr_ds_hww_report_mask_sph1_err_report_f() (0x2U) +#define gr_ds_hww_report_mask_sph2_err_report_f() (0x4U) +#define gr_ds_hww_report_mask_sph3_err_report_f() (0x8U) +#define gr_ds_hww_report_mask_sph4_err_report_f() (0x10U) +#define gr_ds_hww_report_mask_sph5_err_report_f() (0x20U) +#define gr_ds_hww_report_mask_sph6_err_report_f() (0x40U) +#define gr_ds_hww_report_mask_sph7_err_report_f() (0x80U) +#define gr_ds_hww_report_mask_sph8_err_report_f() (0x100U) +#define gr_ds_hww_report_mask_sph9_err_report_f() (0x200U) +#define gr_ds_hww_report_mask_sph10_err_report_f() (0x400U) +#define gr_ds_hww_report_mask_sph11_err_report_f() (0x800U) +#define gr_ds_hww_report_mask_sph12_err_report_f() (0x1000U) +#define gr_ds_hww_report_mask_sph13_err_report_f() (0x2000U) +#define gr_ds_hww_report_mask_sph14_err_report_f() (0x4000U) +#define gr_ds_hww_report_mask_sph15_err_report_f() (0x8000U) +#define gr_ds_hww_report_mask_sph16_err_report_f() (0x10000U) +#define gr_ds_hww_report_mask_sph17_err_report_f() (0x20000U) +#define gr_ds_hww_report_mask_sph18_err_report_f() (0x40000U) +#define gr_ds_hww_report_mask_sph19_err_report_f() (0x80000U) +#define gr_ds_hww_report_mask_sph20_err_report_f() (0x100000U) +#define gr_ds_hww_report_mask_sph21_err_report_f() (0x200000U) +#define gr_ds_hww_report_mask_sph22_err_report_f() (0x400000U) +#define gr_ds_hww_report_mask_sph23_err_report_f() (0x800000U) +#define gr_ds_hww_report_mask_2_r() (0x0040584cU) +#define gr_ds_hww_report_mask_2_sph24_err_report_f() (0x1U) +#define gr_ds_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_scc_bundle_cb_base_r() (0x00408004U) +#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_bundle_cb_size_r() (0x00408008U) +#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U) +#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) +#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_scc_pagepool_base_r() (0x0040800cU) +#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_pagepool_r() (0x00408010U) +#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) +#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) +#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) +#define gr_scc_pagepool_max_valid_pages_s() (10U) +#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) +#define gr_scc_pagepool_valid_true_f() (0x80000000U) +#define gr_scc_hww_esr_r() (0x00408030U) +#define gr_scc_hww_esr_reset_active_f() (0x40000000U) +#define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) +#define gr_cwd_fs_r() (0x00405b00U) +#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) +#define gr_cwd_gpc_tpc_id_r(i)\ + (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) +#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) +#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) +#define gr_cwd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_sm_id__size_1_v() (0x00000010U) +#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) +#define gr_gpc0_fs_gpc_r() (0x00502608U) +#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) +#define gr_gpc0_cfg_r() (0x00502620U) +#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpccs_rc_lanes_r() (0x00502880U) +#define gr_gpccs_rc_lanes_num_chains_s() (6U) +#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_rc_lane_size_r() (0x00502910U) +#define gr_gpccs_rc_lane_size_v_s() (24U) +#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) +#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) +#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) +#define gr_gpc0_zcull_fs_r() (0x00500910U) +#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) +#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) +#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ + (((v)&0xfU) << 0U) +#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) +#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) +#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) +#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) +#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_zcull_zcsize_r(i)\ + (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) +#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) +#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) +#define gr_gpc0_gpm_pd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ + (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) +#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) +#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) +#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU) +#define gr_gpc0_tpc0_sm_arch_sm_version_v(r) (((r) >> 20U) & 0xfffU) +#define gr_gpc0_ppc0_pes_vsc_strem_r() (0x00503018U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00030000U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00030a00U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ + (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00030000U) +#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419b00U) +#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419b04U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) +#define gr_gpcs_tpcs_tex_m_dbg2_r() (0x00419a3cU) +#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(v) (((v)&0x1U) << 2U) +#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m() (U32(0x1U) << 2U) +#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(v) (((v)&0x1U) << 4U) +#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m() (U32(0x1U) << 4U) +#define gr_gpccs_falcon_addr_r() (0x0041a0acU) +#define gr_gpccs_falcon_addr_lsb_s() (6U) +#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_msb_s() (6U) +#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) +#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_ext_s() (12U) +#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) +#define gr_gpccs_cpuctl_r() (0x0041a100U) +#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_gpccs_dmactl_r() (0x0041a10cU) +#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_gpccs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt__size_1_v() (0x00000004U) +#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_gpccs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000018U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x18U) +#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x00500ee4U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x00000250U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ + (0x00000100U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x00500ee0U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) +#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x00418eecU) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ + (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ + (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ + (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ + (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ + (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00500100U) +#define gr_gpcs_swdx_dss_zbc_z_r(i)\ + (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0050014cU) +#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) +#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) +#define gr_crstr_gpc_map0_r() (0x00418b08U) +#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map1_r() (0x00418b0cU) +#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map2_r() (0x00418b10U) +#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map3_r() (0x00418b14U) +#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map4_r() (0x00418b18U) +#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_gpc_map5_r() (0x00418b1cU) +#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) +#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) +#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) +#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) +#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) +#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) +#define gr_crstr_map_table_cfg_r() (0x00418bb8U) +#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) +#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) +#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) +#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) +#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_gcc_pagepool_r() (0x00419008U) +#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) +#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f()\ + (0x20U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f()\ + (0x80U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\ + (0x200U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f()\ + (0x400U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f()\ + (0x800U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f()\ + (0x1000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f() (0x2000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f() (0x4000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f()\ + (0x8000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f()\ + (0x10000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f()\ + (0x20000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\ + (0x40000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f()\ + (0x800000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f()\ + (0x400000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f()\ + (0x80000U) +#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f()\ + (0x100000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() (0x00504644U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() (0x00419e4cU) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f()\ + (0x1U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()\ + (0x4U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f()\ + (0x20000000U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f()\ + (0x40000000U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f()\ + (0x40U) +#define gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r() (0x0050464cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r() (0x00419d0cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f() (0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) +#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) +#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) +#define gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm_dbgr_control0_r() (0x00504610U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m() (U32(0x1U) << 0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m() (U32(0x1U) << 1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m() (U32(0x1U) << 2U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v()\ + (0x00000000U) +#define gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v()\ + (0x00000000U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_r() (0x00504614U) +#define gr_gpc0_tpc0_sm_warp_valid_mask_1_r() (0x00504618U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() (0x00504624U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r() (0x00504628U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() (0x00504634U) +#define gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r() (0x00504638U) +#define gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r() (0x00419e24U) +#define gr_gpc0_tpc0_sm_dbgr_status0_r() (0x0050460cU) +#define gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(r) (((r) >> 4U) & 0x1U) +#define gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_hww_global_esr_r() (0x00419e50U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f() (0x1U) +#define gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() (0x2U) +#define gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f()\ + (0x8U) +#define gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() (0x80000000U) +#define gr_gpc0_tpc0_sm_hww_global_esr_r() (0x00504650U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f() (0x20000000U) +#define gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f() (0x40000000U) +#define gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() (0x1U) +#define gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f() (0x2U) +#define gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f()\ + (0x8U) +#define gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f() (0x80000000U) +#define gr_gpc0_tpc0_tex_m_hww_esr_r() (0x00504224U) +#define gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f() (0x1U) +#define gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f() (0x80U) +#define gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f() (0x100U) +#define gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f() (0x40000000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_r() (0x00504648U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v() (0x00000000U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m() (U32(0x1U) << 24U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m() (U32(0x7U) << 25U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() (0x00504654U) +#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) +#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) +#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) +#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) +#define gr_ppcs_wwdx_map_gpc_map1_r() (0x0041bf04U) +#define gr_ppcs_wwdx_map_gpc_map2_r() (0x0041bf08U) +#define gr_ppcs_wwdx_map_gpc_map3_r() (0x0041bf0cU) +#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) +#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) +#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) +#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ + (((v)&0x1fU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ + (((v)&0x7U) << 21U) +#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) +#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) +#define gr_bes_zrop_settings_r() (0x00408850U) +#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_be0_crop_debug3_r() (0x00410108U) +#define gr_bes_crop_debug3_r() (0x00408908U) +#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) +#define gr_bes_crop_debug3_blendopt_read_suppress_m() (U32(0x1U) << 1U) +#define gr_bes_crop_debug3_blendopt_read_suppress_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_read_suppress_enabled_f() (0x2U) +#define gr_bes_crop_debug3_blendopt_fill_override_m() (U32(0x1U) << 2U) +#define gr_bes_crop_debug3_blendopt_fill_override_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_fill_override_enabled_f() (0x4U) +#define gr_bes_crop_debug4_r() (0x0040894cU) +#define gr_bes_crop_debug4_clamp_fp_blend_m() (U32(0x1U) << 18U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) +#define gr_bes_crop_settings_r() (0x00408958U) +#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) +#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) +#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) +#define gr_zcull_subregion_qty_v() (0x00000010U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r() (0x00504604U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r() (0x00504608U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r() (0x0050465cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r() (0x00504660U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r() (0x00504664U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r() (0x00504668U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r() (0x0050466cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r() (0x00504658U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r() (0x00504730U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r() (0x00504734U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r() (0x00504738U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r() (0x0050473cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r() (0x00504740U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r() (0x00504744U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r() (0x00504748U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r() (0x0050474cU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r() (0x00504678U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r() (0x00504694U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r() (0x005046f0U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r() (0x00504700U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r() (0x005046f4U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r() (0x00504704U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r() (0x005046f8U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r() (0x00504708U) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r() (0x005046fcU) +#define gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r() (0x0050470cU) +#define gr_fe_pwr_mode_r() (0x00404170U) +#define gr_fe_pwr_mode_mode_auto_f() (0x0U) +#define gr_fe_pwr_mode_mode_force_on_f() (0x2U) +#define gr_fe_pwr_mode_req_v(r) (((r) >> 4U) & 0x1U) +#define gr_fe_pwr_mode_req_send_f() (0x10U) +#define gr_fe_pwr_mode_req_done_v() (0x00000000U) +#define gr_gpcs_pri_mmu_ctrl_r() (0x00418880U) +#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() (U32(0x1U) << 0U) +#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() (U32(0x1U) << 11U) +#define gr_gpcs_pri_mmu_ctrl_vol_fault_m() (U32(0x1U) << 1U) +#define gr_gpcs_pri_mmu_ctrl_comp_fault_m() (U32(0x1U) << 2U) +#define gr_gpcs_pri_mmu_ctrl_miss_gran_m() (U32(0x3U) << 3U) +#define gr_gpcs_pri_mmu_ctrl_cache_mode_m() (U32(0x3U) << 5U) +#define gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() (U32(0x3U) << 28U) +#define gr_gpcs_pri_mmu_ctrl_mmu_vol_m() (U32(0x1U) << 30U) +#define gr_gpcs_pri_mmu_ctrl_mmu_disable_m() (U32(0x1U) << 31U) +#define gr_gpcs_pri_mmu_pm_unit_mask_r() (0x00418890U) +#define gr_gpcs_pri_mmu_pm_req_mask_r() (0x00418894U) +#define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define gr_gpcs_pri_mmu_debug_wr_r() (0x004188b4U) +#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) +#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) +#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m() (U32(0x1U) << 3U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m() (U32(0x1U) << 30U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U) +#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) +#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) +#define gr_debug_2_r() (0x00400088U) +#define gr_debug_2_gfxp_wfi_always_injects_wfi_m() (U32(0x1U) << 23U) +#define gr_debug_2_gfxp_wfi_always_injects_wfi_v(r) (((r) >> 23U) & 0x1U) +#define gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f() (0x800000U) +#define gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f() (0x0U) +#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419c84U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ + (((v)&0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_disp_ctrl_r() (0x00419f78U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) +#define gr_gpcs_tc_debug0_r() (0x00418708U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0xffU) << 0U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0xffU) << 0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h index c972dd4fb..1bc8c950b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,484 +59,150 @@ #include #include -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 ltc_ltca_g_axi_pctrl_r(void) -{ - return 0x00160000U; -} -static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) -{ - return (v & 0xffU) << 2U; -} +#define ltc_pltcg_base_v() (0x00140000U) +#define ltc_pltcg_extent_v() (0x0017ffffU) +#define ltc_ltc0_ltss_v() (0x00140200U) +#define ltc_ltc0_lts0_v() (0x00140400U) +#define ltc_ltcs_ltss_v() (0x0017e200U) +#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U) +#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U) +#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U) +#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U) +#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U) +#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU) +#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) +#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) +#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU) +#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) +#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) +#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU) +#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U) +#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U) +#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param2_r() (0x0017e3f4U) +#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) +#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ + (((v)&0x1fU) << 16U) +#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ + (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ + (U32(0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffffffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U) +#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U) +#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U) +#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltcs_ltss_intr_r() (0x0017e20cU) +#define ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() (0x100U) +#define ltc_ltcs_ltss_intr_ecc_ded_error_pending_f() (0x200U) +#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U) +#define ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() (0x1000000U) +#define ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f() (0x2000000U) +#define ltc_ltc0_lts0_intr_r() (0x0014040cU) +#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU) +#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\ + (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\ + (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\ + (0x40000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\ + (((r) >> 16U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U) +#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltc0_lts0_tstg_info_1_r() (0x0014058cU) +#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU) +#define ltc_ltca_g_axi_pctrl_r() (0x00160000U) +#define ltc_ltca_g_axi_pctrl_user_sid_f(v) (((v)&0xffU) << 2U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h index 1d0abe2c0..689f269f5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,200 +59,58 @@ #include #include -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_replayable_fault_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pfb_pending_f(void) -{ - return 0x2000U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020cU; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} +#define mc_boot_0_r() (0x00000000U) +#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU) +#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU) +#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU) +#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU) +#define mc_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_pfifo_pending_f() (0x100U) +#define mc_intr_replayable_fault_pending_f() (0x200U) +#define mc_intr_pfb_pending_f() (0x2000U) +#define mc_intr_pgraph_pending_f() (0x1000U) +#define mc_intr_pmu_pending_f() (0x1000000U) +#define mc_intr_ltc_pending_f() (0x2000000U) +#define mc_intr_priv_ring_pending_f() (0x40000000U) +#define mc_intr_pbus_pending_f() (0x10000000U) +#define mc_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_clear_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_enable_r() (0x00000200U) +#define mc_enable_xbar_enabled_f() (0x4U) +#define mc_enable_l2_enabled_f() (0x8U) +#define mc_enable_pmedia_s() (1U) +#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) +#define mc_enable_pmedia_m() (U32(0x1U) << 4U) +#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) +#define mc_enable_priv_ring_enabled_f() (0x20U) +#define mc_enable_ce0_m() (U32(0x1U) << 6U) +#define mc_enable_pfifo_enabled_f() (0x100U) +#define mc_enable_pgraph_enabled_f() (0x1000U) +#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U) +#define mc_enable_pwr_disabled_v() (0x00000000U) +#define mc_enable_pwr_enabled_f() (0x2000U) +#define mc_enable_pfb_enabled_f() (0x100000U) +#define mc_enable_ce2_m() (U32(0x1U) << 21U) +#define mc_enable_ce2_enabled_f() (0x200000U) +#define mc_enable_blg_enabled_f() (0x8000000U) +#define mc_enable_perfmon_enabled_f() (0x10000000U) +#define mc_enable_hub_enabled_f() (0x20000000U) +#define mc_intr_ltc_r() (0x000001c0U) +#define mc_enable_pb_r() (0x00000204U) +#define mc_enable_pb_0_s() (1U) +#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) +#define mc_enable_pb_0_m() (U32(0x1U) << 0U) +#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) +#define mc_enable_pb_0_enabled_v() (0x00000001U) +#define mc_enable_pb_sel_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define mc_elpg_enable_r() (0x0000020cU) +#define mc_elpg_enable_xbar_enabled_f() (0x4U) +#define mc_elpg_enable_pfb_enabled_f() (0x100000U) +#define mc_elpg_enable_hub_enabled_f() (0x20000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h index ee5a33589..716a80d63 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,576 +59,189 @@ #include #include -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_timeout_period_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method3_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_data0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_allowed_syncpoints_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) -{ - return (v & 0x7fffU) << 16U; -} -static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) -{ - return (r >> 16U) & 0x7fffU; -} -static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000U; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001U; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} +#define pbdma_gp_entry1_r() (0x10000004U) +#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) +#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) +#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) +#define pbdma_gp_base_r(i)\ + (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base__size_1_v() (0x00000001U) +#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) +#define pbdma_gp_base_rsvd_s() (3U) +#define pbdma_gp_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) +#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) +#define pbdma_gp_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_get_r(i)\ + (nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_put_r(i)\ + (nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout_r(i)\ + (nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout__size_1_v() (0x00000001U) +#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U) +#define pbdma_timeout_period_max_f() (0xffffffffU) +#define pbdma_pb_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_r(i)\ + (nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_r(i)\ + (nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_r(i)\ + (nvgpu_safe_add_u32(0x0004009cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_formats_gp_fermi0_f() (0x0U) +#define pbdma_formats_pb_fermi1_f() (0x100U) +#define pbdma_formats_mp_fermi0_f() (0x0U) +#define pbdma_pb_header_r(i)\ + (nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_priv_user_f() (0x0U) +#define pbdma_pb_header_method_zero_f() (0x0U) +#define pbdma_pb_header_subchannel_zero_f() (0x0U) +#define pbdma_pb_header_level_main_f() (0x0U) +#define pbdma_pb_header_first_true_f() (0x400000U) +#define pbdma_pb_header_type_inc_f() (0x20000000U) +#define pbdma_pb_header_type_non_inc_f() (0x60000000U) +#define pbdma_hdr_shadow_r(i)\ + (nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_0_r(i)\ + (nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_1_r(i)\ + (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_r(i)\ + (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) +#define pbdma_subdevice_status_active_f() (0x10000000U) +#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) +#define pbdma_method0_r(i)\ + (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method0_fifo_size_v() (0x00000004U) +#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) +#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) +#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) +#define pbdma_method0_first_true_f() (0x400000U) +#define pbdma_method0_valid_true_f() (0x80000000U) +#define pbdma_method1_r(i)\ + (nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method2_r(i)\ + (nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method3_r(i)\ + (nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_data0_r(i)\ + (nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_r(i)\ + (nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_engine_sw_f() (0x1fU) +#define pbdma_acquire_r(i)\ + (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_retry_man_2_f() (0x2U) +#define pbdma_acquire_retry_exp_2_f() (0x100U) +#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) +#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) +#define pbdma_acquire_timeout_exp_max_f() (0x7800U) +#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) +#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) +#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) +#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) +#define pbdma_acquire_timeout_en_disable_f() (0x0U) +#define pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_channel_r(i)\ + (nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_r(i)\ + (nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_hw_valid_f() (0xfaceU) +#define pbdma_signature_sw_zero_f() (0x0U) +#define pbdma_userd_r(i)\ + (nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_target_vid_mem_f() (0x0U) +#define pbdma_userd_target_sys_mem_coh_f() (0x2U) +#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) +#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) +#define pbdma_userd_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) +#define pbdma_config_r(i)\ + (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_config_auth_level_privileged_f() (0x100U) +#define pbdma_hce_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) +#define pbdma_intr_0_r(i)\ + (nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_intr_0_memreq_pending_f() (0x1U) +#define pbdma_intr_0_memack_timeout_pending_f() (0x2U) +#define pbdma_intr_0_memack_extra_pending_f() (0x4U) +#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U) +#define pbdma_intr_0_memdat_extra_pending_f() (0x10U) +#define pbdma_intr_0_memflush_pending_f() (0x20U) +#define pbdma_intr_0_memop_pending_f() (0x40U) +#define pbdma_intr_0_lbconnect_pending_f() (0x80U) +#define pbdma_intr_0_lbreq_pending_f() (0x100U) +#define pbdma_intr_0_lback_timeout_pending_f() (0x200U) +#define pbdma_intr_0_lback_extra_pending_f() (0x400U) +#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U) +#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U) +#define pbdma_intr_0_gpfifo_pending_f() (0x2000U) +#define pbdma_intr_0_gpptr_pending_f() (0x4000U) +#define pbdma_intr_0_gpentry_pending_f() (0x8000U) +#define pbdma_intr_0_gpcrc_pending_f() (0x10000U) +#define pbdma_intr_0_pbptr_pending_f() (0x20000U) +#define pbdma_intr_0_pbentry_pending_f() (0x40000U) +#define pbdma_intr_0_pbcrc_pending_f() (0x80000U) +#define pbdma_intr_0_xbarconnect_pending_f() (0x100000U) +#define pbdma_intr_0_method_pending_f() (0x200000U) +#define pbdma_intr_0_methodcrc_pending_f() (0x400000U) +#define pbdma_intr_0_device_pending_f() (0x800000U) +#define pbdma_intr_0_semaphore_pending_f() (0x2000000U) +#define pbdma_intr_0_acquire_pending_f() (0x4000000U) +#define pbdma_intr_0_pri_pending_f() (0x8000000U) +#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U) +#define pbdma_intr_0_pbseg_pending_f() (0x40000000U) +#define pbdma_intr_0_signature_pending_f() (0x80000000U) +#define pbdma_intr_0_syncpoint_illegal_pending_f() (0x10000000U) +#define pbdma_intr_1_r(i)\ + (nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_r(i)\ + (nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U) +#define pbdma_intr_en_1_r(i)\ + (nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_r(i)\ + (nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_lbreq_enabled_f() (0x100U) +#define pbdma_intr_stall_1_r(i)\ + (nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U) +#define pbdma_udma_nop_r() (0x00000008U) +#define pbdma_allowed_syncpoints_r(i)\ + (nvgpu_safe_add_u32(0x000400e8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_allowed_syncpoints_0_valid_f(v) (((v)&0x1U) << 31U) +#define pbdma_allowed_syncpoints_0_index_f(v) (((v)&0x7fffU) << 16U) +#define pbdma_allowed_syncpoints_0_index_v(r) (((r) >> 16U) & 0x7fffU) +#define pbdma_allowed_syncpoints_1_valid_f(v) (((v)&0x1U) << 15U) +#define pbdma_allowed_syncpoints_1_index_f(v) (((v)&0x7fffU) << 0U) +#define pbdma_syncpointa_r(i)\ + (nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU) +#define pbdma_syncpointb_r(i)\ + (nvgpu_safe_add_u32(0x000400a8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_syncpointb_op_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_syncpointb_op_wait_v() (0x00000000U) +#define pbdma_syncpointb_wait_switch_v(r) (((r) >> 4U) & 0x1U) +#define pbdma_syncpointb_wait_switch_en_v() (0x00000001U) +#define pbdma_syncpointb_syncpt_index_v(r) (((r) >> 8U) & 0xfffU) +#define pbdma_runlist_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_runlist_timeslice_timeout_128_f() (0x80U) +#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U) +#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h index 6566c4403..38d25b27e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,164 +59,44 @@ #include #include -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x001b0000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x001b0fffU; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} +#define perf_pmmsys_base_v() (0x001b0000U) +#define perf_pmmsys_extent_v() (0x001b0fffU) +#define perf_pmasys_control_r() (0x001b4000U) +#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) +#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) +#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) +#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) +#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) +#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) +#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_mem_block_r() (0x001b4070U) +#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) +#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) +#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) +#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) +#define perf_pmasys_mem_block_target_lfb_f() (0x0U) +#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U) +#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) +#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) +#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) +#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) +#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) +#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) +#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) +#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) +#define perf_pmasys_mem_block_valid_false_f() (0x0U) +#define perf_pmasys_outbase_r() (0x001b4074U) +#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_outbaseupper_r() (0x001b4078U) +#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) +#define perf_pmasys_outsize_r() (0x001b407cU) +#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_mem_bytes_r() (0x001b4084U) +#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_mem_bump_r() (0x001b4088U) +#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_enginestatus_r() (0x001b40a4U) +#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) +#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) +#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h index 1fbaff923..319f5fd95 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pram_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pram_data032_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U)); -} +#define pram_data032_r(i)\ + (nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h index 6e2059c94..7d3fd6446 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,112 +59,33 @@ #include #include -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} +#define pri_ringmaster_command_r() (0x0012004cU) +#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U) +#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU) +#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U) +#define pri_ringmaster_command_cmd_start_ring_f() (0x1U) +#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U) +#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U) +#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U) +#define pri_ringmaster_command_data_r() (0x00120048U) +#define pri_ringmaster_start_results_r() (0x00120050U) +#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U) +#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U) +#define pri_ringmaster_intr_status0_r() (0x00120058U) +#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\ + (((r) >> 0U) & 0x1U) +#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U) +#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U) +#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\ + (((r) >> 8U) & 0x1U) +#define pri_ringmaster_intr_status1_r() (0x0012005cU) +#define pri_ringmaster_global_ctl_r() (0x00120060U) +#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U) +#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U) +#define pri_ringmaster_enum_fbp_r() (0x00120074U) +#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_gpc_r() (0x00120078U) +#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_ltc_r() (0x0012006cU) +#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h index 12b62fc28..7b1eb7e69 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,14 @@ #include #include -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_subid_v(u32 r) -{ - return (r >> 24U) & 0x3fU; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(u32 r) -{ - return (r >> 20U) & 0x3U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} +#define pri_ringstation_gpc_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U) +#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) +#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) +#define pri_ringstation_gpc_gpc0_priv_error_info_subid_v(r)\ + (((r) >> 24U) & 0x3fU) +#define pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(r)\ + (((r) >> 20U) & 0x3U) +#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h index 01e5d4914..5fd94c66c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,44 +59,17 @@ #include #include -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_info_subid_v(u32 r) -{ - return (r >> 24U) & 0x3fU; -} -static inline u32 pri_ringstation_sys_priv_error_info_priv_level_v(u32 r) -{ - return (r >> 20U) & 0x3U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} +#define pri_ringstation_sys_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_sys_decode_config_r() (0x00122204U) +#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U) +#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\ + (0x1U) +#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U) +#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) +#define pri_ringstation_sys_priv_error_info_r() (0x00122128U) +#define pri_ringstation_sys_priv_error_info_subid_v(r) (((r) >> 24U) & 0x3fU) +#define pri_ringstation_sys_priv_error_info_priv_level_v(r)\ + (((r) >> 20U) & 0x3U) +#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h index d3ad6f95c..7a69f8069 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_proj_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,124 +59,34 @@ #include #include -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} +#define proj_gpc_base_v() (0x00500000U) +#define proj_gpc_shared_base_v() (0x00418000U) +#define proj_gpc_stride_v() (0x00008000U) +#define proj_gpc_priv_stride_v() (0x00000800U) +#define proj_ltc_stride_v() (0x00002000U) +#define proj_lts_stride_v() (0x00000200U) +#define proj_fbpa_base_v() (0x00900000U) +#define proj_fbpa_shared_base_v() (0x009a0000U) +#define proj_fbpa_stride_v() (0x00004000U) +#define proj_ppc_in_gpc_base_v() (0x00003000U) +#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U) +#define proj_ppc_in_gpc_stride_v() (0x00000200U) +#define proj_rop_base_v() (0x00410000U) +#define proj_rop_shared_base_v() (0x00408800U) +#define proj_rop_stride_v() (0x00000400U) +#define proj_tpc_in_gpc_base_v() (0x00004000U) +#define proj_tpc_in_gpc_stride_v() (0x00000800U) +#define proj_tpc_in_gpc_shared_base_v() (0x00001800U) +#define proj_host_num_engines_v() (0x00000002U) +#define proj_host_num_pbdma_v() (0x00000001U) +#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000002U) +#define proj_scal_litter_num_sm_per_tpc_v() (0x00000001U) +#define proj_scal_litter_num_fbps_v() (0x00000001U) +#define proj_scal_litter_num_fbpas_v() (0x00000001U) +#define proj_scal_litter_num_gpcs_v() (0x00000001U) +#define proj_scal_litter_num_pes_per_gpc_v() (0x00000001U) +#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U) +#define proj_scal_litter_num_zcull_banks_v() (0x00000004U) +#define proj_scal_max_gpcs_v() (0x00000020U) +#define proj_scal_max_tpc_per_gpc_v() (0x00000008U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h index eff461f59..16e1952bd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,852 +59,238 @@ #include #include -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_host_error_r(void) -{ - return 0x0010a990U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} +#define pwr_falcon_irqsset_r() (0x0010a000U) +#define pwr_falcon_irqsset_swgen0_set_f() (0x40U) +#define pwr_falcon_irqsclr_r() (0x0010a004U) +#define pwr_falcon_irqstat_r() (0x0010a008U) +#define pwr_falcon_irqstat_halt_true_f() (0x10U) +#define pwr_falcon_irqstat_exterr_true_f() (0x20U) +#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) +#define pwr_falcon_irqmode_r() (0x0010a00cU) +#define pwr_falcon_irqmset_r() (0x0010a010U) +#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_r() (0x0010a014U) +#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmask_r() (0x0010a018U) +#define pwr_falcon_irqdest_r() (0x0010a01cU) +#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pwr_falcon_curctx_r() (0x0010a050U) +#define pwr_falcon_nxtctx_r() (0x0010a054U) +#define pwr_falcon_mailbox0_r() (0x0010a040U) +#define pwr_falcon_mailbox1_r() (0x0010a044U) +#define pwr_falcon_itfen_r() (0x0010a048U) +#define pwr_falcon_itfen_ctxen_enable_f() (0x1U) +#define pwr_falcon_idlestate_r() (0x0010a04cU) +#define pwr_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pwr_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pwr_falcon_os_r() (0x0010a080U) +#define pwr_falcon_engctl_r() (0x0010a0a4U) +#define pwr_falcon_cpuctl_r() (0x0010a100U) +#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) +#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) +#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) +#define pwr_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_sctl_r() (0x0010a240U) +#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pwr_falcon_bootvec_r() (0x0010a104U) +#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_falcon_dmactl_r() (0x0010a10cU) +#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pwr_falcon_hwcfg_r() (0x0010a108U) +#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pwr_falcon_dmatrfbase_r() (0x0010a110U) +#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) +#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) +#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) +#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) +#define pwr_falcon_exterraddr_r() (0x0010a168U) +#define pwr_falcon_exterrstat_r() (0x0010a16cU) +#define pwr_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pwr_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) +#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) +#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) +#define pwr_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_new_instblk_r() (0x0010a480U) +#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define pwr_pmu_new_instblk_target_fb_f() (0x0U) +#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) +#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) +#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) +#define pwr_pmu_mutex_id_r() (0x0010a488U) +#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) +#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) +#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) +#define pwr_pmu_mutex_r(i)\ + (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mutex__size_1_v() (0x00000010U) +#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) +#define pwr_pmu_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_head__size_1_v() (0x00000004U) +#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) +#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_head_r() (0x0010a4c8U) +#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) +#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_idle_mask_r(i)\ + (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U) +#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) +#define pwr_pmu_idle_count_r(i)\ + (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) +#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_idle_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) +#define pwr_pmu_idle_ctrl_value_busy_f() (0x2U) +#define pwr_pmu_idle_ctrl_value_always_f() (0x3U) +#define pwr_pmu_idle_ctrl_filter_m() (U32(0x1U) << 2U) +#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) +#define pwr_pmu_idle_threshold_r(i)\ + (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_intr_r() (0x0010a9e8U) +#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) +#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) +#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) +#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_intr_clear_v() (0x00000001U) +#define pwr_pmu_idle_mask_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_mask_1_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_ctrl_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_debug_r(i)\ + (nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_debug__size_1_v() (0x00000004U) +#define pwr_pmu_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mailbox__size_1_v() (0x0000000cU) +#define pwr_pmu_bar0_addr_r() (0x0010a7a0U) +#define pwr_pmu_bar0_data_r() (0x0010a7a4U) +#define pwr_pmu_bar0_ctl_r() (0x0010a7acU) +#define pwr_pmu_bar0_timeout_r() (0x0010a7a8U) +#define pwr_pmu_bar0_fecs_error_r() (0x0010a988U) +#define pwr_pmu_bar0_host_error_r() (0x0010a990U) +#define pwr_pmu_bar0_error_status_r() (0x0010a7b0U) +#define pwr_pmu_bar0_error_status_timeout_host_m() (U32(0x1U) << 0U) +#define pwr_pmu_bar0_error_status_timeout_fecs_m() (U32(0x1U) << 1U) +#define pwr_pmu_bar0_error_status_cmd_hwerr_m() (U32(0x1U) << 2U) +#define pwr_pmu_bar0_error_status_err_cmd_m() (U32(0x1U) << 3U) +#define pwr_pmu_bar0_error_status_hosterr_m() (U32(0x1U) << 30U) +#define pwr_pmu_bar0_error_status_fecserr_m() (U32(0x1U) << 31U) +#define pwr_pmu_pg_idlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_ppuidlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_idle_cnt_r(i)\ + (nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_intren_r(i)\ + (nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_target_local_fb_f() (0x0U) +#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pwr_fbif_transcfg_mem_type_s() (1U) +#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pwr_fbif_transcfg_mem_type_physical_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h index 210496338..b95da2074 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,468 +59,120 @@ #include #include -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130U; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14U; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15U; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16U; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39U; -} -static inline u32 ram_fc_allowed_syncpoints_w(void) -{ - return 58U; -} -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41U; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0U; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000U; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 14U; -} -static inline u32 ram_rl_entry_timeslice_scale_v(u32 r) -{ - return (r >> 14U) & 0xfU; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000U; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 18U; -} -static inline u32 ram_rl_entry_timeslice_timeout_v(u32 r) -{ - return (r >> 18U) & 0xffU; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3fU) << 26U; -} +#define ram_in_ramfc_s() (4096U) +#define ram_in_ramfc_w() (0U) +#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_page_dir_base_target_w() (128U) +#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) +#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) +#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) +#define ram_in_page_dir_base_vol_w() (128U) +#define ram_in_page_dir_base_vol_true_f() (0x4U) +#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_w() (128U) +#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) +#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) +#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) +#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) +#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) +#define ram_in_use_ver2_pt_format_w() (128U) +#define ram_in_use_ver2_pt_format_true_f() (0x400U) +#define ram_in_use_ver2_pt_format_false_f() (0x0U) +#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) +#define ram_in_big_page_size_m() (U32(0x1U) << 11U) +#define ram_in_big_page_size_w() (128U) +#define ram_in_big_page_size_128kb_f() (0x0U) +#define ram_in_big_page_size_64kb_f() (0x800U) +#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_page_dir_base_lo_w() (128U) +#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_page_dir_base_hi_w() (129U) +#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_adr_limit_lo_w() (130U) +#define ram_in_adr_limit_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_adr_limit_hi_w() (131U) +#define ram_in_engine_cs_w() (132U) +#define ram_in_engine_cs_wfi_v() (0x00000000U) +#define ram_in_engine_cs_wfi_f() (0x0U) +#define ram_in_engine_cs_fg_v() (0x00000001U) +#define ram_in_engine_cs_fg_f() (0x8U) +#define ram_in_gr_cs_w() (132U) +#define ram_in_gr_cs_wfi_f() (0x0U) +#define ram_in_gr_wfi_target_w() (132U) +#define ram_in_gr_wfi_mode_w() (132U) +#define ram_in_gr_wfi_mode_physical_v() (0x00000000U) +#define ram_in_gr_wfi_mode_physical_f() (0x0U) +#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) +#define ram_in_gr_wfi_mode_virtual_f() (0x4U) +#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_gr_wfi_ptr_lo_w() (132U) +#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_gr_wfi_ptr_hi_w() (133U) +#define ram_in_base_shift_v() (0x0000000cU) +#define ram_in_alloc_size_v() (0x00001000U) +#define ram_fc_size_val_v() (0x00000200U) +#define ram_fc_gp_put_w() (0U) +#define ram_fc_userd_w() (2U) +#define ram_fc_userd_hi_w() (3U) +#define ram_fc_signature_w() (4U) +#define ram_fc_gp_get_w() (5U) +#define ram_fc_pb_get_w() (6U) +#define ram_fc_pb_get_hi_w() (7U) +#define ram_fc_pb_top_level_get_w() (8U) +#define ram_fc_pb_top_level_get_hi_w() (9U) +#define ram_fc_acquire_w() (12U) +#define ram_fc_semaphorea_w() (14U) +#define ram_fc_semaphoreb_w() (15U) +#define ram_fc_semaphorec_w() (16U) +#define ram_fc_semaphored_w() (17U) +#define ram_fc_gp_base_w() (18U) +#define ram_fc_gp_base_hi_w() (19U) +#define ram_fc_gp_fetch_w() (20U) +#define ram_fc_pb_fetch_w() (21U) +#define ram_fc_pb_fetch_hi_w() (22U) +#define ram_fc_pb_put_w() (23U) +#define ram_fc_pb_put_hi_w() (24U) +#define ram_fc_pb_header_w() (33U) +#define ram_fc_pb_count_w() (34U) +#define ram_fc_subdevice_w() (37U) +#define ram_fc_formats_w() (39U) +#define ram_fc_allowed_syncpoints_w() (58U) +#define ram_fc_syncpointa_w() (41U) +#define ram_fc_syncpointb_w() (42U) +#define ram_fc_target_w() (43U) +#define ram_fc_hce_ctrl_w() (57U) +#define ram_fc_chid_w() (58U) +#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) +#define ram_fc_chid_id_w() (0U) +#define ram_fc_config_w() (61U) +#define ram_fc_runlist_timeslice_w() (62U) +#define ram_userd_base_shift_v() (0x00000009U) +#define ram_userd_chan_size_v() (0x00000200U) +#define ram_userd_put_w() (16U) +#define ram_userd_get_w() (17U) +#define ram_userd_ref_w() (18U) +#define ram_userd_put_hi_w() (19U) +#define ram_userd_top_level_get_w() (22U) +#define ram_userd_top_level_get_hi_w() (23U) +#define ram_userd_get_hi_w() (24U) +#define ram_userd_gp_get_w() (34U) +#define ram_userd_gp_put_w() (35U) +#define ram_userd_gp_top_level_get_w() (22U) +#define ram_userd_gp_top_level_get_hi_w() (23U) +#define ram_rl_entry_size_v() (0x00000008U) +#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) +#define ram_rl_entry_type_chid_f() (0x0U) +#define ram_rl_entry_type_tsg_f() (0x2000U) +#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) +#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) +#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) +#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) +#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) +#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) +#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h index 497b77c85..736c42357 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,360 +59,97 @@ #include #include -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return U32(0x3U) << 4U; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return U32(0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return U32(0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return U32(0xfU) << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return U32(0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return U32(0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return U32(0x3fU) << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} +#define therm_use_a_r() (0x00020798U) +#define therm_use_a_ext_therm_0_enable_f() (0x1U) +#define therm_use_a_ext_therm_1_enable_f() (0x2U) +#define therm_use_a_ext_therm_2_enable_f() (0x4U) +#define therm_evt_ext_therm_0_r() (0x00020700U) +#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 24U) +#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000001U) +#define therm_evt_ext_therm_0_mode_f(v) (((v)&0x3U) << 30U) +#define therm_evt_ext_therm_0_mode_normal_v() (0x00000000U) +#define therm_evt_ext_therm_0_mode_inverted_v() (0x00000001U) +#define therm_evt_ext_therm_0_mode_forced_v() (0x00000002U) +#define therm_evt_ext_therm_0_mode_cleared_v() (0x00000003U) +#define therm_evt_ext_therm_1_r() (0x00020704U) +#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 24U) +#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000002U) +#define therm_evt_ext_therm_1_mode_f(v) (((v)&0x3U) << 30U) +#define therm_evt_ext_therm_1_mode_normal_v() (0x00000000U) +#define therm_evt_ext_therm_1_mode_inverted_v() (0x00000001U) +#define therm_evt_ext_therm_1_mode_forced_v() (0x00000002U) +#define therm_evt_ext_therm_1_mode_cleared_v() (0x00000003U) +#define therm_evt_ext_therm_2_r() (0x00020708U) +#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 24U) +#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000003U) +#define therm_evt_ext_therm_2_mode_f(v) (((v)&0x3U) << 30U) +#define therm_evt_ext_therm_2_mode_normal_v() (0x00000000U) +#define therm_evt_ext_therm_2_mode_inverted_v() (0x00000001U) +#define therm_evt_ext_therm_2_mode_forced_v() (0x00000002U) +#define therm_evt_ext_therm_2_mode_cleared_v() (0x00000003U) +#define therm_weight_1_r() (0x00020024U) +#define therm_config1_r() (0x00020050U) +#define therm_config2_r() (0x00020130U) +#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) +#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) +#define therm_gate_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) +#define therm_gate_ctrl_eng_clk_run_f() (0x0U) +#define therm_gate_ctrl_eng_clk_auto_f() (0x1U) +#define therm_gate_ctrl_eng_clk_stop_f() (0x2U) +#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) +#define therm_gate_ctrl_blk_clk_run_f() (0x0U) +#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) +#define therm_gate_ctrl_eng_pwr_m() (U32(0x3U) << 4U) +#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U) +#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U) +#define therm_gate_ctrl_eng_pwr_off_f() (0x20U) +#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) +#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) +#define therm_fecs_idle_filter_r() (0x00020288U) +#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_hubmmu_idle_filter_r() (0x0002028cU) +#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_clk_slowdown_r(i)\ + (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) +#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) +#define therm_grad_stepping_table_r(i)\ + (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) +#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) +#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) +#define therm_grad_stepping0_r() (0x000202c0U) +#define therm_grad_stepping0_feature_s() (1U) +#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) +#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) +#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) +#define therm_grad_stepping0_feature_enable_f() (0x1U) +#define therm_grad_stepping1_r() (0x000202c4U) +#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) +#define therm_clk_timing_r(i)\ + (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h index 0047ce706..310bdc36a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,72 +59,21 @@ #include #include -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} +#define timer_pri_timeout_r() (0x00009080U) +#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) +#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) +#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) +#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) +#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) +#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) +#define timer_pri_timeout_en_en_disabled_f() (0x0U) +#define timer_pri_timeout_save_0_r() (0x00009084U) +#define timer_pri_timeout_save_0_fecs_tgt_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_save_0_addr_v(r) (((r) >> 2U) & 0x3fffffU) +#define timer_pri_timeout_save_0_write_v(r) (((r) >> 1U) & 0x1U) +#define timer_pri_timeout_save_1_r() (0x00009088U) +#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU) +#define timer_time_0_r() (0x00009400U) +#define timer_time_1_r() (0x00009410U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h index d29c57785..92c904f45 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_top_gp10b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,196 +59,53 @@ #include #include -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_device_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_chain_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_engine_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_runlist_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_intr_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_reset_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x1fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} +#define top_num_gpcs_r() (0x00022430U) +#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_tpc_per_gpc_r() (0x00022434U) +#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbps_r() (0x00022438U) +#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_ltc_per_fbp_r() (0x00022450U) +#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_slices_per_ltc_r() (0x0002245cU) +#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_ltcs_r() (0x00022454U) +#define top_device_info_r(i)\ + (nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U))) +#define top_device_info__size_1_v() (0x00000040U) +#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U) +#define top_device_info_chain_enable_v() (0x00000001U) +#define top_device_info_chain_disable_v() (0x00000000U) +#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU) +#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU) +#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU) +#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU) +#define top_device_info_type_enum_graphics_v() (0x00000000U) +#define top_device_info_type_enum_graphics_f() (0x0U) +#define top_device_info_type_enum_copy2_v() (0x00000003U) +#define top_device_info_type_enum_copy2_f() (0xcU) +#define top_device_info_type_enum_lce_v() (0x00000013U) +#define top_device_info_type_enum_lce_f() (0x4cU) +#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U) +#define top_device_info_engine_valid_v() (0x00000001U) +#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U) +#define top_device_info_runlist_valid_v() (0x00000001U) +#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U) +#define top_device_info_intr_valid_v() (0x00000001U) +#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_reset_valid_v() (0x00000001U) +#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) +#define top_device_info_entry_not_valid_v() (0x00000000U) +#define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_engine_type_v() (0x00000003U) +#define top_device_info_entry_data_v() (0x00000001U) +#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U) +#define top_device_info_data_type_enum2_v() (0x00000000U) +#define top_device_info_data_inst_id_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0xfffU) +#define top_device_info_data_pri_base_align_v() (0x0000000cU) +#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x1fU) +#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_data_fault_id_valid_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index 71261e8b2..d6c3acb0f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,188 +59,51 @@ #include #include -static inline u32 bus_sw_scratch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} +#define bus_sw_scratch_r(i)\ + (nvgpu_safe_add_u32(0x00001580U, nvgpu_safe_mult_u32((i), 4U))) +#define bus_bar0_window_r() (0x00001700U) +#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) +#define bus_bar0_window_target_vid_mem_f() (0x0U) +#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) +#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) +#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) +#define bus_bar1_block_r() (0x00001704U) +#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar1_block_target_vid_mem_f() (0x0U) +#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar1_block_mode_virtual_f() (0x80000000U) +#define bus_bar2_block_r() (0x00001714U) +#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar2_block_target_vid_mem_f() (0x0U) +#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar2_block_mode_virtual_f() (0x80000000U) +#define bus_bar1_block_ptr_shift_v() (0x0000000cU) +#define bus_bar2_block_ptr_shift_v() (0x0000000cU) +#define bus_bind_status_r() (0x00001710U) +#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U) +#define bus_bind_status_bar1_pending_empty_f() (0x0U) +#define bus_bind_status_bar1_pending_busy_f() (0x1U) +#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define bus_bind_status_bar1_outstanding_false_f() (0x0U) +#define bus_bind_status_bar1_outstanding_true_f() (0x2U) +#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U) +#define bus_bind_status_bar2_pending_empty_v() (0x00000000U) +#define bus_bind_status_bar2_pending_empty_f() (0x0U) +#define bus_bind_status_bar2_pending_busy_v() (0x00000001U) +#define bus_bind_status_bar2_pending_busy_f() (0x4U) +#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U) +#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U) +#define bus_bind_status_bar2_outstanding_false_f() (0x0U) +#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U) +#define bus_bind_status_bar2_outstanding_true_f() (0x8U) +#define bus_intr_0_r() (0x00001100U) +#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U) +#define bus_intr_en_0_r() (0x00001140U) +#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index a637d5dbc..d9f24628d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,172 +59,48 @@ #include #include -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_in_use_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 ccsr_channel_status_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acquire_v(void) -{ - return 0x00000003U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_v(void) -{ - return 0x00000005U; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void) -{ - return 0x00000006U; -} -static inline u32 ccsr_channel_status_on_eng_v(void) -{ - return 0x00000007U; -} -static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void) -{ - return 0x00000008U; -} -static inline u32 ccsr_channel_status_on_eng_pending_v(void) -{ - return 0x00000009U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) -{ - return 0x400000U; -} -static inline u32 ccsr_channel_eng_faulted_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 ccsr_channel_eng_faulted_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 ccsr_channel_eng_faulted_reset_f(void) -{ - return 0x800000U; -} -static inline u32 ccsr_channel_eng_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ccsr_channel_busy_true_v(void) -{ - return 0x00000001U; -} +#define ccsr_channel_inst_r(i)\ + (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel_inst__size_1_v() (0x00001000U) +#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define ccsr_channel_inst_target_vid_mem_f() (0x0U) +#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) +#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) +#define ccsr_channel_inst_bind_false_f() (0x0U) +#define ccsr_channel_inst_bind_true_f() (0x80000000U) +#define ccsr_channel_r(i)\ + (nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel__size_1_v() (0x00001000U) +#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) +#define ccsr_channel_enable_in_use_v() (0x00000001U) +#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) +#define ccsr_channel_enable_set_true_f() (0x400U) +#define ccsr_channel_enable_clr_true_f() (0x800U) +#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) +#define ccsr_channel_status_idle_v() (0x00000000U) +#define ccsr_channel_status_pending_v() (0x00000001U) +#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U) +#define ccsr_channel_status_pending_acquire_v() (0x00000003U) +#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U) +#define ccsr_channel_status_on_pbdma_v() (0x00000005U) +#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U) +#define ccsr_channel_status_on_eng_v() (0x00000007U) +#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U) +#define ccsr_channel_status_on_eng_pending_v() (0x00000009U) +#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU) +#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU) +#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU) +#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU) +#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU) +#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) +#define ccsr_channel_next_true_v() (0x00000001U) +#define ccsr_channel_force_ctx_reload_true_f() (0x100U) +#define ccsr_channel_pbdma_faulted_f(v) (((v)&0x1U) << 22U) +#define ccsr_channel_pbdma_faulted_reset_f() (0x400000U) +#define ccsr_channel_eng_faulted_f(v) (((v)&0x1U) << 23U) +#define ccsr_channel_eng_faulted_v(r) (((r) >> 23U) & 0x1U) +#define ccsr_channel_eng_faulted_reset_f() (0x800000U) +#define ccsr_channel_eng_faulted_true_v() (0x00000001U) +#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U) +#define ccsr_channel_busy_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h index d3cc621c0..cf40fd16c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,52 +59,17 @@ #include #include -static inline u32 ce_intr_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32(i, 128U)); -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_invalid_config_pending_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_invalid_config_reset_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) -{ - return 0x10U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) -{ - return 0x10U; -} -static inline u32 ce_pce_map_r(void) -{ - return 0x00104028U; -} +#define ce_intr_status_r(i)\ + (nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U))) +#define ce_intr_status_blockpipe_pending_f() (0x1U) +#define ce_intr_status_blockpipe_reset_f() (0x1U) +#define ce_intr_status_nonblockpipe_pending_f() (0x2U) +#define ce_intr_status_nonblockpipe_reset_f() (0x2U) +#define ce_intr_status_launcherr_pending_f() (0x4U) +#define ce_intr_status_launcherr_reset_f() (0x4U) +#define ce_intr_status_invalid_config_pending_f() (0x8U) +#define ce_intr_status_invalid_config_reset_f() (0x8U) +#define ce_intr_status_mthd_buffer_fault_pending_f() (0x10U) +#define ce_intr_status_mthd_buffer_fault_reset_f() (0x10U) +#define ce_pce_map_r() (0x00104028U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h index 7ccf15ff8..647bdb4f9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,412 +59,123 @@ #include #include -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_gpccs_header_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) -{ - return 0x00000011U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) -{ - return 0x00000012U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) -{ - return 0x00000021U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) -{ - return 0x00000094U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) -{ - return 0x00000064U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) -{ - return 0x00000074U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) -{ - return 0x00000078U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) -{ - return 0x0000007cU; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) -{ - return 0x000000b8U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) -{ - return 0x000000bcU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) -{ - return 0x000000c0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) -{ - return 0x000000c4U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) -{ - return 0x000000c8U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) -{ - return 0x000000ccU; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) -{ - return 0x000000e0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) -{ - return 0x000000e4U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} +#define ctxsw_prog_fecs_header_v() (0x00000100U) +#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) +#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) +#define ctxsw_prog_main_image_ctl_o() (0x0000000cU) +#define ctxsw_prog_main_image_ctl_type_f(v) (((v)&0x3fU) << 0U) +#define ctxsw_prog_main_image_ctl_type_undefined_v() (0x00000000U) +#define ctxsw_prog_main_image_ctl_type_opengl_v() (0x00000008U) +#define ctxsw_prog_main_image_ctl_type_dx9_v() (0x00000010U) +#define ctxsw_prog_main_image_ctl_type_dx10_v() (0x00000011U) +#define ctxsw_prog_main_image_ctl_type_dx11_v() (0x00000012U) +#define ctxsw_prog_main_image_ctl_type_compute_v() (0x00000020U) +#define ctxsw_prog_main_image_ctl_type_per_veid_header_v() (0x00000021U) +#define ctxsw_prog_main_image_patch_count_o() (0x00000010U) +#define ctxsw_prog_main_image_context_id_o() (0x000000f0U) +#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U) +#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U) +#define ctxsw_prog_main_image_zcull_o() (0x0000001cU) +#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U) +#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U) +#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U) +#define ctxsw_prog_main_image_pm_o() (0x00000028U) +#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U) +#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U) +#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f() (0x2U) +#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) +#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) +#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) +#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) +#define ctxsw_prog_main_image_num_wfi_save_ops_o() (0x000000d0U) +#define ctxsw_prog_main_image_num_cta_save_ops_o() (0x000000d4U) +#define ctxsw_prog_main_image_num_gfxp_save_ops_o() (0x000000d8U) +#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU) +#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) +#define ctxsw_prog_main_image_zcull_ptr_hi_o() (0x00000060U) +#define ctxsw_prog_main_image_zcull_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_pm_ptr_hi_o() (0x00000094U) +#define ctxsw_prog_main_image_full_preemption_ptr_hi_o() (0x00000064U) +#define ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) +#define ctxsw_prog_main_image_full_preemption_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o() (0x00000070U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_o() (0x00000074U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_context_buffer_ptr_hi_o() (0x00000078U) +#define ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_context_buffer_ptr_o() (0x0000007cU) +#define ctxsw_prog_main_image_context_buffer_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) +#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) +#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) +#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_image_global_cb_ptr_o() (0x000000b8U) +#define ctxsw_prog_main_image_global_cb_ptr_v_f(v) (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_global_cb_ptr_hi_o() (0x000000bcU) +#define ctxsw_prog_main_image_global_cb_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_o() (0x000000c0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_hi_o() (0x000000c4U) +#define ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_control_block_ptr_o() (0x000000c8U) +#define ctxsw_prog_main_image_control_block_ptr_v_f(v) (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_control_block_ptr_hi_o() (0x000000ccU) +#define ctxsw_prog_main_image_control_block_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o() (0x000000e0U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o() (0x000000e4U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) +#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) +#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U) +#define ctxsw_prog_local_magic_value_o() (0x000000fcU) +#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU) +#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU) +#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU) +#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U) +#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\ + (0x00000000U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\ + (0x00000002U) +#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ + (((r) >> 0U) & 0x3U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U) +#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U) +#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U) +#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU) +#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U) +#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) +#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ + (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) +#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h index cd28e8b78..4451185c4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,548 +59,145 @@ #include #include -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} +#define falcon_falcon_irqsset_r() (0x00000000U) +#define falcon_falcon_irqsset_swgen0_set_f() (0x40U) +#define falcon_falcon_irqsclr_r() (0x00000004U) +#define falcon_falcon_irqstat_r() (0x00000008U) +#define falcon_falcon_irqstat_halt_true_f() (0x10U) +#define falcon_falcon_irqstat_exterr_true_f() (0x20U) +#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) +#define falcon_falcon_irqmode_r() (0x0000000cU) +#define falcon_falcon_irqmset_r() (0x00000010U) +#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_r() (0x00000014U) +#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqmask_r() (0x00000018U) +#define falcon_falcon_irqdest_r() (0x0000001cU) +#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define falcon_falcon_curctx_r() (0x00000050U) +#define falcon_falcon_nxtctx_r() (0x00000054U) +#define falcon_falcon_mailbox0_r() (0x00000040U) +#define falcon_falcon_mailbox1_r() (0x00000044U) +#define falcon_falcon_itfen_r() (0x00000048U) +#define falcon_falcon_itfen_ctxen_enable_f() (0x1U) +#define falcon_falcon_idlestate_r() (0x0000004cU) +#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define falcon_falcon_os_r() (0x00000080U) +#define falcon_falcon_engctl_r() (0x000000a4U) +#define falcon_falcon_cpuctl_r() (0x00000100U) +#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define falcon_falcon_cpuctl_alias_r() (0x00000130U) +#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) +#define falcon_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_sctl_r() (0x00000240U) +#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define falcon_falcon_bootvec_r() (0x00000104U) +#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define falcon_falcon_dmactl_r() (0x0000010cU) +#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_hwcfg_r() (0x00000108U) +#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define falcon_falcon_dmatrfbase_r() (0x00000110U) +#define falcon_falcon_dmatrfbase1_r() (0x00000128U) +#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) +#define falcon_falcon_dmatrfcmd_r() (0x00000118U) +#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) +#define falcon_falcon_imctl_debug_r() (0x0000015cU) +#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) +#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) +#define falcon_falcon_imstat_r() (0x00000144U) +#define falcon_falcon_traceidx_r() (0x00000148U) +#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) +#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) +#define falcon_falcon_tracepc_r() (0x0000014cU) +#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) +#define falcon_falcon_exterraddr_r() (0x0010a168U) +#define falcon_falcon_exterrstat_r() (0x0010a16cU) +#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) +#define falcon_falcon_icd_cmd_r() (0x00000200U) +#define falcon_falcon_icd_cmd_opc_s() (4U) +#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define falcon_falcon_icd_rdata_r() (0x0000020cU) +#define falcon_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define falcon_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_debug1_r() (0x00000090U) +#define falcon_falcon_debug1_ctxsw_mode_s() (1U) +#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define falcon_falcon_debuginfo_r() (0x00000094U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index 29970d0b0..33c267933 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,1840 +59,511 @@ #include #include -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return U32(0x1U) << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_r(void) -{ - return 0x001fac80U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_hshub_num_active_ltcs_r(void) -{ - return 0x001fbc20U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return U32(0x1U) << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return U32(0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return U32(0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return U32(0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return U32(0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_niso_cfg1_r(void) -{ - return 0x00100c14U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_f(void) -{ - return 0x20000U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_niso_intr_r(void) -{ - return 0x00100a20U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en_set__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a34U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en_clr__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) -{ - return (r >> 1U) & 0x3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x6U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_buffer_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) -{ - return U32(0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_addr_lo_r(void) -{ - return 0x00100e4cU; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_addr_hi_r(void) -{ - return 0x00100e50U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_inst_lo_r(void) -{ - return 0x00100e54U; -} -static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_inst_hi_r(void) -{ - return 0x00100e58U; -} -static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_info_r(void) -{ - return 0x00100e5cU; -} -static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fb_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_status_r(void) -{ - return 0x00100e60U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_replayable_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fb_mmu_fault_status_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_set_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_fault_status_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) -{ - return 0x200U; -} -static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_error_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) -{ - return 0x400U; -} -static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) -{ - return 0x1000U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) -{ - return 0x2000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) -{ - return U32(0x1U) << 14U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) -{ - return 0x4000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) -{ - return 0x8000U; -} -static inline u32 fb_mmu_fault_status_busy_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_mmu_fault_status_busy_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_busy_true_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_status_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_status_valid_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_status_valid_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_local_memory_range_r(void) -{ - return 0x00100ce0U; -} -static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) -{ - return (r >> 4U) & 0x3fU; -} -static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_niso_scrub_status_r(void) -{ - return 0x00100b20U; -} -static inline u32 fb_niso_scrub_status_flag_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_priv_level_mask_r(void) -{ - return 0x00100cdcU; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_hshub_config0_r(void) -{ - return 0x001fbc00U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 fb_hshub_config1_r(void) -{ - return 0x001fbc04U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config2_r(void) -{ - return 0x001fbc08U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config6_r(void) -{ - return 0x001fbc18U; -} -static inline u32 fb_hshub_config7_r(void) -{ - return 0x001fbc1cU; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_r(void) -{ - return 0x001fbc50U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(u32 r) -{ - return (r >> 4U) & 0x7U; -} +#define fb_fbhub_num_active_ltcs_r() (0x00100800U) +#define fb_fbhub_num_active_ltcs_use_nvlink_f(v) (((v)&0xffU) << 16U) +#define fb_fbhub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U) +#define fb_fbhub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_f(v, i)\ + (((v) & 0x1) << (16U + i*1U)) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_m(i)\ + (U32(0x1U) << (16U + (i)*1U)) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_v(r, i)\ + (((r) >> (16U + i*1U)) & 0x1U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ + ((0x1U << (32U +((i)*1U)))) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(v) (((v)&0x1U) << 25U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f() (0x0U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v() (0x00000001U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f() (0x2000000U) +#define fb_mmu_ctrl_r() (0x00100c80U) +#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) +#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) +#define fb_mmu_ctrl_atomic_capability_mode_f(v) (((v)&0x3U) << 24U) +#define fb_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define fb_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U) +#define fb_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U) +#define fb_mmu_ctrl_atomic_capability_mode_l2_f() (0x0U) +#define fb_mmu_ctrl_atomic_capability_mode_atomic_v() (0x00000001U) +#define fb_mmu_ctrl_atomic_capability_mode_atomic_f() (0x1000000U) +#define fb_mmu_ctrl_atomic_capability_mode_rmw_v() (0x00000002U) +#define fb_mmu_ctrl_atomic_capability_mode_rmw_f() (0x2000000U) +#define fb_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U) +#define fb_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U) +#define fb_hsmmu_pri_mmu_ctrl_r() (0x001fac80U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(v) (((v)&0x3U) << 24U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f() (0x0U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v() (0x00000001U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f() (0x1000000U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v() (0x00000002U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f() (0x2000000U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U) +#define fb_hshub_num_active_ltcs_r() (0x001fbc20U) +#define fb_hshub_num_active_ltcs_use_nvlink_f(v) (((v)&0xffU) << 16U) +#define fb_hshub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U) +#define fb_hshub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_f(v, i)\ + (((v) & 0x1) << (16U + i*1U)) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_m(i)\ + (U32(0x1U) << (16U + (i)*1U)) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_v(r, i)\ + (((r) >> (16U + i*1U)) & 0x1U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ + ((0x1U << (32U +((i)*1U)))) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(v) (((v)&0x1U) << 25U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f() (0x0U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v() (0x00000001U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f() (0x2000000U) +#define fb_priv_mmu_phy_secure_r() (0x00100ce4U) +#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) +#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) +#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_invalidate_r() (0x00100cbcU) +#define fb_mmu_invalidate_all_va_true_f() (0x1U) +#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) +#define fb_mmu_invalidate_hubtlb_only_s() (1U) +#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) +#define fb_mmu_invalidate_replay_s() (3U) +#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) +#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) +#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) +#define fb_mmu_invalidate_replay_none_f() (0x0U) +#define fb_mmu_invalidate_replay_start_f() (0x8U) +#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U) +#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) +#define fb_mmu_invalidate_sys_membar_s() (1U) +#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) +#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) +#define fb_mmu_invalidate_ack_s() (2U) +#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) +#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) +#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) +#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) +#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) +#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) +#define fb_mmu_invalidate_cancel_client_id_s() (6U) +#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) +#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) +#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) +#define fb_mmu_invalidate_cancel_client_type_s() (1U) +#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) +#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) +#define fb_mmu_invalidate_cancel_cache_level_s() (3U) +#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) +#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) +#define fb_mmu_invalidate_cancel_cache_level_pte_only_f() (0x1000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f() (0x2000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f() (0x3000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f() (0x4000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f() (0x5000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) +#define fb_mmu_invalidate_trigger_s() (1U) +#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) +#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) +#define fb_mmu_debug_wr_r() (0x00100cc8U) +#define fb_mmu_debug_wr_aperture_s() (2U) +#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_wr_vol_false_f() (0x0U) +#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) +#define fb_mmu_debug_wr_vol_true_f() (0x4U) +#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_rd_r() (0x00100cccU) +#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_rd_vol_false_f() (0x0U) +#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_ctrl_r() (0x00100cc4U) +#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_niso_cfg1_r() (0x00100c14U) +#define fb_niso_cfg1_sysmem_nvlink_f(v) (((v)&0x1U) << 17U) +#define fb_niso_cfg1_sysmem_nvlink_m() (U32(0x1U) << 17U) +#define fb_niso_cfg1_sysmem_nvlink_v(r) (((r) >> 17U) & 0x1U) +#define fb_niso_cfg1_sysmem_nvlink_enabled_v() (0x00000001U) +#define fb_niso_cfg1_sysmem_nvlink_enabled_f() (0x20000U) +#define fb_niso_flush_sysmem_addr_r() (0x00100c10U) +#define fb_niso_intr_r() (0x00100a20U) +#define fb_niso_intr_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_hub_access_counter_notify_pending_f() (0x1U) +#define fb_niso_intr_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_hub_access_counter_error_pending_f() (0x2U) +#define fb_niso_intr_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_mmu_replayable_fault_notify_pending_f() (0x8000000U) +#define fb_niso_intr_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_mmu_replayable_fault_overflow_pending_f() (0x10000000U) +#define fb_niso_intr_mmu_nonreplayable_fault_notify_m() (U32(0x1U) << 29U) +#define fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() (0x20000000U) +#define fb_niso_intr_mmu_nonreplayable_fault_overflow_m() (U32(0x1U) << 30U) +#define fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f() (0x40000000U) +#define fb_niso_intr_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_mmu_other_fault_notify_pending_f() (0x80000000U) +#define fb_niso_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en__size_1_v() (0x00000002U) +#define fb_niso_intr_en_hub_access_counter_notify_f(v) (((v)&0x1U) << 0U) +#define fb_niso_intr_en_hub_access_counter_notify_enabled_f() (0x1U) +#define fb_niso_intr_en_hub_access_counter_error_f(v) (((v)&0x1U) << 1U) +#define fb_niso_intr_en_hub_access_counter_error_enabled_f() (0x2U) +#define fb_niso_intr_en_mmu_replayable_fault_notify_f(v) (((v)&0x1U) << 27U) +#define fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f() (0x8000000U) +#define fb_niso_intr_en_mmu_replayable_fault_overflow_f(v) (((v)&0x1U) << 28U) +#define fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f() (0x10000000U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(v) (((v)&0x1U) << 29U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f() (0x20000000U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(v)\ + (((v)&0x1U) << 30U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f()\ + (0x40000000U) +#define fb_niso_intr_en_mmu_other_fault_notify_f(v) (((v)&0x1U) << 31U) +#define fb_niso_intr_en_mmu_other_fault_notify_enabled_f() (0x80000000U) +#define fb_niso_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en_set__size_1_v() (0x00000002U) +#define fb_niso_intr_en_set_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_en_set_hub_access_counter_notify_set_f() (0x1U) +#define fb_niso_intr_en_set_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_en_set_hub_access_counter_error_set_f() (0x2U) +#define fb_niso_intr_en_set_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f() (0x8000000U) +#define fb_niso_intr_en_set_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f() (0x10000000U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m()\ + (U32(0x1U) << 29U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f() (0x20000000U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m()\ + (U32(0x1U) << 30U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f()\ + (0x40000000U) +#define fb_niso_intr_en_set_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_en_set_mmu_other_fault_notify_set_f() (0x80000000U) +#define fb_niso_intr_en_clr_r(i)\ + (nvgpu_safe_add_u32(0x00100a34U, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en_clr__size_1_v() (0x00000002U) +#define fb_niso_intr_en_clr_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_en_clr_hub_access_counter_notify_set_f() (0x1U) +#define fb_niso_intr_en_clr_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_en_clr_hub_access_counter_error_set_f() (0x2U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f() (0x8000000U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f() (0x10000000U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m()\ + (U32(0x1U) << 29U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f() (0x20000000U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m()\ + (U32(0x1U) << 30U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f()\ + (0x40000000U) +#define fb_niso_intr_en_clr_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_en_clr_mmu_other_fault_notify_set_f() (0x80000000U) +#define fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v() (0x00000000U) +#define fb_niso_intr_en_clr_mmu_replay_fault_buffer_v() (0x00000001U) +#define fb_mmu_fault_buffer_lo_r(i)\ + (nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_lo__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_lo_addr_mode_f(v) (((v)&0x1U) << 0U) +#define fb_mmu_fault_buffer_lo_addr_mode_v(r) (((r) >> 0U) & 0x1U) +#define fb_mmu_fault_buffer_lo_addr_mode_virtual_v() (0x00000000U) +#define fb_mmu_fault_buffer_lo_addr_mode_virtual_f() (0x0U) +#define fb_mmu_fault_buffer_lo_addr_mode_physical_v() (0x00000001U) +#define fb_mmu_fault_buffer_lo_addr_mode_physical_f() (0x1U) +#define fb_mmu_fault_buffer_lo_phys_aperture_f(v) (((v)&0x3U) << 1U) +#define fb_mmu_fault_buffer_lo_phys_aperture_v(r) (((r) >> 1U) & 0x3U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f() (0x4U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f() (0x6U) +#define fb_mmu_fault_buffer_lo_phys_vol_f(v) (((v)&0x1U) << 3U) +#define fb_mmu_fault_buffer_lo_phys_vol_v(r) (((r) >> 3U) & 0x1U) +#define fb_mmu_fault_buffer_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_buffer_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_buffer_hi_r(i)\ + (nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_hi__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_hi_addr_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fault_buffer_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_buffer_get_r(i)\ + (nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_get__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_get_ptr_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_get_ptr_m() (U32(0xfffffU) << 0U) +#define fb_mmu_fault_buffer_get_ptr_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_get_getptr_corrupted_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_m() (U32(0x1U) << 30U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_v() (0x00000001U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_f() (0x40000000U) +#define fb_mmu_fault_buffer_get_overflow_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_get_overflow_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_buffer_get_overflow_clear_v() (0x00000001U) +#define fb_mmu_fault_buffer_get_overflow_clear_f() (0x80000000U) +#define fb_mmu_fault_buffer_put_r(i)\ + (nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_put__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_put_ptr_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_put_ptr_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_put_getptr_corrupted_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_f() (0x40000000U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_no_v() (0x00000000U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_no_f() (0x0U) +#define fb_mmu_fault_buffer_put_overflow_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_put_overflow_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_buffer_put_overflow_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_put_overflow_yes_f() (0x80000000U) +#define fb_mmu_fault_buffer_size_r(i)\ + (nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_size__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_size_val_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_size_val_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_size_overflow_intr_f(v) (((v)&0x1U) << 29U) +#define fb_mmu_fault_buffer_size_overflow_intr_v(r) (((r) >> 29U) & 0x1U) +#define fb_mmu_fault_buffer_size_overflow_intr_enable_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_overflow_intr_enable_f() (0x20000000U) +#define fb_mmu_fault_buffer_size_set_default_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_size_set_default_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_buffer_size_set_default_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_set_default_yes_f() (0x40000000U) +#define fb_mmu_fault_buffer_size_enable_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_size_enable_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_buffer_size_enable_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_buffer_size_enable_true_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_enable_true_f() (0x80000000U) +#define fb_mmu_fault_addr_lo_r() (0x00100e4cU) +#define fb_mmu_fault_addr_lo_phys_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_fault_addr_lo_phys_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f() (0x2U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f() (0x3U) +#define fb_mmu_fault_addr_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_addr_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_addr_hi_r() (0x00100e50U) +#define fb_mmu_fault_addr_hi_addr_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fault_addr_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_inst_lo_r() (0x00100e54U) +#define fb_mmu_fault_inst_lo_engine_id_v(r) (((r) >> 0U) & 0x1ffU) +#define fb_mmu_fault_inst_lo_aperture_v(r) (((r) >> 10U) & 0x3U) +#define fb_mmu_fault_inst_lo_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_inst_lo_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_inst_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_inst_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_inst_hi_r() (0x00100e58U) +#define fb_mmu_fault_inst_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_info_r() (0x00100e5cU) +#define fb_mmu_fault_info_fault_type_v(r) (((r) >> 0U) & 0x1fU) +#define fb_mmu_fault_info_replayable_fault_v(r) (((r) >> 7U) & 0x1U) +#define fb_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU) +#define fb_mmu_fault_info_access_type_v(r) (((r) >> 16U) & 0xfU) +#define fb_mmu_fault_info_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_fault_info_gpc_id_v(r) (((r) >> 24U) & 0x1fU) +#define fb_mmu_fault_info_protected_mode_v(r) (((r) >> 29U) & 0x1U) +#define fb_mmu_fault_info_replayable_fault_en_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_info_valid_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_status_r() (0x00100e60U) +#define fb_mmu_fault_status_dropped_bar1_phys_m() (U32(0x1U) << 0U) +#define fb_mmu_fault_status_dropped_bar1_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_phys_set_f() (0x1U) +#define fb_mmu_fault_status_dropped_bar1_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_phys_clear_f() (0x1U) +#define fb_mmu_fault_status_dropped_bar1_virt_m() (U32(0x1U) << 1U) +#define fb_mmu_fault_status_dropped_bar1_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_virt_set_f() (0x2U) +#define fb_mmu_fault_status_dropped_bar1_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_virt_clear_f() (0x2U) +#define fb_mmu_fault_status_dropped_bar2_phys_m() (U32(0x1U) << 2U) +#define fb_mmu_fault_status_dropped_bar2_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_phys_set_f() (0x4U) +#define fb_mmu_fault_status_dropped_bar2_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_phys_clear_f() (0x4U) +#define fb_mmu_fault_status_dropped_bar2_virt_m() (U32(0x1U) << 3U) +#define fb_mmu_fault_status_dropped_bar2_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_virt_set_f() (0x8U) +#define fb_mmu_fault_status_dropped_bar2_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_virt_clear_f() (0x8U) +#define fb_mmu_fault_status_dropped_ifb_phys_m() (U32(0x1U) << 4U) +#define fb_mmu_fault_status_dropped_ifb_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_phys_set_f() (0x10U) +#define fb_mmu_fault_status_dropped_ifb_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_phys_clear_f() (0x10U) +#define fb_mmu_fault_status_dropped_ifb_virt_m() (U32(0x1U) << 5U) +#define fb_mmu_fault_status_dropped_ifb_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_virt_set_f() (0x20U) +#define fb_mmu_fault_status_dropped_ifb_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_virt_clear_f() (0x20U) +#define fb_mmu_fault_status_dropped_other_phys_m() (U32(0x1U) << 6U) +#define fb_mmu_fault_status_dropped_other_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_phys_set_f() (0x40U) +#define fb_mmu_fault_status_dropped_other_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_phys_clear_f() (0x40U) +#define fb_mmu_fault_status_dropped_other_virt_m() (U32(0x1U) << 7U) +#define fb_mmu_fault_status_dropped_other_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_virt_set_f() (0x80U) +#define fb_mmu_fault_status_dropped_other_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_virt_clear_f() (0x80U) +#define fb_mmu_fault_status_replayable_m() (U32(0x1U) << 8U) +#define fb_mmu_fault_status_replayable_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_set_f() (0x100U) +#define fb_mmu_fault_status_replayable_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_m() (U32(0x1U) << 9U) +#define fb_mmu_fault_status_non_replayable_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_set_f() (0x200U) +#define fb_mmu_fault_status_non_replayable_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_error_m() (U32(0x1U) << 10U) +#define fb_mmu_fault_status_replayable_error_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_error_set_f() (0x400U) +#define fb_mmu_fault_status_replayable_error_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_error_m() (U32(0x1U) << 11U) +#define fb_mmu_fault_status_non_replayable_error_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_error_set_f() (0x800U) +#define fb_mmu_fault_status_non_replayable_error_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_overflow_m() (U32(0x1U) << 12U) +#define fb_mmu_fault_status_replayable_overflow_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_overflow_set_f() (0x1000U) +#define fb_mmu_fault_status_replayable_overflow_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_overflow_m() (U32(0x1U) << 13U) +#define fb_mmu_fault_status_non_replayable_overflow_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_overflow_set_f() (0x2000U) +#define fb_mmu_fault_status_non_replayable_overflow_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_m() (U32(0x1U) << 14U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_set_f() (0x4000U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_m()\ + (U32(0x1U) << 15U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v()\ + (0x00000001U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f() (0x8000U) +#define fb_mmu_fault_status_busy_m() (U32(0x1U) << 30U) +#define fb_mmu_fault_status_busy_true_v() (0x00000001U) +#define fb_mmu_fault_status_busy_true_f() (0x40000000U) +#define fb_mmu_fault_status_valid_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_status_valid_set_v() (0x00000001U) +#define fb_mmu_fault_status_valid_set_f() (0x80000000U) +#define fb_mmu_fault_status_valid_clear_v() (0x00000001U) +#define fb_mmu_fault_status_valid_clear_f() (0x80000000U) +#define fb_mmu_local_memory_range_r() (0x00100ce0U) +#define fb_mmu_local_memory_range_lower_scale_v(r) (((r) >> 0U) & 0xfU) +#define fb_mmu_local_memory_range_lower_mag_v(r) (((r) >> 4U) & 0x3fU) +#define fb_mmu_local_memory_range_ecc_mode_v(r) (((r) >> 30U) & 0x1U) +#define fb_niso_scrub_status_r() (0x00100b20U) +#define fb_niso_scrub_status_flag_v(r) (((r) >> 0U) & 0x1U) +#define fb_mmu_priv_level_mask_r() (0x00100cdcU) +#define fb_mmu_priv_level_mask_write_violation_f(v) (((v)&0x1U) << 7U) +#define fb_mmu_priv_level_mask_write_violation_m() (U32(0x1U) << 7U) +#define fb_mmu_priv_level_mask_write_violation_v(r) (((r) >> 7U) & 0x1U) +#define fb_hshub_config0_r() (0x001fbc00U) +#define fb_hshub_config0_sysmem_nvlink_mask_f(v) (((v)&0xffffU) << 0U) +#define fb_hshub_config0_sysmem_nvlink_mask_m() (U32(0xffffU) << 0U) +#define fb_hshub_config0_sysmem_nvlink_mask_v(r) (((r) >> 0U) & 0xffffU) +#define fb_hshub_config0_peer_pcie_mask_f(v) (((v)&0xffffU) << 16U) +#define fb_hshub_config0_peer_pcie_mask_v(r) (((r) >> 16U) & 0xffffU) +#define fb_hshub_config1_r() (0x001fbc04U) +#define fb_hshub_config1_peer_0_nvlink_mask_f(v) (((v)&0xffU) << 0U) +#define fb_hshub_config1_peer_0_nvlink_mask_v(r) (((r) >> 0U) & 0xffU) +#define fb_hshub_config1_peer_1_nvlink_mask_f(v) (((v)&0xffU) << 8U) +#define fb_hshub_config1_peer_1_nvlink_mask_v(r) (((r) >> 8U) & 0xffU) +#define fb_hshub_config1_peer_2_nvlink_mask_f(v) (((v)&0xffU) << 16U) +#define fb_hshub_config1_peer_2_nvlink_mask_v(r) (((r) >> 16U) & 0xffU) +#define fb_hshub_config1_peer_3_nvlink_mask_f(v) (((v)&0xffU) << 24U) +#define fb_hshub_config1_peer_3_nvlink_mask_v(r) (((r) >> 24U) & 0xffU) +#define fb_hshub_config2_r() (0x001fbc08U) +#define fb_hshub_config2_peer_4_nvlink_mask_f(v) (((v)&0xffU) << 0U) +#define fb_hshub_config2_peer_4_nvlink_mask_v(r) (((r) >> 0U) & 0xffU) +#define fb_hshub_config2_peer_5_nvlink_mask_f(v) (((v)&0xffU) << 8U) +#define fb_hshub_config2_peer_5_nvlink_mask_v(r) (((r) >> 8U) & 0xffU) +#define fb_hshub_config2_peer_6_nvlink_mask_f(v) (((v)&0xffU) << 16U) +#define fb_hshub_config2_peer_6_nvlink_mask_v(r) (((r) >> 16U) & 0xffU) +#define fb_hshub_config2_peer_7_nvlink_mask_f(v) (((v)&0xffU) << 24U) +#define fb_hshub_config2_peer_7_nvlink_mask_v(r) (((r) >> 24U) & 0xffU) +#define fb_hshub_config6_r() (0x001fbc18U) +#define fb_hshub_config7_r() (0x001fbc1cU) +#define fb_hshub_config7_nvlink_logical_0_physical_portmap_f(v)\ + (((v)&0xfU) << 0U) +#define fb_hshub_config7_nvlink_logical_0_physical_portmap_v(r)\ + (((r) >> 0U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_1_physical_portmap_f(v)\ + (((v)&0xfU) << 4U) +#define fb_hshub_config7_nvlink_logical_1_physical_portmap_v(r)\ + (((r) >> 4U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_2_physical_portmap_f(v)\ + (((v)&0xfU) << 8U) +#define fb_hshub_config7_nvlink_logical_2_physical_portmap_v(r)\ + (((r) >> 8U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_3_physical_portmap_f(v)\ + (((v)&0xfU) << 12U) +#define fb_hshub_config7_nvlink_logical_3_physical_portmap_v(r)\ + (((r) >> 12U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_4_physical_portmap_f(v)\ + (((v)&0xfU) << 16U) +#define fb_hshub_config7_nvlink_logical_4_physical_portmap_v(r)\ + (((r) >> 16U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_5_physical_portmap_f(v)\ + (((v)&0xfU) << 20U) +#define fb_hshub_config7_nvlink_logical_5_physical_portmap_v(r)\ + (((r) >> 20U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_6_physical_portmap_f(v)\ + (((v)&0xfU) << 24U) +#define fb_hshub_config7_nvlink_logical_6_physical_portmap_v(r)\ + (((r) >> 24U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_7_physical_portmap_f(v)\ + (((v)&0xfU) << 28U) +#define fb_hshub_config7_nvlink_logical_7_physical_portmap_v(r)\ + (((r) >> 28U) & 0xfU) +#define fb_hshub_nvl_cfg_priv_level_mask_r() (0x001fbc50U) +#define fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(v)\ + (((v)&0x7U) << 4U) +#define fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(r)\ + (((r) >> 4U) & 0x7U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h index 3118b9a37..bd1ded324 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,464 +59,131 @@ #include #include -static inline u32 fifo_userd_writeback_r(void) -{ - return 0x0000225cU; -} -static inline u32 fifo_userd_writeback_timer_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_userd_writeback_timer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_userd_writeback_timer_shorter_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_userd_writeback_timer_100us_v(void) -{ - return 0x00000064U; -} -static inline u32 fifo_userd_writeback_timescale_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fifo_userd_writeback_timescale_0_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x0000000dU; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x0000000dU; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_memop_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_memop_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x0000000eU; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return U32(0x3fffffffU) << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_fb_timeout_period_init_f(void) -{ - return 0x3c00U; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_runlist_preempt_r(void) -{ - return 0x00002638U; -} -static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x0000000fU; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_eng_reload_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x0000000eU; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_cfg0_r(void) -{ - return 0x00002004U; -} -static inline u32 fifo_cfg0_num_pbdma_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} +#define fifo_userd_writeback_r() (0x0000225cU) +#define fifo_userd_writeback_timer_f(v) (((v)&0xffU) << 0U) +#define fifo_userd_writeback_timer_disabled_v() (0x00000000U) +#define fifo_userd_writeback_timer_shorter_v() (0x00000003U) +#define fifo_userd_writeback_timer_100us_v() (0x00000064U) +#define fifo_userd_writeback_timescale_f(v) (((v)&0xfU) << 12U) +#define fifo_userd_writeback_timescale_0_v() (0x00000000U) +#define fifo_runlist_base_r() (0x00002270U) +#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_runlist_base_target_vid_mem_f() (0x0U) +#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) +#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) +#define fifo_runlist_r() (0x00002274U) +#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) +#define fifo_eng_runlist_base_r(i)\ + (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist_base__size_1_v() (0x0000000dU) +#define fifo_eng_runlist_r(i)\ + (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist__size_1_v() (0x0000000dU) +#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) +#define fifo_eng_runlist_length_max_v() (0x0000ffffU) +#define fifo_eng_runlist_pending_true_f() (0x100000U) +#define fifo_pb_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pb_timeslice_timeout_16_f() (0x10U) +#define fifo_pb_timeslice_timescale_0_f() (0x0U) +#define fifo_pb_timeslice_enable_true_f() (0x10000000U) +#define fifo_pbdma_map_r(i)\ + (nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_0_r() (0x00002100U) +#define fifo_intr_0_bind_error_pending_f() (0x1U) +#define fifo_intr_0_bind_error_reset_f() (0x1U) +#define fifo_intr_0_sched_error_pending_f() (0x100U) +#define fifo_intr_0_sched_error_reset_f() (0x100U) +#define fifo_intr_0_chsw_error_pending_f() (0x10000U) +#define fifo_intr_0_chsw_error_reset_f() (0x10000U) +#define fifo_intr_0_memop_timeout_pending_f() (0x800000U) +#define fifo_intr_0_memop_timeout_reset_f() (0x800000U) +#define fifo_intr_0_lb_error_pending_f() (0x1000000U) +#define fifo_intr_0_lb_error_reset_f() (0x1000000U) +#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U) +#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) +#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) +#define fifo_intr_en_0_r() (0x00002140U) +#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) +#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) +#define fifo_intr_en_1_r() (0x00002528U) +#define fifo_intr_bind_error_r() (0x0000252cU) +#define fifo_intr_sched_error_r() (0x0000254cU) +#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) +#define fifo_intr_chsw_error_r() (0x0000256cU) +#define fifo_intr_pbdma_id_r() (0x000025a0U) +#define fifo_intr_pbdma_id_status_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_pbdma_id_status_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_pbdma_id_status__size_1_v() (0x0000000eU) +#define fifo_intr_runlist_r() (0x00002a00U) +#define fifo_fb_timeout_r() (0x00002a04U) +#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U) +#define fifo_fb_timeout_period_max_f() (0x3fffffffU) +#define fifo_fb_timeout_period_init_f() (0x3c00U) +#define fifo_sched_disable_r() (0x00002630U) +#define fifo_sched_disable_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_sched_disable_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_sched_disable_true_v() (0x00000001U) +#define fifo_runlist_preempt_r() (0x00002638U) +#define fifo_runlist_preempt_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_runlist_preempt_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_runlist_preempt_runlist_pending_v() (0x00000001U) +#define fifo_preempt_r() (0x00002634U) +#define fifo_preempt_pending_true_f() (0x100000U) +#define fifo_preempt_type_channel_f() (0x0U) +#define fifo_preempt_type_tsg_f() (0x1000000U) +#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) +#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) +#define fifo_engine_status_r(i)\ + (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_engine_status__size_1_v() (0x0000000fU) +#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_engine_status_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_engine_status_ctx_status_valid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U) +#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U) +#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U) +#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_engine_status_next_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_eng_reload_v(r) (((r) >> 29U) & 0x1U) +#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U) +#define fifo_engine_status_faulted_true_v() (0x00000001U) +#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U) +#define fifo_engine_status_engine_idle_v() (0x00000000U) +#define fifo_engine_status_engine_busy_v() (0x00000001U) +#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U) +#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U) +#define fifo_pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pbdma_status__size_1_v() (0x0000000eU) +#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_pbdma_status_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U) +#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U) +#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U) +#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U) +#define fifo_cfg0_r() (0x00002004U) +#define fifo_cfg0_num_pbdma_v(r) (((r) >> 0U) & 0xffU) +#define fifo_cfg0_pbdma_fault_id_v(r) (((r) >> 16U) & 0xffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h index 9a877da30..2b8e718f6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,132 +59,36 @@ #include #include -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} +#define flush_l2_system_invalidate_r() (0x00070004U) +#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U) +#define flush_l2_system_invalidate_pending_busy_f() (0x1U) +#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U) +#define flush_l2_flush_dirty_r() (0x00070010U) +#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U) +#define flush_l2_flush_dirty_pending_empty_f() (0x0U) +#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U) +#define flush_l2_flush_dirty_pending_busy_f() (0x1U) +#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U) +#define flush_l2_flush_dirty_outstanding_false_f() (0x0U) +#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U) +#define flush_l2_clean_comptags_r() (0x0007000cU) +#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U) +#define flush_l2_clean_comptags_pending_empty_f() (0x0U) +#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U) +#define flush_l2_clean_comptags_pending_busy_f() (0x1U) +#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U) +#define flush_l2_clean_comptags_outstanding_false_f() (0x0U) +#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U) +#define flush_fb_flush_r() (0x00070000U) +#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_fb_flush_pending_busy_v() (0x00000001U) +#define flush_fb_flush_pending_busy_f() (0x1U) +#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_fb_flush_outstanding_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h index 6d5f588a2..bf49f82af 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,92 +59,30 @@ #include #include -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} +#define fuse_status_opt_gpc_r() (0x00021c1cU) +#define fuse_status_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) +#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0xffU) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU) +#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) +#define fuse_status_opt_fbio_r() (0x00021c14U) +#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) +#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) +#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) +#define fuse_status_opt_rop_l2_fbp_r(i)\ + (nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_status_opt_fbp_r() (0x00021d38U) +#define fuse_status_opt_fbp_idx_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fuse_opt_ecc_en_r() (0x00021228U) +#define fuse_opt_feature_fuses_override_disable_r() (0x000213f0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h index 7c9a430e2..91393cd72 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,300 +59,78 @@ #include #include -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_type_unbound_inst_block_v(void) -{ - return 0x00000004U; -} -static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) -{ - return 0x00000005U; -} -static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) -{ - return 0x0000001fU; -} -static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) -{ - return 0x0000000fU; -} +#define gmmu_new_pde_is_pte_w() (0U) +#define gmmu_new_pde_is_pte_false_f() (0x0U) +#define gmmu_new_pde_aperture_w() (0U) +#define gmmu_new_pde_aperture_invalid_f() (0x0U) +#define gmmu_new_pde_aperture_video_memory_f() (0x2U) +#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pde_address_sys_w() (0U) +#define gmmu_new_pde_vol_w() (0U) +#define gmmu_new_pde_vol_true_f() (0x8U) +#define gmmu_new_pde_vol_false_f() (0x0U) +#define gmmu_new_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_pde__size_v() (0x00000008U) +#define gmmu_new_dual_pde_is_pte_w() (0U) +#define gmmu_new_dual_pde_is_pte_false_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_w() (0U) +#define gmmu_new_dual_pde_aperture_big_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_new_dual_pde_address_big_sys_w() (0U) +#define gmmu_new_dual_pde_aperture_small_w() (2U) +#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_small_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_vol_small_w() (2U) +#define gmmu_new_dual_pde_vol_small_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_small_false_f() (0x0U) +#define gmmu_new_dual_pde_vol_big_w() (0U) +#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) +#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_dual_pde_address_small_sys_w() (2U) +#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) +#define gmmu_new_dual_pde__size_v() (0x00000010U) +#define gmmu_new_pte__size_v() (0x00000008U) +#define gmmu_new_pte_valid_w() (0U) +#define gmmu_new_pte_valid_true_f() (0x1U) +#define gmmu_new_pte_valid_false_f() (0x0U) +#define gmmu_new_pte_privilege_w() (0U) +#define gmmu_new_pte_privilege_true_f() (0x20U) +#define gmmu_new_pte_privilege_false_f() (0x0U) +#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_sys_w() (0U) +#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_vid_w() (0U) +#define gmmu_new_pte_vol_w() (0U) +#define gmmu_new_pte_vol_true_f() (0x8U) +#define gmmu_new_pte_vol_false_f() (0x0U) +#define gmmu_new_pte_aperture_w() (0U) +#define gmmu_new_pte_aperture_video_memory_f() (0x0U) +#define gmmu_new_pte_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pte_read_only_w() (0U) +#define gmmu_new_pte_read_only_true_f() (0x40U) +#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U) +#define gmmu_new_pte_comptagline_w() (1U) +#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) +#define gmmu_new_pte_kind_w() (1U) +#define gmmu_new_pte_address_shift_v() (0x0000000cU) +#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) +#define gmmu_pte_kind_w() (1U) +#define gmmu_pte_kind_invalid_v() (0x000000ffU) +#define gmmu_pte_kind_pitch_v() (0x00000000U) +#define gmmu_fault_client_type_gpc_v() (0x00000000U) +#define gmmu_fault_client_type_hub_v() (0x00000001U) +#define gmmu_fault_type_unbound_inst_block_v() (0x00000004U) +#define gmmu_fault_mmu_eng_id_bar2_v() (0x00000005U) +#define gmmu_fault_mmu_eng_id_physical_v() (0x0000001fU) +#define gmmu_fault_mmu_eng_id_ce0_v() (0x0000000fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index 652bd492a..83bfbab18 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,4052 +59,1118 @@ #include #include -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_en_fe_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception_en_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_en_gpc_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 gr_exception_en_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_en_memfmt_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_exception_en_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_en_ds_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_exception_en_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_en_pd_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_exception_en_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_en_scc_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_exception_en_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_en_ssync_enabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_exception_en_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception_en_mme_enabled_f(void) -{ - return 0x80U; -} -static inline u32 gr_exception_en_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_en_sked_enabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x0050433cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419b3cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_fe_chip_def_info_r(void) -{ - return 0x00404030U; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x00504358U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) -{ - return U32(0x1U) << 14U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 26U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) -{ - return 0x0050435cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) -{ - return 0x00504360U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) -{ - return 0x0050436cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) -{ - return 0x00504370U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) -{ - return 0x00504374U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) -{ - return 0x0050463cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) -{ - return 0x00504640U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) -{ - return 0x00504430U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) -{ - return 0x00504434U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_address_veid_f(u32 v) -{ - return (v & 0x3fU) << 20U; -} -static inline u32 gr_pipe_bundle_address_veid_w(void) -{ - return 0U; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x0050472cU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) -{ - return 0x00419eb4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_irqsset_r(void) -{ - return 0x00409000U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_irqsset_r(void) -{ - return 0x0041a000U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return U32(0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00001680U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00001680U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return U32(0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ssync_hww_esr_r(void) -{ - return 0x00405a14U; -} -static inline u32 gr_ssync_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ssync_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x00504330U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000480U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00000d10U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000480U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419e00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419e04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return U32(0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return U32(0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x000004b0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00418100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0041814cU; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) -{ - return 0x00418198U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) -{ - return 0x00504728U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void) -{ - return 0x4000000U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00504710U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504714U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) -{ - return 0x00504718U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x0050471cU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00419e90U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00419e94U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) -{ - return 0x00419e80U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void) -{ - return 0x5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void) -{ - return 0x6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void) -{ - return 0x9U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void) -{ - return 0xbU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void) -{ - return 0xdU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void) -{ - return 0xeU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) -{ - return 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void) -{ - return 0x12U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void) -{ - return 0x16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void) -{ - return 0x17U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void) -{ - return 0x19U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) -{ - return U32(0xfU) << 24U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x005043a0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419ba0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x005043b0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419bb0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) -{ - return 0x00000005U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) -{ - return 0x00419a00U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) -{ - return U32(0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) -{ - return 0x00419bf0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return U32(0x3U) << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return U32(0x3U) << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) -{ - return 0x00419e84U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419bd8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return U32(0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419ba4U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return U32(0x3U) << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return U32(0x1ffU) << 0U; -} +#define gr_intr_r() (0x00400100U) +#define gr_intr_notify_pending_f() (0x1U) +#define gr_intr_notify_reset_f() (0x1U) +#define gr_intr_semaphore_pending_f() (0x2U) +#define gr_intr_semaphore_reset_f() (0x2U) +#define gr_intr_illegal_method_pending_f() (0x10U) +#define gr_intr_illegal_method_reset_f() (0x10U) +#define gr_intr_illegal_notify_pending_f() (0x40U) +#define gr_intr_illegal_notify_reset_f() (0x40U) +#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) +#define gr_intr_firmware_method_pending_f() (0x100U) +#define gr_intr_firmware_method_reset_f() (0x100U) +#define gr_intr_illegal_class_pending_f() (0x20U) +#define gr_intr_illegal_class_reset_f() (0x20U) +#define gr_intr_fecs_error_pending_f() (0x80000U) +#define gr_intr_fecs_error_reset_f() (0x80000U) +#define gr_intr_class_error_pending_f() (0x100000U) +#define gr_intr_class_error_reset_f() (0x100000U) +#define gr_intr_exception_pending_f() (0x200000U) +#define gr_intr_exception_reset_f() (0x200000U) +#define gr_fecs_intr_r() (0x00400144U) +#define gr_class_error_r() (0x00400110U) +#define gr_class_error_code_v(r) (((r) >> 0U) & 0xffffU) +#define gr_intr_nonstall_r() (0x00400120U) +#define gr_intr_nonstall_trap_pending_f() (0x2U) +#define gr_intr_en_r() (0x0040013cU) +#define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception1_r() (0x00400118U) +#define gr_exception1_gpc_0_pending_f() (0x1U) +#define gr_exception2_r() (0x0040011cU) +#define gr_exception_en_r() (0x00400138U) +#define gr_exception_en_fe_m() (U32(0x1U) << 0U) +#define gr_exception_en_fe_enabled_f() (0x1U) +#define gr_exception_en_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_en_gpc_enabled_f() (0x1000000U) +#define gr_exception_en_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_en_memfmt_enabled_f() (0x2U) +#define gr_exception_en_ds_m() (U32(0x1U) << 4U) +#define gr_exception_en_ds_enabled_f() (0x10U) +#define gr_exception_en_pd_m() (U32(0x1U) << 2U) +#define gr_exception_en_pd_enabled_f() (0x4U) +#define gr_exception_en_scc_m() (U32(0x1U) << 3U) +#define gr_exception_en_scc_enabled_f() (0x8U) +#define gr_exception_en_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_en_ssync_enabled_f() (0x20U) +#define gr_exception_en_mme_m() (U32(0x1U) << 7U) +#define gr_exception_en_mme_enabled_f() (0x80U) +#define gr_exception_en_sked_m() (U32(0x1U) << 8U) +#define gr_exception_en_sked_enabled_f() (0x100U) +#define gr_exception1_en_r() (0x00400130U) +#define gr_exception2_en_r() (0x00400134U) +#define gr_gpfifo_ctl_r() (0x00400500U) +#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) +#define gr_gpfifo_ctl_access_disabled_f() (0x0U) +#define gr_gpfifo_ctl_access_enabled_f() (0x1U) +#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) +#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) +#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) +#define gr_gpfifo_status_r() (0x00400504U) +#define gr_trapped_addr_r() (0x00400704U) +#define gr_trapped_addr_mthd_v(r) (((r) >> 2U) & 0xfffU) +#define gr_trapped_addr_subch_v(r) (((r) >> 16U) & 0x7U) +#define gr_trapped_addr_mme_generated_v(r) (((r) >> 20U) & 0x1U) +#define gr_trapped_addr_datahigh_v(r) (((r) >> 24U) & 0x1U) +#define gr_trapped_addr_priv_v(r) (((r) >> 28U) & 0x1U) +#define gr_trapped_addr_status_v(r) (((r) >> 31U) & 0x1U) +#define gr_trapped_data_lo_r() (0x00400708U) +#define gr_trapped_data_hi_r() (0x0040070cU) +#define gr_trapped_data_mme_r() (0x00400710U) +#define gr_trapped_data_mme_pc_v(r) (((r) >> 0U) & 0xfffU) +#define gr_status_r() (0x00400700U) +#define gr_status_fe_method_upper_v(r) (((r) >> 1U) & 0x1U) +#define gr_status_fe_method_lower_v(r) (((r) >> 2U) & 0x1U) +#define gr_status_fe_method_lower_idle_v() (0x00000000U) +#define gr_status_fe_gi_v(r) (((r) >> 21U) & 0x1U) +#define gr_status_mask_r() (0x00400610U) +#define gr_status_1_r() (0x00400604U) +#define gr_status_2_r() (0x00400608U) +#define gr_engine_status_r() (0x0040060cU) +#define gr_engine_status_value_busy_f() (0x1U) +#define gr_pri_be0_becs_be_exception_r() (0x00410204U) +#define gr_pri_be0_becs_be_exception_en_r() (0x00410208U) +#define gr_pri_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_pri_gpc0_gpccs_gpc_exception_en_r() (0x00502c94U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_activity_0_r() (0x00400380U) +#define gr_activity_1_r() (0x00400384U) +#define gr_activity_2_r() (0x00400388U) +#define gr_activity_4_r() (0x00400390U) +#define gr_activity_4_gpc0_s() (3U) +#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) +#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) +#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) +#define gr_activity_4_gpc0_empty_v() (0x00000000U) +#define gr_activity_4_gpc0_preempted_v() (0x00000004U) +#define gr_pri_gpc0_gcc_dbg_r() (0x00501000U) +#define gr_pri_gpcs_gcc_dbg_r() (0x00419000U) +#define gr_pri_gpcs_gcc_dbg_invalidate_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cache_control_r() (0x0050433cU) +#define gr_pri_gpcs_tpcs_sm_cache_control_r() (0x00419b3cU) +#define gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m() (U32(0x1U) << 0U) +#define gr_pri_sked_activity_r() (0x00407054U) +#define gr_pri_gpc0_gpccs_gpc_activity0_r() (0x00502c80U) +#define gr_pri_gpc0_gpccs_gpc_activity1_r() (0x00502c84U) +#define gr_pri_gpc0_gpccs_gpc_activity2_r() (0x00502c88U) +#define gr_pri_gpc0_gpccs_gpc_activity3_r() (0x00502c8cU) +#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() (0x00504500U) +#define gr_pri_gpcs_gpccs_gpc_activity_0_r() (0x0041ac80U) +#define gr_pri_gpcs_gpccs_gpc_activity_1_r() (0x0041ac84U) +#define gr_pri_gpcs_gpccs_gpc_activity_2_r() (0x0041ac88U) +#define gr_pri_gpcs_gpccs_gpc_activity_3_r() (0x0041ac8cU) +#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r() (0x00419d00U) +#define gr_pri_be0_becs_be_activity0_r() (0x00410200U) +#define gr_pri_bes_becs_be_activity0_r() (0x00408a00U) +#define gr_pri_ds_mpipe_status_r() (0x00405858U) +#define gr_pri_fe_go_idle_info_r() (0x00404194U) +#define gr_pri_fe_chip_def_info_r() (0x00404030U) +#define gr_pri_fe_chip_def_info_max_veid_count_v(r) (((r) >> 0U) & 0xfffU) +#define gr_pri_fe_chip_def_info_max_veid_count_init_v() (0x00000040U) +#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r() (0x00504238U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() (0x00504358U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m()\ + (U32(0x1U) << 8U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m()\ + (U32(0x1U) << 9U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m()\ + (U32(0x1U) << 10U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m()\ + (U32(0x1U) << 11U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m()\ + (U32(0x1U) << 12U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m()\ + (U32(0x1U) << 13U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m()\ + (U32(0x1U) << 14U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m()\ + (U32(0x1U) << 15U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 24U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 26U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() (0x0050435cU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() (0x00504360U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r() (0x0050436cU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 8U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 10U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() (0x00504370U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() (0x00504374U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r() (0x00504638U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 16U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 18U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() (0x0050463cU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() (0x00504640U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_tex_m_routing_r() (0x005042c4U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f() (0x0U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f() (0x1U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f() (0x2U) +#define gr_gpc0_tpc0_mpc_hww_esr_r() (0x00504430U) +#define gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f() (0x40000000U) +#define gr_gpc0_tpc0_mpc_hww_esr_info_r() (0x00504434U) +#define gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(r) (((r) >> 0U) & 0x3fU) +#define gr_pri_be0_crop_status1_r() (0x00410134U) +#define gr_pri_bes_crop_status1_r() (0x00408934U) +#define gr_pri_be0_zrop_status_r() (0x00410048U) +#define gr_pri_be0_zrop_status2_r() (0x0041004cU) +#define gr_pri_bes_zrop_status_r() (0x00408848U) +#define gr_pri_bes_zrop_status2_r() (0x0040884cU) +#define gr_pipe_bundle_address_r() (0x00400200U) +#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pipe_bundle_address_veid_f(v) (((v)&0x3fU) << 20U) +#define gr_pipe_bundle_address_veid_w() (0U) +#define gr_pipe_bundle_data_r() (0x00400204U) +#define gr_pipe_bundle_config_r() (0x00400208U) +#define gr_pipe_bundle_config_override_pipe_mode_disabled_f() (0x0U) +#define gr_pipe_bundle_config_override_pipe_mode_enabled_f() (0x80000000U) +#define gr_fe_hww_esr_r() (0x00404000U) +#define gr_fe_hww_esr_reset_active_f() (0x40000000U) +#define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) +#define gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() (0x00419eacU) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() (0x0050472cU) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()\ + (0x4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f()\ + (0x40U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f()\ + (0x100U) +#define gr_gpcs_tpcs_sms_hww_global_esr_r() (0x00419eb4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_r() (0x00504734U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m() (U32(0x1U) << 5U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m()\ + (U32(0x1U) << 6U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m()\ + (U32(0x1U) << 2U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m() (U32(0x1U) << 8U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f() (0x100U) +#define gr_fe_go_idle_timeout_r() (0x00404154U) +#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) +#define gr_fe_go_idle_timeout_count_prod_f() (0x1800U) +#define gr_fe_object_table_r(i)\ + (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) +#define gr_fe_tpc_fs_r(i)\ + (nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) +#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_mme_hww_esr_r() (0x00404490U) +#define gr_mme_hww_esr_reset_active_f() (0x40000000U) +#define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) +#define gr_memfmt_hww_esr_r() (0x00404600U) +#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) +#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) +#define gr_fecs_cpuctl_r() (0x00409100U) +#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_cpuctl_alias_r() (0x00409130U) +#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_dmactl_r() (0x0040910cU) +#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_fecs_os_r() (0x00409080U) +#define gr_fecs_idlestate_r() (0x0040904cU) +#define gr_fecs_mailbox0_r() (0x00409040U) +#define gr_fecs_mailbox1_r() (0x00409044U) +#define gr_fecs_irqstat_r() (0x00409008U) +#define gr_fecs_irqmode_r() (0x0040900cU) +#define gr_fecs_irqmask_r() (0x00409018U) +#define gr_fecs_irqdest_r() (0x0040901cU) +#define gr_fecs_curctx_r() (0x00409050U) +#define gr_fecs_nxtctx_r() (0x00409054U) +#define gr_fecs_engctl_r() (0x004090a4U) +#define gr_fecs_debug1_r() (0x00409090U) +#define gr_fecs_debuginfo_r() (0x00409094U) +#define gr_fecs_icd_cmd_r() (0x00409200U) +#define gr_fecs_icd_cmd_opc_s() (4U) +#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) +#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) +#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define gr_fecs_icd_rdata_r() (0x0040920cU) +#define gr_fecs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmemc_offs_s() (6U) +#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) +#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmatrfbase_r() (0x00409110U) +#define gr_fecs_dmatrfmoffs_r() (0x00409114U) +#define gr_fecs_dmatrffboffs_r() (0x0040911cU) +#define gr_fecs_dmatrfcmd_r() (0x00409118U) +#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define gr_fecs_bootvec_r() (0x00409104U) +#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_irqsset_r() (0x00409000U) +#define gr_fecs_falcon_hwcfg_r() (0x00409108U) +#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) +#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) +#define gr_fecs_falcon_rm_r() (0x00409084U) +#define gr_fecs_current_ctx_r() (0x00409b00U) +#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_current_ctx_target_s() (2U) +#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_current_ctx_valid_s() (1U) +#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_current_ctx_valid_false_f() (0x0U) +#define gr_fecs_method_data_r() (0x00409500U) +#define gr_fecs_method_push_r() (0x00409504U) +#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) +#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) +#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) +#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) +#define gr_fecs_method_push_adr_wfi_golden_save_v() (0x00000009U) +#define gr_fecs_method_push_adr_restore_golden_v() (0x00000015U) +#define gr_fecs_method_push_adr_discover_zcull_image_size_v() (0x00000016U) +#define gr_fecs_method_push_adr_discover_pm_image_size_v() (0x00000025U) +#define gr_fecs_method_push_adr_discover_reglist_image_size_v() (0x00000030U) +#define gr_fecs_method_push_adr_set_reglist_bind_instance_v() (0x00000031U) +#define gr_fecs_method_push_adr_set_reglist_virtual_address_v() (0x00000032U) +#define gr_fecs_method_push_adr_stop_ctxsw_v() (0x00000038U) +#define gr_fecs_method_push_adr_start_ctxsw_v() (0x00000039U) +#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) +#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU) +#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) +#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\ + (0x0000003aU) +#define gr_fecs_host_int_status_r() (0x00409c18U) +#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) +#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) +#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) +#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_host_int_clear_r() (0x00409c20U) +#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) +#define gr_fecs_host_int_enable_r() (0x00409c24U) +#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) +#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) +#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f() (0x20000U) +#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f() (0x40000U) +#define gr_fecs_host_int_enable_watchdog_enable_f() (0x80000U) +#define gr_fecs_ctxsw_reset_ctl_r() (0x00409614U) +#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() (0x10U) +#define gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() (0x20U) +#define gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() (0x40U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() (0x100U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f() (0x400U) +#define gr_fecs_ctx_state_store_major_rev_id_r() (0x0040960cU) +#define gr_fecs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) +#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) +#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) +#define gr_fecs_ctxsw_mailbox_set_r(i)\ + (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_clear_r(i)\ + (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_fs_r() (0x00409604U) +#define gr_fecs_fs_num_available_gpcs_s() (5U) +#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_fs_num_available_fbps_s() (5U) +#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) +#define gr_fecs_cfg_r() (0x00409620U) +#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_fecs_rc_lanes_r() (0x00409880U) +#define gr_fecs_rc_lanes_num_chains_s() (6U) +#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_fecs_ctxsw_status_1_r() (0x00409400U) +#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) +#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) +#define gr_fecs_new_ctx_r() (0x00409b04U) +#define gr_fecs_new_ctx_ptr_s() (28U) +#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_new_ctx_target_s() (2U) +#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_valid_s() (1U) +#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) +#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) +#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_arb_ctx_ptr_target_s() (2U) +#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) +#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) +#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) +#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r() (0x00502c04U) +#define gr_gpc0_gpccs_ctxsw_status_1_r() (0x00502400U) +#define gr_fecs_ctxsw_idlestate_r() (0x00409420U) +#define gr_fecs_feature_override_ecc_r() (0x00409658U) +#define gr_fecs_feature_override_ecc_sm_lrf_override_v(r) (((r) >> 3U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_override_v(r) (((r) >> 15U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_lrf_v(r) (((r) >> 0U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_v(r) (((r) >> 12U) & 0x1U) +#define gr_gpc0_gpccs_ctxsw_idlestate_r() (0x00502420U) +#define gr_rstr2d_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) +#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_pd_hww_esr_r() (0x00406018U) +#define gr_pd_hww_esr_reset_active_f() (0x40000000U) +#define gr_pd_hww_esr_en_enable_f() (0x80000000U) +#define gr_pd_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) +#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) +#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) +#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) +#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) +#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) +#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) +#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) +#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) +#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) +#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) +#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) +#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) +#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) +#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) +#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) +#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00001680U) +#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) +#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) +#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00001680U) +#define gr_pd_dist_skip_table_r(i)\ + (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) +#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_ds_debug_r() (0x00405800U) +#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) +#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) +#define gr_ds_zbc_color_r_r() (0x00405804U) +#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_g_r() (0x00405808U) +#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_b_r() (0x0040580cU) +#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_a_r() (0x00405810U) +#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_fmt_r() (0x00405814U) +#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) +#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) +#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) +#define gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v() (0x00000004U) +#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) +#define gr_ds_zbc_z_r() (0x00405818U) +#define gr_ds_zbc_z_val_s() (32U) +#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_ds_zbc_z_val__init_v() (0x00000000U) +#define gr_ds_zbc_z_val__init_f() (0x0U) +#define gr_ds_zbc_z_fmt_r() (0x0040581cU) +#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) +#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) +#define gr_ds_zbc_tbl_index_r() (0x00405820U) +#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) +#define gr_ds_zbc_tbl_ld_r() (0x00405824U) +#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) +#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) +#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) +#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) +#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) +#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) +#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) +#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) +#define gr_ds_hww_esr_r() (0x00405840U) +#define gr_ds_hww_esr_reset_s() (1U) +#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) +#define gr_ds_hww_esr_2_r() (0x00405848U) +#define gr_ds_hww_esr_2_reset_s() (1U) +#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_2_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_2_en_enabled_f() (0x80000000U) +#define gr_ds_hww_report_mask_r() (0x00405844U) +#define gr_ds_hww_report_mask_sph0_err_report_f() (0x1U) +#define gr_ds_hww_report_mask_sph1_err_report_f() (0x2U) +#define gr_ds_hww_report_mask_sph2_err_report_f() (0x4U) +#define gr_ds_hww_report_mask_sph3_err_report_f() (0x8U) +#define gr_ds_hww_report_mask_sph4_err_report_f() (0x10U) +#define gr_ds_hww_report_mask_sph5_err_report_f() (0x20U) +#define gr_ds_hww_report_mask_sph6_err_report_f() (0x40U) +#define gr_ds_hww_report_mask_sph7_err_report_f() (0x80U) +#define gr_ds_hww_report_mask_sph8_err_report_f() (0x100U) +#define gr_ds_hww_report_mask_sph9_err_report_f() (0x200U) +#define gr_ds_hww_report_mask_sph10_err_report_f() (0x400U) +#define gr_ds_hww_report_mask_sph11_err_report_f() (0x800U) +#define gr_ds_hww_report_mask_sph12_err_report_f() (0x1000U) +#define gr_ds_hww_report_mask_sph13_err_report_f() (0x2000U) +#define gr_ds_hww_report_mask_sph14_err_report_f() (0x4000U) +#define gr_ds_hww_report_mask_sph15_err_report_f() (0x8000U) +#define gr_ds_hww_report_mask_sph16_err_report_f() (0x10000U) +#define gr_ds_hww_report_mask_sph17_err_report_f() (0x20000U) +#define gr_ds_hww_report_mask_sph18_err_report_f() (0x40000U) +#define gr_ds_hww_report_mask_sph19_err_report_f() (0x80000U) +#define gr_ds_hww_report_mask_sph20_err_report_f() (0x100000U) +#define gr_ds_hww_report_mask_sph21_err_report_f() (0x200000U) +#define gr_ds_hww_report_mask_sph22_err_report_f() (0x400000U) +#define gr_ds_hww_report_mask_sph23_err_report_f() (0x800000U) +#define gr_ds_hww_report_mask_2_r() (0x0040584cU) +#define gr_ds_hww_report_mask_2_sph24_err_report_f() (0x1U) +#define gr_ds_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_scc_bundle_cb_base_r() (0x00408004U) +#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_bundle_cb_size_r() (0x00408008U) +#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U) +#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) +#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_scc_pagepool_base_r() (0x0040800cU) +#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_pagepool_r() (0x00408010U) +#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) +#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) +#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) +#define gr_scc_pagepool_max_valid_pages_s() (10U) +#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) +#define gr_scc_pagepool_valid_true_f() (0x80000000U) +#define gr_scc_hww_esr_r() (0x00408030U) +#define gr_scc_hww_esr_reset_active_f() (0x40000000U) +#define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_ssync_hww_esr_r() (0x00405a14U) +#define gr_ssync_hww_esr_reset_active_f() (0x40000000U) +#define gr_ssync_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) +#define gr_sked_hww_esr_en_r() (0x00407024U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m()\ + (U32(0x1U) << 25U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() (0x0U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()\ + (0x2000000U) +#define gr_cwd_fs_r() (0x00405b00U) +#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) +#define gr_cwd_gpc_tpc_id_r(i)\ + (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) +#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) +#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) +#define gr_cwd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_sm_id__size_1_v() (0x00000010U) +#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) +#define gr_gpc0_fs_gpc_r() (0x00502608U) +#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) +#define gr_gpc0_cfg_r() (0x00502620U) +#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpccs_rc_lanes_r() (0x00502880U) +#define gr_gpccs_rc_lanes_num_chains_s() (6U) +#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_rc_lane_size_r() (0x00502910U) +#define gr_gpccs_rc_lane_size_v_s() (24U) +#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) +#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) +#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) +#define gr_gpc0_zcull_fs_r() (0x00500910U) +#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) +#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) +#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ + (((v)&0xfU) << 0U) +#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) +#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) +#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) +#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) +#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_zcull_zcsize_r(i)\ + (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) +#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) +#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) +#define gr_gpc0_gpm_pd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ + (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) +#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_r() (0x00504608U) +#define gr_gpc0_tpc0_sm_cfg_tpc_id_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_tpc_id_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_arch_r() (0x00504330U) +#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU) +#define gr_gpc0_tpc0_sm_arch_sm_version_v(r) (((r) >> 20U) & 0xfffU) +#define gr_gpc0_ppc0_pes_vsc_strem_r() (0x00503018U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000480U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00000d10U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ + (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000480U) +#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U) +#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419e04U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) +#define gr_gpccs_falcon_addr_r() (0x0041a0acU) +#define gr_gpccs_falcon_addr_lsb_s() (6U) +#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_msb_s() (6U) +#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) +#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_ext_s() (12U) +#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) +#define gr_gpccs_cpuctl_r() (0x0041a100U) +#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_gpccs_dmactl_r() (0x0041a10cU) +#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_gpccs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt__size_1_v() (0x00000004U) +#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_gpccs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U) +#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x000004b0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ + (0x00000100U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) +#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ + (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ + (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ + (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ + (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ + (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00418100U) +#define gr_gpcs_swdx_dss_zbc_z_r(i)\ + (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0041814cU) +#define gr_gpcs_swdx_dss_zbc_s_r(i)\ + (nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_s_val_f(v) (((v)&0xffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() (0x00418198U) +#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) +#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) +#define gr_crstr_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_crstr_gpc_map_tile0_f(v) (((v)&0x1fU) << 0U) +#define gr_crstr_gpc_map_tile1_f(v) (((v)&0x1fU) << 5U) +#define gr_crstr_gpc_map_tile2_f(v) (((v)&0x1fU) << 10U) +#define gr_crstr_gpc_map_tile3_f(v) (((v)&0x1fU) << 15U) +#define gr_crstr_gpc_map_tile4_f(v) (((v)&0x1fU) << 20U) +#define gr_crstr_gpc_map_tile5_f(v) (((v)&0x1fU) << 25U) +#define gr_crstr_map_table_cfg_r() (0x00418bb8U) +#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_r(i)\ + (nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) +#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) +#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_gcc_pagepool_r() (0x00419008U) +#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) +#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() (0x00419ea8U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() (0x00504728U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f()\ + (0x4U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f()\ + (0x20U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f()\ + (0x100U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\ + (0x200U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f()\ + (0x800U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f() (0x2000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f() (0x4000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f()\ + (0x8000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f()\ + (0x10000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\ + (0x40000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f()\ + (0x800000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f()\ + (0x400000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f()\ + (0x4000000U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r() (0x00419d0cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f() (0x1U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U) +#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) +#define gr_gpcs_gpccs_gpc_exception_en_gcc_f(v) (((v)&0x1U) << 2U) +#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) +#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) +#define gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_r() (0x00504704U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m() (U32(0x1U) << 0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f() (0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v() (0x00000000U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m() (U32(0x1U) << 3U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_gpc0_tpc0_sm0_warp_valid_mask_0_r() (0x00504708U) +#define gr_gpc0_tpc0_sm0_warp_valid_mask_1_r() (0x0050470cU) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r() (0x00504710U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r() (0x00504714U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r() (0x00504718U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r() (0x0050471cU) +#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r() (0x00419e90U) +#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r() (0x00419e94U) +#define gr_gpcs_tpcs_sms_dbgr_status0_r() (0x00419e80U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_r() (0x00504700U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(r) (((r) >> 4U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v() (0x00000001U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_r() (0x00504730U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v() (0x00000000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f() (0x0U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f() (0x1U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f() (0x2U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f() (0x4U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f() (0x5U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f() (0x6U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f() (0x8U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f() (0x9U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f() (0xbU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f() (0xdU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f() (0xeU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f() (0xfU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f() (0x12U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f() (0x16U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f() (0x17U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f() (0x18U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f() (0x19U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m() (U32(0xffU) << 16U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m() (U32(0xfU) << 24U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r() (0x0050460cU) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() (0x00504738U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() (0x0050473cU) +#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x005043a0U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419ba0U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) +#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x005043b0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419bb0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) +#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) +#define gr_ppcs_wwdx_map_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) +#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ + (((v)&0x1fU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ + (((v)&0x7U) << 21U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_r(i)\ + (nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v() (0x00000005U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(v) (((v)&0xffU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(v) (((v)&0xffU) << 24U) +#define gr_bes_zrop_settings_r() (0x00408850U) +#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_be0_crop_debug3_r() (0x00410108U) +#define gr_bes_crop_debug3_r() (0x00408908U) +#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) +#define gr_bes_crop_debug3_blendopt_read_suppress_m() (U32(0x1U) << 1U) +#define gr_bes_crop_debug3_blendopt_read_suppress_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_read_suppress_enabled_f() (0x2U) +#define gr_bes_crop_debug3_blendopt_fill_override_m() (U32(0x1U) << 2U) +#define gr_bes_crop_debug3_blendopt_fill_override_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_fill_override_enabled_f() (0x4U) +#define gr_bes_crop_debug4_r() (0x0040894cU) +#define gr_bes_crop_debug4_clamp_fp_blend_m() (U32(0x1U) << 18U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) +#define gr_bes_crop_settings_r() (0x00408958U) +#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) +#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) +#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) +#define gr_zcull_subregion_qty_v() (0x00000010U) +#define gr_gpcs_tpcs_tex_in_dbg_r() (0x00419a00U) +#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(v) (((v)&0x1U) << 19U) +#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m() (U32(0x1U) << 19U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_r() (0x00419bf0U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(v) (((v)&0x1U) << 5U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m() (U32(0x1U) << 5U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(v) (((v)&0x1U) << 10U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m() (U32(0x1U) << 10U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m() (U32(0x1U) << 28U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f() (0x10000000U) +#define gr_fe_pwr_mode_r() (0x00404170U) +#define gr_fe_pwr_mode_mode_auto_f() (0x0U) +#define gr_fe_pwr_mode_mode_force_on_f() (0x2U) +#define gr_fe_pwr_mode_req_v(r) (((r) >> 4U) & 0x1U) +#define gr_fe_pwr_mode_req_send_f() (0x10U) +#define gr_fe_pwr_mode_req_done_v() (0x00000000U) +#define gr_gpcs_pri_mmu_ctrl_r() (0x00418880U) +#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() (U32(0x1U) << 0U) +#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() (U32(0x1U) << 11U) +#define gr_gpcs_pri_mmu_ctrl_vol_fault_m() (U32(0x1U) << 1U) +#define gr_gpcs_pri_mmu_ctrl_comp_fault_m() (U32(0x1U) << 2U) +#define gr_gpcs_pri_mmu_ctrl_miss_gran_m() (U32(0x3U) << 3U) +#define gr_gpcs_pri_mmu_ctrl_cache_mode_m() (U32(0x3U) << 5U) +#define gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() (U32(0x3U) << 28U) +#define gr_gpcs_pri_mmu_ctrl_mmu_vol_m() (U32(0x1U) << 30U) +#define gr_gpcs_pri_mmu_ctrl_mmu_disable_m() (U32(0x1U) << 31U) +#define gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_rmw_f() (0x2000000U) +#define gr_gpcs_pri_mmu_pm_unit_mask_r() (0x00418890U) +#define gr_gpcs_pri_mmu_pm_req_mask_r() (0x00418894U) +#define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define gr_gpcs_pri_mmu_debug_wr_r() (0x004188b4U) +#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) +#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) +#define gr_gpcs_tpcs_sms_dbgr_control0_r() (0x00419e84U) +#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) +#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) +#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419bd8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ + (((v)&0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_disp_ctrl_r() (0x00419ba4U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) +#define gr_gpcs_tc_debug0_r() (0x00418708U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h index 1d1bce4a3..092cf4549 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,276 +59,75 @@ #include #include -static inline u32 ioctrl_reset_r(void) -{ - return 0x00000140U; -} -static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void) -{ - return 0x00000008U; -} -static inline u32 ioctrl_reset_linkreset_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 ioctrl_reset_linkreset_m(void) -{ - return U32(0x3fU) << 8U; -} -static inline u32 ioctrl_reset_linkreset_v(u32 r) -{ - return (r >> 8U) & 0x3fU; -} -static inline u32 ioctrl_debug_reset_r(void) -{ - return 0x00000144U; -} -static inline u32 ioctrl_debug_reset_link_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ioctrl_debug_reset_link_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 ioctrl_debug_reset_link_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 ioctrl_debug_reset_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_debug_reset_common_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 ioctrl_debug_reset_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_clock_control_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ioctrl_clock_control__size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 ioctrl_clock_control_clkdis_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_top_intr_0_status_r(void) -{ - return 0x00000200U; -} -static inline u32 ioctrl_top_intr_0_status_link_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 ioctrl_top_intr_0_status_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_r(void) -{ - return 0x00000220U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_r(void) -{ - return 0x00000224U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000240U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000244U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} +#define ioctrl_reset_r() (0x00000140U) +#define ioctrl_reset_sw_post_reset_delay_microseconds_v() (0x00000008U) +#define ioctrl_reset_linkreset_f(v) (((v)&0x3fU) << 8U) +#define ioctrl_reset_linkreset_m() (U32(0x3fU) << 8U) +#define ioctrl_reset_linkreset_v(r) (((r) >> 8U) & 0x3fU) +#define ioctrl_debug_reset_r() (0x00000144U) +#define ioctrl_debug_reset_link_f(v) (((v)&0x3fU) << 0U) +#define ioctrl_debug_reset_link_m() (U32(0x3fU) << 0U) +#define ioctrl_debug_reset_link_v(r) (((r) >> 0U) & 0x3fU) +#define ioctrl_debug_reset_common_f(v) (((v)&0x1U) << 31U) +#define ioctrl_debug_reset_common_m() (U32(0x1U) << 31U) +#define ioctrl_debug_reset_common_v(r) (((r) >> 31U) & 0x1U) +#define ioctrl_clock_control_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) +#define ioctrl_clock_control__size_1_v() (0x00000006U) +#define ioctrl_clock_control_clkdis_f(v) (((v)&0x1U) << 0U) +#define ioctrl_clock_control_clkdis_m() (U32(0x1U) << 0U) +#define ioctrl_clock_control_clkdis_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_top_intr_0_status_r() (0x00000200U) +#define ioctrl_top_intr_0_status_link_f(v) (((v)&0x3fU) << 0U) +#define ioctrl_top_intr_0_status_link_m() (U32(0x3fU) << 0U) +#define ioctrl_top_intr_0_status_link_v(r) (((r) >> 0U) & 0x3fU) +#define ioctrl_top_intr_0_status_common_f(v) (((v)&0x1U) << 31U) +#define ioctrl_top_intr_0_status_common_m() (U32(0x1U) << 31U) +#define ioctrl_top_intr_0_status_common_v(r) (((r) >> 31U) & 0x1U) +#define ioctrl_common_intr_0_mask_r() (0x00000220U) +#define ioctrl_common_intr_0_mask_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_common_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_common_intr_0_mask_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_common_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_common_intr_0_mask_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_common_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_common_intr_0_mask_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_common_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_common_intr_0_mask_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_common_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U) +#define ioctrl_common_intr_0_status_r() (0x00000224U) +#define ioctrl_common_intr_0_status_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_common_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_common_intr_0_status_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_common_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_common_intr_0_status_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_common_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_common_intr_0_status_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_common_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_common_intr_0_status_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_common_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U) +#define ioctrl_link_intr_0_mask_r(i)\ + (nvgpu_safe_add_u32(0x00000240U, nvgpu_safe_mult_u32((i), 20U))) +#define ioctrl_link_intr_0_mask_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_link_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_link_intr_0_mask_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_link_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_link_intr_0_mask_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_link_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_link_intr_0_mask_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_link_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_link_intr_0_mask_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_link_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U) +#define ioctrl_link_intr_0_status_r(i)\ + (nvgpu_safe_add_u32(0x00000244U, nvgpu_safe_mult_u32((i), 20U))) +#define ioctrl_link_intr_0_status_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_link_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_link_intr_0_status_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_link_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_link_intr_0_status_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_link_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_link_intr_0_status_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_link_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_link_intr_0_status_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_link_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h index b88bb8e6e..ed69759fb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,276 +59,78 @@ #include #include -static inline u32 ioctrlmif_rx_err_contain_en_0_r(void) -{ - return 0x00000e0cU; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f(void) -{ - return 0x8U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f(void) -{ - return 0x10U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_r(void) -{ - return 0x00000e04U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_r(void) -{ - return 0x00000e00U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_first_0_r(void) -{ - return 0x00000e14U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_r(void) -{ - return 0x00000a90U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f(void) -{ - return 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f(void) -{ - return 0x2U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_r(void) -{ - return 0x00000a88U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_r(void) -{ - return 0x00000a84U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_first_0_r(void) -{ - return 0x00000a98U; -} -static inline u32 ioctrlmif_tx_ctrl_buffer_ready_r(void) -{ - return 0x00000a7cU; -} -static inline u32 ioctrlmif_rx_ctrl_buffer_ready_r(void) -{ - return 0x00000dfcU; -} +#define ioctrlmif_rx_err_contain_en_0_r() (0x00000e0cU) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(r)\ + (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v() (0x00000001U) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f() (0x8U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(r)\ + (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v() (0x00000001U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f() (0x10U) +#define ioctrlmif_rx_err_log_en_0_r() (0x00000e04U) +#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_report_en_0_r() (0x00000e08U) +#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(r)\ + (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_status_0_r() (0x00000e00U) +#define ioctrlmif_rx_err_status_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_status_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_status_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_first_0_r() (0x00000e14U) +#define ioctrlmif_tx_err_contain_en_0_r() (0x00000a90U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(r)\ + (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v() (0x00000001U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f() (0x1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(r)\ + (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v() (0x00000001U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f() (0x2U) +#define ioctrlmif_tx_err_log_en_0_r() (0x00000a88U) +#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_report_en_0_r() (0x00000e08U) +#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(r)\ + (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_status_0_r() (0x00000a84U) +#define ioctrlmif_tx_err_status_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_status_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_status_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_status_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_status_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_status_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_first_0_r() (0x00000a98U) +#define ioctrlmif_tx_ctrl_buffer_ready_r() (0x00000a7cU) +#define ioctrlmif_rx_ctrl_buffer_ready_r() (0x00000dfcU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h index 2f06e819a..cb6c37455 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,528 +59,165 @@ #include #include -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) -{ - return 0x0017e204U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) -{ - return 8U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} +#define ltc_pltcg_base_v() (0x00140000U) +#define ltc_pltcg_extent_v() (0x0017ffffU) +#define ltc_ltc0_ltss_v() (0x00140200U) +#define ltc_ltc0_lts0_v() (0x00140400U) +#define ltc_ltcs_ltss_v() (0x0017e200U) +#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U) +#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U) +#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U) +#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U) +#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U) +#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU) +#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) +#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) +#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU) +#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) +#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) +#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs__v(r) (((r) >> 0U) & 0x1fU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(v)\ + (((v)&0x1U) << 24U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(r)\ + (((r) >> 24U) & 0x1U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(v) (((v)&0x1U) << 25U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(r) (((r) >> 25U) & 0x1U) +#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U) +#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U) +#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param2_r() (0x0017e3f4U) +#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) +#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ + (((v)&0x1fU) << 16U) +#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ + (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ + (U32(0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffffffffU) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r() (0x0017e204U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s() (8U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(v)\ + (((v)&0xffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m() (U32(0xffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U) +#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U) +#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U) +#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltcs_ltss_intr_r() (0x0017e20cU) +#define ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() (0x100U) +#define ltc_ltcs_ltss_intr_ecc_ded_error_pending_f() (0x200U) +#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f() (0x200000U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f() (0x0U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U) +#define ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() (0x1000000U) +#define ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f() (0x2000000U) +#define ltc_ltc0_lts0_intr_r() (0x0014040cU) +#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU) +#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\ + (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\ + (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\ + (0x40000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\ + (((r) >> 16U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U) +#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltc0_lts0_tstg_info_1_r() (0x0014058cU) +#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index 49bc9d2b7..b46f8a6b9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,204 +59,59 @@ #include #include -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_nvlink_pending_f(void) -{ - return 0x400000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_enable_nvdec_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvdec_enabled_f(void) -{ - return 0x8000U; -} -static inline u32 mc_enable_nvlink_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvlink_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_enable_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_nvlink_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} +#define mc_boot_0_r() (0x00000000U) +#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU) +#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU) +#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU) +#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU) +#define mc_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_pfifo_pending_f() (0x100U) +#define mc_intr_hub_pending_f() (0x200U) +#define mc_intr_pgraph_pending_f() (0x1000U) +#define mc_intr_pmu_pending_f() (0x1000000U) +#define mc_intr_ltc_pending_f() (0x2000000U) +#define mc_intr_priv_ring_pending_f() (0x40000000U) +#define mc_intr_pbus_pending_f() (0x10000000U) +#define mc_intr_nvlink_pending_f() (0x400000U) +#define mc_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_clear_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_enable_r() (0x00000200U) +#define mc_enable_xbar_enabled_f() (0x4U) +#define mc_enable_l2_enabled_f() (0x8U) +#define mc_enable_pmedia_s() (1U) +#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) +#define mc_enable_pmedia_m() (U32(0x1U) << 4U) +#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) +#define mc_enable_ce0_m() (U32(0x1U) << 6U) +#define mc_enable_pfifo_enabled_f() (0x100U) +#define mc_enable_pgraph_enabled_f() (0x1000U) +#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U) +#define mc_enable_pwr_disabled_v() (0x00000000U) +#define mc_enable_pwr_enabled_f() (0x2000U) +#define mc_enable_pfb_enabled_f() (0x100000U) +#define mc_enable_ce2_m() (U32(0x1U) << 21U) +#define mc_enable_ce2_enabled_f() (0x200000U) +#define mc_enable_blg_enabled_f() (0x8000000U) +#define mc_enable_perfmon_enabled_f() (0x10000000U) +#define mc_enable_hub_enabled_f() (0x20000000U) +#define mc_enable_nvdec_disabled_v() (0x00000000U) +#define mc_enable_nvdec_enabled_f() (0x8000U) +#define mc_enable_nvlink_disabled_v() (0x00000000U) +#define mc_enable_nvlink_disabled_f() (0x0U) +#define mc_enable_nvlink_enabled_v() (0x00000001U) +#define mc_enable_nvlink_enabled_f() (0x2000000U) +#define mc_intr_ltc_r() (0x000001c0U) +#define mc_enable_pb_r() (0x00000204U) +#define mc_enable_pb_0_s() (1U) +#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) +#define mc_enable_pb_0_m() (U32(0x1U) << 0U) +#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) +#define mc_enable_pb_0_enabled_v() (0x00000001U) +#define mc_enable_pb_sel_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h index b01b276eb..4e612ef7b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,904 +59,231 @@ #include #include -static inline u32 minion_minion_status_r(void) -{ - return 0x00000830U; -} -static inline u32 minion_minion_status_status_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_minion_status_status_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 minion_minion_status_status_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_minion_status_status_boot_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_status_status_boot_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_status_intr_code_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 minion_minion_status_intr_code_m(void) -{ - return U32(0xffffffU) << 8U; -} -static inline u32 minion_minion_status_intr_code_v(u32 r) -{ - return (r >> 8U) & 0xffffffU; -} -static inline u32 minion_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 minion_falcon_irqstat_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqstat_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqstat_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqstat_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqstat_exterr_true_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 minion_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 minion_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqmset_halt_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 minion_falcon_irqmset_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_halt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_halt_set_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_exterr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_exterr_set_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 minion_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 minion_minion_intr_r(void) -{ - return 0x00000810U; -} -static inline u32 minion_minion_intr_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_fatal_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 minion_minion_intr_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_nonfatal_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_minion_intr_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_link_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 minion_minion_intr_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_minion_intr_nonstall_en_r(void) -{ - return 0x0000081cU; -} -static inline u32 minion_minion_intr_stall_en_r(void) -{ - return 0x00000818U; -} -static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_f(void) -{ - return 0x2U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_f(void) -{ - return 0x4U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_f(void) -{ - return 0x8U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_nvlink_dl_cmd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000900U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 minion_nvlink_dl_cmd___size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 minion_nvlink_dl_cmd_command_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_dl_cmd_command_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_v(void) -{ - return 0x00000040U; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_f(void) -{ - return 0x40U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_v(void) -{ - return 0x00000003U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_f(void) -{ - return 0x3U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_v(void) -{ - return 0x00000004U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_f(void) -{ - return 0x4U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_v(void) -{ - return 0x00000008U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_f(void) -{ - return 0x8U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_v(void) -{ - return 0x00000009U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_f(void) -{ - return 0x9U; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_v(void) -{ - return 0x0000000cU; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_f(void) -{ - return 0xcU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_v(void) -{ - return 0x0000000aU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_f(void) -{ - return 0xaU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_v(void) -{ - return 0x0000000bU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_f(void) -{ - return 0xbU; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_v(void) -{ - return 0x00000010U; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_f(void) -{ - return 0x10U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_v(void) -{ - return 0x00000011U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_f(void) -{ - return 0x11U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_v(void) -{ - return 0x00000018U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_f(void) -{ - return 0x18U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_v(void) -{ - return 0x00000019U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_f(void) -{ - return 0x19U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_v(void) -{ - return 0x00000020U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_f(void) -{ - return 0x20U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_v(void) -{ - return 0x00000021U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_f(void) -{ - return 0x21U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_v(void) -{ - return 0x00000022U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_f(void) -{ - return 0x22U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_v(void) -{ - return 0x00000023U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_f(void) -{ - return 0x23U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_v(void) -{ - return 0x00000024U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_f(void) -{ - return 0x24U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_v(void) -{ - return 0x00000025U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_f(void) -{ - return 0x25U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_v(void) -{ - return 0x00000026U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_f(void) -{ - return 0x26U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_v(void) -{ - return 0x00000027U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_f(void) -{ - return 0x27U; -} -static inline u32 minion_nvlink_dl_cmd_fault_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_fault_fault_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_dl_cmd_ready_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 minion_misc_0_r(void) -{ - return 0x000008b0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 minion_nvlink_link_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000a00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 minion_nvlink_link_intr___size_1_v(void) -{ - return 0x00000006U; -} -static inline u32 minion_nvlink_link_intr_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_link_intr_code_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 minion_nvlink_link_intr_code_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_code_na_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_link_intr_code_na_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_f(void) -{ - return 0x2U; -} -static inline u32 minion_nvlink_link_intr_code_pmdisabled_v(void) -{ - return 0x00000003U; -} -static inline u32 minion_nvlink_link_intr_code_pmdisabled_f(void) -{ - return 0x3U; -} -static inline u32 minion_nvlink_link_intr_subcode_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_state_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_link_intr_state_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 minion_nvlink_link_intr_state_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 minion_falcon_csberrstat_r(void) -{ - return 0x00000244U; -} -static inline u32 minion_falcon_csberr_info_r(void) -{ - return 0x00000248U; -} -static inline u32 minion_falcon_csberr_addr_r(void) -{ - return 0x0000024cU; -} +#define minion_minion_status_r() (0x00000830U) +#define minion_minion_status_status_f(v) (((v)&0xffU) << 0U) +#define minion_minion_status_status_m() (U32(0xffU) << 0U) +#define minion_minion_status_status_v(r) (((r) >> 0U) & 0xffU) +#define minion_minion_status_status_boot_v() (0x00000001U) +#define minion_minion_status_status_boot_f() (0x1U) +#define minion_minion_status_intr_code_f(v) (((v)&0xffffffU) << 8U) +#define minion_minion_status_intr_code_m() (U32(0xffffffU) << 8U) +#define minion_minion_status_intr_code_v(r) (((r) >> 8U) & 0xffffffU) +#define minion_falcon_irqstat_r() (0x00000008U) +#define minion_falcon_irqstat_halt_f(v) (((v)&0x1U) << 4U) +#define minion_falcon_irqstat_halt_v(r) (((r) >> 4U) & 0x1U) +#define minion_falcon_irqstat_exterr_f(v) (((v)&0x1U) << 5U) +#define minion_falcon_irqstat_exterr_v(r) (((r) >> 5U) & 0x1U) +#define minion_falcon_irqstat_exterr_true_v() (0x00000001U) +#define minion_falcon_irqstat_exterr_true_f() (0x20U) +#define minion_falcon_irqmask_r() (0x00000018U) +#define minion_falcon_irqsclr_r() (0x00000004U) +#define minion_falcon_irqsset_r() (0x00000000U) +#define minion_falcon_irqmset_r() (0x00000010U) +#define minion_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define minion_falcon_irqmset_wdtmr_m() (U32(0x1U) << 1U) +#define minion_falcon_irqmset_wdtmr_v(r) (((r) >> 1U) & 0x1U) +#define minion_falcon_irqmset_wdtmr_set_v() (0x00000001U) +#define minion_falcon_irqmset_wdtmr_set_f() (0x2U) +#define minion_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define minion_falcon_irqmset_halt_m() (U32(0x1U) << 4U) +#define minion_falcon_irqmset_halt_v(r) (((r) >> 4U) & 0x1U) +#define minion_falcon_irqmset_halt_set_v() (0x00000001U) +#define minion_falcon_irqmset_halt_set_f() (0x10U) +#define minion_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define minion_falcon_irqmset_exterr_m() (U32(0x1U) << 5U) +#define minion_falcon_irqmset_exterr_v(r) (((r) >> 5U) & 0x1U) +#define minion_falcon_irqmset_exterr_set_v() (0x00000001U) +#define minion_falcon_irqmset_exterr_set_f() (0x20U) +#define minion_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define minion_falcon_irqmset_swgen0_m() (U32(0x1U) << 6U) +#define minion_falcon_irqmset_swgen0_v(r) (((r) >> 6U) & 0x1U) +#define minion_falcon_irqmset_swgen0_set_v() (0x00000001U) +#define minion_falcon_irqmset_swgen0_set_f() (0x40U) +#define minion_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define minion_falcon_irqmset_swgen1_m() (U32(0x1U) << 7U) +#define minion_falcon_irqmset_swgen1_v(r) (((r) >> 7U) & 0x1U) +#define minion_falcon_irqmset_swgen1_set_v() (0x00000001U) +#define minion_falcon_irqmset_swgen1_set_f() (0x80U) +#define minion_falcon_irqdest_r() (0x0000001cU) +#define minion_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define minion_falcon_irqdest_host_wdtmr_m() (U32(0x1U) << 1U) +#define minion_falcon_irqdest_host_wdtmr_v(r) (((r) >> 1U) & 0x1U) +#define minion_falcon_irqdest_host_wdtmr_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_wdtmr_host_f() (0x2U) +#define minion_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define minion_falcon_irqdest_host_halt_m() (U32(0x1U) << 4U) +#define minion_falcon_irqdest_host_halt_v(r) (((r) >> 4U) & 0x1U) +#define minion_falcon_irqdest_host_halt_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_halt_host_f() (0x10U) +#define minion_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define minion_falcon_irqdest_host_exterr_m() (U32(0x1U) << 5U) +#define minion_falcon_irqdest_host_exterr_v(r) (((r) >> 5U) & 0x1U) +#define minion_falcon_irqdest_host_exterr_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_exterr_host_f() (0x20U) +#define minion_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define minion_falcon_irqdest_host_swgen0_m() (U32(0x1U) << 6U) +#define minion_falcon_irqdest_host_swgen0_v(r) (((r) >> 6U) & 0x1U) +#define minion_falcon_irqdest_host_swgen0_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_swgen0_host_f() (0x40U) +#define minion_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define minion_falcon_irqdest_host_swgen1_m() (U32(0x1U) << 7U) +#define minion_falcon_irqdest_host_swgen1_v(r) (((r) >> 7U) & 0x1U) +#define minion_falcon_irqdest_host_swgen1_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_swgen1_host_f() (0x80U) +#define minion_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define minion_falcon_irqdest_target_wdtmr_m() (U32(0x1U) << 17U) +#define minion_falcon_irqdest_target_wdtmr_v(r) (((r) >> 17U) & 0x1U) +#define minion_falcon_irqdest_target_wdtmr_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_wdtmr_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define minion_falcon_irqdest_target_halt_m() (U32(0x1U) << 20U) +#define minion_falcon_irqdest_target_halt_v(r) (((r) >> 20U) & 0x1U) +#define minion_falcon_irqdest_target_halt_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_halt_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define minion_falcon_irqdest_target_exterr_m() (U32(0x1U) << 21U) +#define minion_falcon_irqdest_target_exterr_v(r) (((r) >> 21U) & 0x1U) +#define minion_falcon_irqdest_target_exterr_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_exterr_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define minion_falcon_irqdest_target_swgen0_m() (U32(0x1U) << 22U) +#define minion_falcon_irqdest_target_swgen0_v(r) (((r) >> 22U) & 0x1U) +#define minion_falcon_irqdest_target_swgen0_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_swgen0_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define minion_falcon_irqdest_target_swgen1_m() (U32(0x1U) << 23U) +#define minion_falcon_irqdest_target_swgen1_v(r) (((r) >> 23U) & 0x1U) +#define minion_falcon_irqdest_target_swgen1_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_swgen1_host_normal_f() (0x0U) +#define minion_falcon_os_r() (0x00000080U) +#define minion_falcon_mailbox1_r() (0x00000044U) +#define minion_minion_intr_r() (0x00000810U) +#define minion_minion_intr_fatal_f(v) (((v)&0x1U) << 0U) +#define minion_minion_intr_fatal_m() (U32(0x1U) << 0U) +#define minion_minion_intr_fatal_v(r) (((r) >> 0U) & 0x1U) +#define minion_minion_intr_nonfatal_f(v) (((v)&0x1U) << 1U) +#define minion_minion_intr_nonfatal_m() (U32(0x1U) << 1U) +#define minion_minion_intr_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define minion_minion_intr_falcon_stall_f(v) (((v)&0x1U) << 2U) +#define minion_minion_intr_falcon_stall_m() (U32(0x1U) << 2U) +#define minion_minion_intr_falcon_stall_v(r) (((r) >> 2U) & 0x1U) +#define minion_minion_intr_falcon_nostall_f(v) (((v)&0x1U) << 3U) +#define minion_minion_intr_falcon_nostall_m() (U32(0x1U) << 3U) +#define minion_minion_intr_falcon_nostall_v(r) (((r) >> 3U) & 0x1U) +#define minion_minion_intr_link_f(v) (((v)&0xffffU) << 16U) +#define minion_minion_intr_link_m() (U32(0xffffU) << 16U) +#define minion_minion_intr_link_v(r) (((r) >> 16U) & 0xffffU) +#define minion_minion_intr_nonstall_en_r() (0x0000081cU) +#define minion_minion_intr_stall_en_r() (0x00000818U) +#define minion_minion_intr_stall_en_fatal_f(v) (((v)&0x1U) << 0U) +#define minion_minion_intr_stall_en_fatal_m() (U32(0x1U) << 0U) +#define minion_minion_intr_stall_en_fatal_v(r) (((r) >> 0U) & 0x1U) +#define minion_minion_intr_stall_en_fatal_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_fatal_enable_f() (0x1U) +#define minion_minion_intr_stall_en_fatal_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_fatal_disable_f() (0x0U) +#define minion_minion_intr_stall_en_nonfatal_f(v) (((v)&0x1U) << 1U) +#define minion_minion_intr_stall_en_nonfatal_m() (U32(0x1U) << 1U) +#define minion_minion_intr_stall_en_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define minion_minion_intr_stall_en_nonfatal_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_nonfatal_enable_f() (0x2U) +#define minion_minion_intr_stall_en_nonfatal_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_nonfatal_disable_f() (0x0U) +#define minion_minion_intr_stall_en_falcon_stall_f(v) (((v)&0x1U) << 2U) +#define minion_minion_intr_stall_en_falcon_stall_m() (U32(0x1U) << 2U) +#define minion_minion_intr_stall_en_falcon_stall_v(r) (((r) >> 2U) & 0x1U) +#define minion_minion_intr_stall_en_falcon_stall_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_falcon_stall_enable_f() (0x4U) +#define minion_minion_intr_stall_en_falcon_stall_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_falcon_stall_disable_f() (0x0U) +#define minion_minion_intr_stall_en_falcon_nostall_f(v) (((v)&0x1U) << 3U) +#define minion_minion_intr_stall_en_falcon_nostall_m() (U32(0x1U) << 3U) +#define minion_minion_intr_stall_en_falcon_nostall_v(r) (((r) >> 3U) & 0x1U) +#define minion_minion_intr_stall_en_falcon_nostall_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_falcon_nostall_enable_f() (0x8U) +#define minion_minion_intr_stall_en_falcon_nostall_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_falcon_nostall_disable_f() (0x0U) +#define minion_minion_intr_stall_en_link_f(v) (((v)&0xffffU) << 16U) +#define minion_minion_intr_stall_en_link_m() (U32(0xffffU) << 16U) +#define minion_minion_intr_stall_en_link_v(r) (((r) >> 16U) & 0xffffU) +#define minion_nvlink_dl_cmd_r(i)\ + (nvgpu_safe_add_u32(0x00000900U, nvgpu_safe_mult_u32((i), 4U))) +#define minion_nvlink_dl_cmd___size_1_v() (0x00000006U) +#define minion_nvlink_dl_cmd_command_f(v) (((v)&0xffU) << 0U) +#define minion_nvlink_dl_cmd_command_v(r) (((r) >> 0U) & 0xffU) +#define minion_nvlink_dl_cmd_command_configeom_v() (0x00000040U) +#define minion_nvlink_dl_cmd_command_configeom_f() (0x40U) +#define minion_nvlink_dl_cmd_command_nop_v() (0x00000000U) +#define minion_nvlink_dl_cmd_command_nop_f() (0x0U) +#define minion_nvlink_dl_cmd_command_initphy_v() (0x00000001U) +#define minion_nvlink_dl_cmd_command_initphy_f() (0x1U) +#define minion_nvlink_dl_cmd_command_initlaneenable_v() (0x00000003U) +#define minion_nvlink_dl_cmd_command_initlaneenable_f() (0x3U) +#define minion_nvlink_dl_cmd_command_initdlpl_v() (0x00000004U) +#define minion_nvlink_dl_cmd_command_initdlpl_f() (0x4U) +#define minion_nvlink_dl_cmd_command_lanedisable_v() (0x00000008U) +#define minion_nvlink_dl_cmd_command_lanedisable_f() (0x8U) +#define minion_nvlink_dl_cmd_command_fastlanedisable_v() (0x00000009U) +#define minion_nvlink_dl_cmd_command_fastlanedisable_f() (0x9U) +#define minion_nvlink_dl_cmd_command_laneshutdown_v() (0x0000000cU) +#define minion_nvlink_dl_cmd_command_laneshutdown_f() (0xcU) +#define minion_nvlink_dl_cmd_command_setacmode_v() (0x0000000aU) +#define minion_nvlink_dl_cmd_command_setacmode_f() (0xaU) +#define minion_nvlink_dl_cmd_command_clracmode_v() (0x0000000bU) +#define minion_nvlink_dl_cmd_command_clracmode_f() (0xbU) +#define minion_nvlink_dl_cmd_command_enablepm_v() (0x00000010U) +#define minion_nvlink_dl_cmd_command_enablepm_f() (0x10U) +#define minion_nvlink_dl_cmd_command_disablepm_v() (0x00000011U) +#define minion_nvlink_dl_cmd_command_disablepm_f() (0x11U) +#define minion_nvlink_dl_cmd_command_savestate_v() (0x00000018U) +#define minion_nvlink_dl_cmd_command_savestate_f() (0x18U) +#define minion_nvlink_dl_cmd_command_restorestate_v() (0x00000019U) +#define minion_nvlink_dl_cmd_command_restorestate_f() (0x19U) +#define minion_nvlink_dl_cmd_command_initpll_0_v() (0x00000020U) +#define minion_nvlink_dl_cmd_command_initpll_0_f() (0x20U) +#define minion_nvlink_dl_cmd_command_initpll_1_v() (0x00000021U) +#define minion_nvlink_dl_cmd_command_initpll_1_f() (0x21U) +#define minion_nvlink_dl_cmd_command_initpll_2_v() (0x00000022U) +#define minion_nvlink_dl_cmd_command_initpll_2_f() (0x22U) +#define minion_nvlink_dl_cmd_command_initpll_3_v() (0x00000023U) +#define minion_nvlink_dl_cmd_command_initpll_3_f() (0x23U) +#define minion_nvlink_dl_cmd_command_initpll_4_v() (0x00000024U) +#define minion_nvlink_dl_cmd_command_initpll_4_f() (0x24U) +#define minion_nvlink_dl_cmd_command_initpll_5_v() (0x00000025U) +#define minion_nvlink_dl_cmd_command_initpll_5_f() (0x25U) +#define minion_nvlink_dl_cmd_command_initpll_6_v() (0x00000026U) +#define minion_nvlink_dl_cmd_command_initpll_6_f() (0x26U) +#define minion_nvlink_dl_cmd_command_initpll_7_v() (0x00000027U) +#define minion_nvlink_dl_cmd_command_initpll_7_f() (0x27U) +#define minion_nvlink_dl_cmd_fault_f(v) (((v)&0x1U) << 30U) +#define minion_nvlink_dl_cmd_fault_v(r) (((r) >> 30U) & 0x1U) +#define minion_nvlink_dl_cmd_fault_fault_clear_v() (0x00000001U) +#define minion_nvlink_dl_cmd_ready_f(v) (((v)&0x1U) << 31U) +#define minion_nvlink_dl_cmd_ready_v(r) (((r) >> 31U) & 0x1U) +#define minion_misc_0_r() (0x000008b0U) +#define minion_misc_0_scratch_swrw_0_f(v) (((v)&0xffffffffU) << 0U) +#define minion_misc_0_scratch_swrw_0_v(r) (((r) >> 0U) & 0xffffffffU) +#define minion_nvlink_link_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000a00U, nvgpu_safe_mult_u32((i), 4U))) +#define minion_nvlink_link_intr___size_1_v() (0x00000006U) +#define minion_nvlink_link_intr_code_f(v) (((v)&0xffU) << 0U) +#define minion_nvlink_link_intr_code_m() (U32(0xffU) << 0U) +#define minion_nvlink_link_intr_code_v(r) (((r) >> 0U) & 0xffU) +#define minion_nvlink_link_intr_code_na_v() (0x00000000U) +#define minion_nvlink_link_intr_code_na_f() (0x0U) +#define minion_nvlink_link_intr_code_swreq_v() (0x00000001U) +#define minion_nvlink_link_intr_code_swreq_f() (0x1U) +#define minion_nvlink_link_intr_code_dlreq_v() (0x00000002U) +#define minion_nvlink_link_intr_code_dlreq_f() (0x2U) +#define minion_nvlink_link_intr_code_pmdisabled_v() (0x00000003U) +#define minion_nvlink_link_intr_code_pmdisabled_f() (0x3U) +#define minion_nvlink_link_intr_subcode_f(v) (((v)&0xffU) << 8U) +#define minion_nvlink_link_intr_subcode_m() (U32(0xffU) << 8U) +#define minion_nvlink_link_intr_subcode_v(r) (((r) >> 8U) & 0xffU) +#define minion_nvlink_link_intr_state_f(v) (((v)&0x1U) << 31U) +#define minion_nvlink_link_intr_state_m() (U32(0x1U) << 31U) +#define minion_nvlink_link_intr_state_v(r) (((r) >> 31U) & 0x1U) +#define minion_falcon_csberrstat_r() (0x00000244U) +#define minion_falcon_csberr_info_r() (0x00000248U) +#define minion_falcon_csberr_addr_r() (0x0000024cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h index 98e11fae0..34f586cee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,1516 +59,383 @@ #include #include -static inline u32 nvl_link_state_r(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 nvl_link_state_state_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 nvl_link_state_state_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 nvl_link_state_state_init_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_init_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_state_state_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_state_state_hwcfg_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_state_state_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_state_state_swcfg_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_state_state_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_state_state_active_f(void) -{ - return 0x3U; -} -static inline u32 nvl_link_state_state_fault_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_link_state_state_fault_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_state_state_rcvy_ac_v(void) -{ - return 0x00000008U; -} -static inline u32 nvl_link_state_state_rcvy_ac_f(void) -{ - return 0x8U; -} -static inline u32 nvl_link_state_state_rcvy_sw_v(void) -{ - return 0x00000009U; -} -static inline u32 nvl_link_state_state_rcvy_sw_f(void) -{ - return 0x9U; -} -static inline u32 nvl_link_state_state_rcvy_rx_v(void) -{ - return 0x0000000aU; -} -static inline u32 nvl_link_state_state_rcvy_rx_f(void) -{ - return 0xaU; -} -static inline u32 nvl_link_state_an0_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvl_link_state_an0_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 nvl_link_state_an0_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvl_link_state_tl_busy_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvl_link_state_tl_busy_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 nvl_link_state_tl_busy_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvl_link_state_dbg_substate_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 nvl_link_state_dbg_substate_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 nvl_link_state_dbg_substate_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 nvl_link_activity_r(void) -{ - return 0x0000000cU; -} -static inline u32 nvl_link_activity_blkact_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_link_activity_blkact_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 nvl_link_activity_blkact_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 nvl_sublink_activity_blkact0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_blkact1_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_m(void) -{ - return U32(0x7U) << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_v(u32 r) -{ - return (r >> 8U) & 0x7U; -} -static inline u32 nvl_link_config_r(void) -{ - return 0x00000018U; -} -static inline u32 nvl_link_config_ac_safe_en_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_config_ac_safe_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_ac_safe_en_on_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_config_link_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_config_link_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 nvl_link_config_link_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_config_link_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_link_en_on_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_link_change_r(void) -{ - return 0x00000040U; -} -static inline u32 nvl_link_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_link_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_link_change_newstate_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_link_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_link_change_newstate_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_newstate_hwcfg_f(void) -{ - return 0x10U; -} -static inline u32 nvl_link_change_newstate_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_newstate_swcfg_f(void) -{ - return 0x20U; -} -static inline u32 nvl_link_change_newstate_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_change_newstate_active_f(void) -{ - return 0x30U; -} -static inline u32 nvl_link_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_link_change_action_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 nvl_link_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_link_change_action_ltssm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_action_ltssm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_link_change_status_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 nvl_link_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_link_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_sublink_change_r(void) -{ - return 0x00000044U; -} -static inline u32 nvl_sublink_change_countdown_f(u32 v) -{ - return (v & 0xfffU) << 20U; -} -static inline u32 nvl_sublink_change_countdown_m(void) -{ - return U32(0xfffU) << 20U; -} -static inline u32 nvl_sublink_change_countdown_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_sublink_change_sublink_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 nvl_sublink_change_sublink_m(void) -{ - return U32(0xfU) << 12U; -} -static inline u32 nvl_sublink_change_sublink_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 nvl_sublink_change_sublink_tx_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_sublink_tx_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_sublink_rx_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_sublink_rx_f(void) -{ - return 0x1000U; -} -static inline u32 nvl_sublink_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sublink_change_newstate_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_sublink_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sublink_change_newstate_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_newstate_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_newstate_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sublink_change_newstate_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sublink_change_newstate_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sublink_change_newstate_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sublink_change_newstate_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sublink_change_newstate_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sublink_change_newstate_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sublink_change_newstate_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sublink_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_sublink_change_action_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 nvl_sublink_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_sublink_change_action_slsm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_action_slsm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_sublink_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_sublink_change_status_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 nvl_sublink_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_sublink_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_sublink_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_sublink_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_test_r(void) -{ - return 0x00000048U; -} -static inline u32 nvl_link_test_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_link_test_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_link_test_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_link_test_mode_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_test_auto_nvhs_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_r(void) -{ - return 0x00002024U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl1_slsm_status_rx_r(void) -{ - return 0x00003014U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_r(void) -{ - return 0x00002008U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void) -{ - return 0x00000728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void) -{ - return 0x728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v) -{ - return (v & 0x1fU) << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void) -{ - return U32(0x1fU) << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r) -{ - return (r >> 11U) & 0x1fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void) -{ - return 0x7800U; -} -static inline u32 nvl_sl1_error_rate_ctrl_r(void) -{ - return 0x00003284U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void) -{ - return U32(0x7U) << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 nvl_sl1_rxslsm_timeout_2_r(void) -{ - return 0x00003034U; -} -static inline u32 nvl_txiobist_configreg_r(void) -{ - return 0x00002e14U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvl_txiobist_config_r(void) -{ - return 0x00002e10U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_r(void) -{ - return 0x00000050U; -} -static inline u32 nvl_intr_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_tx_replay_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_intr_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_ltssm_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 nvl_intr_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_request_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_intr_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_sw2_r(void) -{ - return 0x00000054U; -} -static inline u32 nvl_intr_minion_r(void) -{ - return 0x00000060U; -} -static inline u32 nvl_intr_minion_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_minion_request_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_intr_minion_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_nonstall_en_r(void) -{ - return 0x0000005cU; -} -static inline u32 nvl_intr_stall_en_r(void) -{ - return 0x00000058U; -} -static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void) -{ - return 0x2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void) -{ - return 0x4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void) -{ - return 0x10U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void) -{ - return 0x20U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void) -{ - return 0x100U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void) -{ - return 0x10000U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void) -{ - return 0x100000U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void) -{ - return 0x200000U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void) -{ - return 0x400000U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void) -{ - return 0x800000U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void) -{ - return 0x1000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 nvl_intr_stall_en_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_br0_cfg_cal_r(void) -{ - return 0x0000281cU; -} -static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void) -{ - return 0x1U; -} -static inline u32 nvl_br0_cfg_status_cal_r(void) -{ - return 0x00002838U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} +#define nvl_link_state_r() (0x00000000U) +#define nvl_link_state_state_f(v) (((v)&0xffU) << 0U) +#define nvl_link_state_state_m() (U32(0xffU) << 0U) +#define nvl_link_state_state_v(r) (((r) >> 0U) & 0xffU) +#define nvl_link_state_state_init_v() (0x00000000U) +#define nvl_link_state_state_init_f() (0x0U) +#define nvl_link_state_state_hwcfg_v() (0x00000001U) +#define nvl_link_state_state_hwcfg_f() (0x1U) +#define nvl_link_state_state_swcfg_v() (0x00000002U) +#define nvl_link_state_state_swcfg_f() (0x2U) +#define nvl_link_state_state_active_v() (0x00000003U) +#define nvl_link_state_state_active_f() (0x3U) +#define nvl_link_state_state_fault_v() (0x00000004U) +#define nvl_link_state_state_fault_f() (0x4U) +#define nvl_link_state_state_rcvy_ac_v() (0x00000008U) +#define nvl_link_state_state_rcvy_ac_f() (0x8U) +#define nvl_link_state_state_rcvy_sw_v() (0x00000009U) +#define nvl_link_state_state_rcvy_sw_f() (0x9U) +#define nvl_link_state_state_rcvy_rx_v() (0x0000000aU) +#define nvl_link_state_state_rcvy_rx_f() (0xaU) +#define nvl_link_state_an0_busy_f(v) (((v)&0x1U) << 12U) +#define nvl_link_state_an0_busy_m() (U32(0x1U) << 12U) +#define nvl_link_state_an0_busy_v(r) (((r) >> 12U) & 0x1U) +#define nvl_link_state_tl_busy_f(v) (((v)&0x1U) << 13U) +#define nvl_link_state_tl_busy_m() (U32(0x1U) << 13U) +#define nvl_link_state_tl_busy_v(r) (((r) >> 13U) & 0x1U) +#define nvl_link_state_dbg_substate_f(v) (((v)&0xffffU) << 16U) +#define nvl_link_state_dbg_substate_m() (U32(0xffffU) << 16U) +#define nvl_link_state_dbg_substate_v(r) (((r) >> 16U) & 0xffffU) +#define nvl_link_activity_r() (0x0000000cU) +#define nvl_link_activity_blkact_f(v) (((v)&0x7U) << 0U) +#define nvl_link_activity_blkact_m() (U32(0x7U) << 0U) +#define nvl_link_activity_blkact_v(r) (((r) >> 0U) & 0x7U) +#define nvl_sublink_activity_r(i)\ + (nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32((i), 4U))) +#define nvl_sublink_activity_blkact0_f(v) (((v)&0x7U) << 0U) +#define nvl_sublink_activity_blkact0_m() (U32(0x7U) << 0U) +#define nvl_sublink_activity_blkact0_v(r) (((r) >> 0U) & 0x7U) +#define nvl_sublink_activity_blkact1_f(v) (((v)&0x7U) << 8U) +#define nvl_sublink_activity_blkact1_m() (U32(0x7U) << 8U) +#define nvl_sublink_activity_blkact1_v(r) (((r) >> 8U) & 0x7U) +#define nvl_link_config_r() (0x00000018U) +#define nvl_link_config_ac_safe_en_f(v) (((v)&0x1U) << 30U) +#define nvl_link_config_ac_safe_en_m() (U32(0x1U) << 30U) +#define nvl_link_config_ac_safe_en_v(r) (((r) >> 30U) & 0x1U) +#define nvl_link_config_ac_safe_en_on_v() (0x00000001U) +#define nvl_link_config_ac_safe_en_on_f() (0x40000000U) +#define nvl_link_config_link_en_f(v) (((v)&0x1U) << 31U) +#define nvl_link_config_link_en_m() (U32(0x1U) << 31U) +#define nvl_link_config_link_en_v(r) (((r) >> 31U) & 0x1U) +#define nvl_link_config_link_en_on_v() (0x00000001U) +#define nvl_link_config_link_en_on_f() (0x80000000U) +#define nvl_link_change_r() (0x00000040U) +#define nvl_link_change_oldstate_mask_f(v) (((v)&0xfU) << 16U) +#define nvl_link_change_oldstate_mask_m() (U32(0xfU) << 16U) +#define nvl_link_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU) +#define nvl_link_change_oldstate_mask_dontcare_v() (0x0000000fU) +#define nvl_link_change_oldstate_mask_dontcare_f() (0xf0000U) +#define nvl_link_change_newstate_f(v) (((v)&0xfU) << 4U) +#define nvl_link_change_newstate_m() (U32(0xfU) << 4U) +#define nvl_link_change_newstate_v(r) (((r) >> 4U) & 0xfU) +#define nvl_link_change_newstate_hwcfg_v() (0x00000001U) +#define nvl_link_change_newstate_hwcfg_f() (0x10U) +#define nvl_link_change_newstate_swcfg_v() (0x00000002U) +#define nvl_link_change_newstate_swcfg_f() (0x20U) +#define nvl_link_change_newstate_active_v() (0x00000003U) +#define nvl_link_change_newstate_active_f() (0x30U) +#define nvl_link_change_action_f(v) (((v)&0x3U) << 2U) +#define nvl_link_change_action_m() (U32(0x3U) << 2U) +#define nvl_link_change_action_v(r) (((r) >> 2U) & 0x3U) +#define nvl_link_change_action_ltssm_change_v() (0x00000001U) +#define nvl_link_change_action_ltssm_change_f() (0x4U) +#define nvl_link_change_status_f(v) (((v)&0x3U) << 0U) +#define nvl_link_change_status_m() (U32(0x3U) << 0U) +#define nvl_link_change_status_v(r) (((r) >> 0U) & 0x3U) +#define nvl_link_change_status_done_v() (0x00000000U) +#define nvl_link_change_status_done_f() (0x0U) +#define nvl_link_change_status_busy_v() (0x00000001U) +#define nvl_link_change_status_busy_f() (0x1U) +#define nvl_link_change_status_fault_v() (0x00000002U) +#define nvl_link_change_status_fault_f() (0x2U) +#define nvl_sublink_change_r() (0x00000044U) +#define nvl_sublink_change_countdown_f(v) (((v)&0xfffU) << 20U) +#define nvl_sublink_change_countdown_m() (U32(0xfffU) << 20U) +#define nvl_sublink_change_countdown_v(r) (((r) >> 20U) & 0xfffU) +#define nvl_sublink_change_oldstate_mask_f(v) (((v)&0xfU) << 16U) +#define nvl_sublink_change_oldstate_mask_m() (U32(0xfU) << 16U) +#define nvl_sublink_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU) +#define nvl_sublink_change_oldstate_mask_dontcare_v() (0x0000000fU) +#define nvl_sublink_change_oldstate_mask_dontcare_f() (0xf0000U) +#define nvl_sublink_change_sublink_f(v) (((v)&0xfU) << 12U) +#define nvl_sublink_change_sublink_m() (U32(0xfU) << 12U) +#define nvl_sublink_change_sublink_v(r) (((r) >> 12U) & 0xfU) +#define nvl_sublink_change_sublink_tx_v() (0x00000000U) +#define nvl_sublink_change_sublink_tx_f() (0x0U) +#define nvl_sublink_change_sublink_rx_v() (0x00000001U) +#define nvl_sublink_change_sublink_rx_f() (0x1000U) +#define nvl_sublink_change_newstate_f(v) (((v)&0xfU) << 4U) +#define nvl_sublink_change_newstate_m() (U32(0xfU) << 4U) +#define nvl_sublink_change_newstate_v(r) (((r) >> 4U) & 0xfU) +#define nvl_sublink_change_newstate_hs_v() (0x00000000U) +#define nvl_sublink_change_newstate_hs_f() (0x0U) +#define nvl_sublink_change_newstate_eighth_v() (0x00000004U) +#define nvl_sublink_change_newstate_eighth_f() (0x40U) +#define nvl_sublink_change_newstate_train_v() (0x00000005U) +#define nvl_sublink_change_newstate_train_f() (0x50U) +#define nvl_sublink_change_newstate_safe_v() (0x00000006U) +#define nvl_sublink_change_newstate_safe_f() (0x60U) +#define nvl_sublink_change_newstate_off_v() (0x00000007U) +#define nvl_sublink_change_newstate_off_f() (0x70U) +#define nvl_sublink_change_action_f(v) (((v)&0x3U) << 2U) +#define nvl_sublink_change_action_m() (U32(0x3U) << 2U) +#define nvl_sublink_change_action_v(r) (((r) >> 2U) & 0x3U) +#define nvl_sublink_change_action_slsm_change_v() (0x00000001U) +#define nvl_sublink_change_action_slsm_change_f() (0x4U) +#define nvl_sublink_change_status_f(v) (((v)&0x3U) << 0U) +#define nvl_sublink_change_status_m() (U32(0x3U) << 0U) +#define nvl_sublink_change_status_v(r) (((r) >> 0U) & 0x3U) +#define nvl_sublink_change_status_done_v() (0x00000000U) +#define nvl_sublink_change_status_done_f() (0x0U) +#define nvl_sublink_change_status_busy_v() (0x00000001U) +#define nvl_sublink_change_status_busy_f() (0x1U) +#define nvl_sublink_change_status_fault_v() (0x00000002U) +#define nvl_sublink_change_status_fault_f() (0x2U) +#define nvl_link_test_r() (0x00000048U) +#define nvl_link_test_mode_f(v) (((v)&0x1U) << 0U) +#define nvl_link_test_mode_m() (U32(0x1U) << 0U) +#define nvl_link_test_mode_v(r) (((r) >> 0U) & 0x1U) +#define nvl_link_test_mode_enable_v() (0x00000001U) +#define nvl_link_test_mode_enable_f() (0x1U) +#define nvl_link_test_auto_hwcfg_f(v) (((v)&0x1U) << 30U) +#define nvl_link_test_auto_hwcfg_m() (U32(0x1U) << 30U) +#define nvl_link_test_auto_hwcfg_v(r) (((r) >> 30U) & 0x1U) +#define nvl_link_test_auto_hwcfg_enable_v() (0x00000001U) +#define nvl_link_test_auto_hwcfg_enable_f() (0x40000000U) +#define nvl_link_test_auto_nvhs_f(v) (((v)&0x1U) << 31U) +#define nvl_link_test_auto_nvhs_m() (U32(0x1U) << 31U) +#define nvl_link_test_auto_nvhs_v(r) (((r) >> 31U) & 0x1U) +#define nvl_link_test_auto_nvhs_enable_v() (0x00000001U) +#define nvl_link_test_auto_nvhs_enable_f() (0x80000000U) +#define nvl_sl0_slsm_status_tx_r() (0x00002024U) +#define nvl_sl0_slsm_status_tx_substate_f(v) (((v)&0xfU) << 0U) +#define nvl_sl0_slsm_status_tx_substate_m() (U32(0xfU) << 0U) +#define nvl_sl0_slsm_status_tx_substate_v(r) (((r) >> 0U) & 0xfU) +#define nvl_sl0_slsm_status_tx_primary_state_f(v) (((v)&0xfU) << 4U) +#define nvl_sl0_slsm_status_tx_primary_state_m() (U32(0xfU) << 4U) +#define nvl_sl0_slsm_status_tx_primary_state_v(r) (((r) >> 4U) & 0xfU) +#define nvl_sl0_slsm_status_tx_primary_state_hs_v() (0x00000000U) +#define nvl_sl0_slsm_status_tx_primary_state_hs_f() (0x0U) +#define nvl_sl0_slsm_status_tx_primary_state_eighth_v() (0x00000004U) +#define nvl_sl0_slsm_status_tx_primary_state_eighth_f() (0x40U) +#define nvl_sl0_slsm_status_tx_primary_state_train_v() (0x00000005U) +#define nvl_sl0_slsm_status_tx_primary_state_train_f() (0x50U) +#define nvl_sl0_slsm_status_tx_primary_state_off_v() (0x00000007U) +#define nvl_sl0_slsm_status_tx_primary_state_off_f() (0x70U) +#define nvl_sl0_slsm_status_tx_primary_state_safe_v() (0x00000006U) +#define nvl_sl0_slsm_status_tx_primary_state_safe_f() (0x60U) +#define nvl_sl1_slsm_status_rx_r() (0x00003014U) +#define nvl_sl1_slsm_status_rx_substate_f(v) (((v)&0xfU) << 0U) +#define nvl_sl1_slsm_status_rx_substate_m() (U32(0xfU) << 0U) +#define nvl_sl1_slsm_status_rx_substate_v(r) (((r) >> 0U) & 0xfU) +#define nvl_sl1_slsm_status_rx_primary_state_f(v) (((v)&0xfU) << 4U) +#define nvl_sl1_slsm_status_rx_primary_state_m() (U32(0xfU) << 4U) +#define nvl_sl1_slsm_status_rx_primary_state_v(r) (((r) >> 4U) & 0xfU) +#define nvl_sl1_slsm_status_rx_primary_state_hs_v() (0x00000000U) +#define nvl_sl1_slsm_status_rx_primary_state_hs_f() (0x0U) +#define nvl_sl1_slsm_status_rx_primary_state_eighth_v() (0x00000004U) +#define nvl_sl1_slsm_status_rx_primary_state_eighth_f() (0x40U) +#define nvl_sl1_slsm_status_rx_primary_state_train_v() (0x00000005U) +#define nvl_sl1_slsm_status_rx_primary_state_train_f() (0x50U) +#define nvl_sl1_slsm_status_rx_primary_state_off_v() (0x00000007U) +#define nvl_sl1_slsm_status_rx_primary_state_off_f() (0x70U) +#define nvl_sl1_slsm_status_rx_primary_state_safe_v() (0x00000006U) +#define nvl_sl1_slsm_status_rx_primary_state_safe_f() (0x60U) +#define nvl_sl0_safe_ctrl2_tx_r() (0x00002008U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_f(v) (((v)&0x7ffU) << 0U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_m() (U32(0x7ffU) << 0U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_v(r) (((r) >> 0U) & 0x7ffU) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_init_v() (0x00000728U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_init_f() (0x728U) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(v) (((v)&0x1fU) << 11U) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_m() (U32(0x1fU) << 11U) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(r) (((r) >> 11U) & 0x1fU) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v() (0x0000000fU) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f() (0x7800U) +#define nvl_sl1_error_rate_ctrl_r() (0x00003284U) +#define nvl_sl1_error_rate_ctrl_short_threshold_man_f(v) (((v)&0x7U) << 0U) +#define nvl_sl1_error_rate_ctrl_short_threshold_man_m() (U32(0x7U) << 0U) +#define nvl_sl1_error_rate_ctrl_short_threshold_man_v(r) (((r) >> 0U) & 0x7U) +#define nvl_sl1_error_rate_ctrl_long_threshold_man_f(v) (((v)&0x7U) << 16U) +#define nvl_sl1_error_rate_ctrl_long_threshold_man_m() (U32(0x7U) << 16U) +#define nvl_sl1_error_rate_ctrl_long_threshold_man_v(r) (((r) >> 16U) & 0x7U) +#define nvl_sl1_rxslsm_timeout_2_r() (0x00003034U) +#define nvl_txiobist_configreg_r() (0x00002e14U) +#define nvl_txiobist_configreg_io_bist_mode_in_f(v) (((v)&0x1U) << 17U) +#define nvl_txiobist_configreg_io_bist_mode_in_m() (U32(0x1U) << 17U) +#define nvl_txiobist_configreg_io_bist_mode_in_v(r) (((r) >> 17U) & 0x1U) +#define nvl_txiobist_config_r() (0x00002e10U) +#define nvl_txiobist_config_dpg_prbsseedld_f(v) (((v)&0x1U) << 2U) +#define nvl_txiobist_config_dpg_prbsseedld_m() (U32(0x1U) << 2U) +#define nvl_txiobist_config_dpg_prbsseedld_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_r() (0x00000050U) +#define nvl_intr_tx_replay_f(v) (((v)&0x1U) << 0U) +#define nvl_intr_tx_replay_m() (U32(0x1U) << 0U) +#define nvl_intr_tx_replay_v(r) (((r) >> 0U) & 0x1U) +#define nvl_intr_tx_recovery_short_f(v) (((v)&0x1U) << 1U) +#define nvl_intr_tx_recovery_short_m() (U32(0x1U) << 1U) +#define nvl_intr_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) +#define nvl_intr_tx_recovery_long_f(v) (((v)&0x1U) << 2U) +#define nvl_intr_tx_recovery_long_m() (U32(0x1U) << 2U) +#define nvl_intr_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_tx_fault_ram_f(v) (((v)&0x1U) << 4U) +#define nvl_intr_tx_fault_ram_m() (U32(0x1U) << 4U) +#define nvl_intr_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) +#define nvl_intr_tx_fault_interface_f(v) (((v)&0x1U) << 5U) +#define nvl_intr_tx_fault_interface_m() (U32(0x1U) << 5U) +#define nvl_intr_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) +#define nvl_intr_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) +#define nvl_intr_tx_fault_sublink_change_m() (U32(0x1U) << 8U) +#define nvl_intr_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) +#define nvl_intr_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) +#define nvl_intr_rx_fault_sublink_change_m() (U32(0x1U) << 16U) +#define nvl_intr_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) +#define nvl_intr_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) +#define nvl_intr_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) +#define nvl_intr_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) +#define nvl_intr_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) +#define nvl_intr_rx_short_error_rate_m() (U32(0x1U) << 21U) +#define nvl_intr_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) +#define nvl_intr_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) +#define nvl_intr_rx_long_error_rate_m() (U32(0x1U) << 22U) +#define nvl_intr_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) +#define nvl_intr_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) +#define nvl_intr_rx_ila_trigger_m() (U32(0x1U) << 23U) +#define nvl_intr_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) +#define nvl_intr_rx_crc_counter_f(v) (((v)&0x1U) << 24U) +#define nvl_intr_rx_crc_counter_m() (U32(0x1U) << 24U) +#define nvl_intr_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) +#define nvl_intr_ltssm_fault_f(v) (((v)&0x1U) << 28U) +#define nvl_intr_ltssm_fault_m() (U32(0x1U) << 28U) +#define nvl_intr_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) +#define nvl_intr_ltssm_protocol_f(v) (((v)&0x1U) << 29U) +#define nvl_intr_ltssm_protocol_m() (U32(0x1U) << 29U) +#define nvl_intr_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) +#define nvl_intr_minion_request_f(v) (((v)&0x1U) << 30U) +#define nvl_intr_minion_request_m() (U32(0x1U) << 30U) +#define nvl_intr_minion_request_v(r) (((r) >> 30U) & 0x1U) +#define nvl_intr_sw2_r() (0x00000054U) +#define nvl_intr_minion_r() (0x00000060U) +#define nvl_intr_minion_tx_replay_f(v) (((v)&0x1U) << 0U) +#define nvl_intr_minion_tx_replay_m() (U32(0x1U) << 0U) +#define nvl_intr_minion_tx_replay_v(r) (((r) >> 0U) & 0x1U) +#define nvl_intr_minion_tx_recovery_short_f(v) (((v)&0x1U) << 1U) +#define nvl_intr_minion_tx_recovery_short_m() (U32(0x1U) << 1U) +#define nvl_intr_minion_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) +#define nvl_intr_minion_tx_recovery_long_f(v) (((v)&0x1U) << 2U) +#define nvl_intr_minion_tx_recovery_long_m() (U32(0x1U) << 2U) +#define nvl_intr_minion_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_minion_tx_fault_ram_f(v) (((v)&0x1U) << 4U) +#define nvl_intr_minion_tx_fault_ram_m() (U32(0x1U) << 4U) +#define nvl_intr_minion_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) +#define nvl_intr_minion_tx_fault_interface_f(v) (((v)&0x1U) << 5U) +#define nvl_intr_minion_tx_fault_interface_m() (U32(0x1U) << 5U) +#define nvl_intr_minion_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) +#define nvl_intr_minion_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) +#define nvl_intr_minion_tx_fault_sublink_change_m() (U32(0x1U) << 8U) +#define nvl_intr_minion_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) +#define nvl_intr_minion_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) +#define nvl_intr_minion_rx_fault_sublink_change_m() (U32(0x1U) << 16U) +#define nvl_intr_minion_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) +#define nvl_intr_minion_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) +#define nvl_intr_minion_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) +#define nvl_intr_minion_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) +#define nvl_intr_minion_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) +#define nvl_intr_minion_rx_short_error_rate_m() (U32(0x1U) << 21U) +#define nvl_intr_minion_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) +#define nvl_intr_minion_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) +#define nvl_intr_minion_rx_long_error_rate_m() (U32(0x1U) << 22U) +#define nvl_intr_minion_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) +#define nvl_intr_minion_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) +#define nvl_intr_minion_rx_ila_trigger_m() (U32(0x1U) << 23U) +#define nvl_intr_minion_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) +#define nvl_intr_minion_rx_crc_counter_f(v) (((v)&0x1U) << 24U) +#define nvl_intr_minion_rx_crc_counter_m() (U32(0x1U) << 24U) +#define nvl_intr_minion_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) +#define nvl_intr_minion_ltssm_fault_f(v) (((v)&0x1U) << 28U) +#define nvl_intr_minion_ltssm_fault_m() (U32(0x1U) << 28U) +#define nvl_intr_minion_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) +#define nvl_intr_minion_ltssm_protocol_f(v) (((v)&0x1U) << 29U) +#define nvl_intr_minion_ltssm_protocol_m() (U32(0x1U) << 29U) +#define nvl_intr_minion_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) +#define nvl_intr_minion_minion_request_f(v) (((v)&0x1U) << 30U) +#define nvl_intr_minion_minion_request_m() (U32(0x1U) << 30U) +#define nvl_intr_minion_minion_request_v(r) (((r) >> 30U) & 0x1U) +#define nvl_intr_nonstall_en_r() (0x0000005cU) +#define nvl_intr_stall_en_r() (0x00000058U) +#define nvl_intr_stall_en_tx_replay_f(v) (((v)&0x1U) << 0U) +#define nvl_intr_stall_en_tx_replay_m() (U32(0x1U) << 0U) +#define nvl_intr_stall_en_tx_replay_v(r) (((r) >> 0U) & 0x1U) +#define nvl_intr_stall_en_tx_recovery_short_f(v) (((v)&0x1U) << 1U) +#define nvl_intr_stall_en_tx_recovery_short_m() (U32(0x1U) << 1U) +#define nvl_intr_stall_en_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) +#define nvl_intr_stall_en_tx_recovery_short_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_recovery_short_enable_f() (0x2U) +#define nvl_intr_stall_en_tx_recovery_long_f(v) (((v)&0x1U) << 2U) +#define nvl_intr_stall_en_tx_recovery_long_m() (U32(0x1U) << 2U) +#define nvl_intr_stall_en_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_stall_en_tx_recovery_long_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_recovery_long_enable_f() (0x4U) +#define nvl_intr_stall_en_tx_fault_ram_f(v) (((v)&0x1U) << 4U) +#define nvl_intr_stall_en_tx_fault_ram_m() (U32(0x1U) << 4U) +#define nvl_intr_stall_en_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) +#define nvl_intr_stall_en_tx_fault_ram_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_fault_ram_enable_f() (0x10U) +#define nvl_intr_stall_en_tx_fault_interface_f(v) (((v)&0x1U) << 5U) +#define nvl_intr_stall_en_tx_fault_interface_m() (U32(0x1U) << 5U) +#define nvl_intr_stall_en_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) +#define nvl_intr_stall_en_tx_fault_interface_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_fault_interface_enable_f() (0x20U) +#define nvl_intr_stall_en_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) +#define nvl_intr_stall_en_tx_fault_sublink_change_m() (U32(0x1U) << 8U) +#define nvl_intr_stall_en_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) +#define nvl_intr_stall_en_tx_fault_sublink_change_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_fault_sublink_change_enable_f() (0x100U) +#define nvl_intr_stall_en_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) +#define nvl_intr_stall_en_rx_fault_sublink_change_m() (U32(0x1U) << 16U) +#define nvl_intr_stall_en_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) +#define nvl_intr_stall_en_rx_fault_sublink_change_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_fault_sublink_change_enable_f() (0x10000U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_enable_f() (0x100000U) +#define nvl_intr_stall_en_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) +#define nvl_intr_stall_en_rx_short_error_rate_m() (U32(0x1U) << 21U) +#define nvl_intr_stall_en_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) +#define nvl_intr_stall_en_rx_short_error_rate_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_short_error_rate_enable_f() (0x200000U) +#define nvl_intr_stall_en_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) +#define nvl_intr_stall_en_rx_long_error_rate_m() (U32(0x1U) << 22U) +#define nvl_intr_stall_en_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) +#define nvl_intr_stall_en_rx_long_error_rate_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_long_error_rate_enable_f() (0x400000U) +#define nvl_intr_stall_en_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) +#define nvl_intr_stall_en_rx_ila_trigger_m() (U32(0x1U) << 23U) +#define nvl_intr_stall_en_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) +#define nvl_intr_stall_en_rx_ila_trigger_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_ila_trigger_enable_f() (0x800000U) +#define nvl_intr_stall_en_rx_crc_counter_f(v) (((v)&0x1U) << 24U) +#define nvl_intr_stall_en_rx_crc_counter_m() (U32(0x1U) << 24U) +#define nvl_intr_stall_en_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) +#define nvl_intr_stall_en_rx_crc_counter_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_crc_counter_enable_f() (0x1000000U) +#define nvl_intr_stall_en_ltssm_fault_f(v) (((v)&0x1U) << 28U) +#define nvl_intr_stall_en_ltssm_fault_m() (U32(0x1U) << 28U) +#define nvl_intr_stall_en_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) +#define nvl_intr_stall_en_ltssm_fault_enable_v() (0x00000001U) +#define nvl_intr_stall_en_ltssm_fault_enable_f() (0x10000000U) +#define nvl_intr_stall_en_ltssm_protocol_f(v) (((v)&0x1U) << 29U) +#define nvl_intr_stall_en_ltssm_protocol_m() (U32(0x1U) << 29U) +#define nvl_intr_stall_en_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) +#define nvl_intr_stall_en_ltssm_protocol_enable_v() (0x00000001U) +#define nvl_intr_stall_en_ltssm_protocol_enable_f() (0x20000000U) +#define nvl_intr_stall_en_minion_request_f(v) (((v)&0x1U) << 30U) +#define nvl_intr_stall_en_minion_request_m() (U32(0x1U) << 30U) +#define nvl_intr_stall_en_minion_request_v(r) (((r) >> 30U) & 0x1U) +#define nvl_intr_stall_en_minion_request_enable_v() (0x00000001U) +#define nvl_intr_stall_en_minion_request_enable_f() (0x40000000U) +#define nvl_br0_cfg_cal_r() (0x0000281cU) +#define nvl_br0_cfg_cal_rxcal_f(v) (((v)&0x1U) << 0U) +#define nvl_br0_cfg_cal_rxcal_m() (U32(0x1U) << 0U) +#define nvl_br0_cfg_cal_rxcal_v(r) (((r) >> 0U) & 0x1U) +#define nvl_br0_cfg_cal_rxcal_on_v() (0x00000001U) +#define nvl_br0_cfg_cal_rxcal_on_f() (0x1U) +#define nvl_br0_cfg_status_cal_r() (0x00002838U) +#define nvl_br0_cfg_status_cal_rxcal_done_f(v) (((v)&0x1U) << 2U) +#define nvl_br0_cfg_status_cal_rxcal_done_m() (U32(0x1U) << 2U) +#define nvl_br0_cfg_status_cal_rxcal_done_v(r) (((r) >> 2U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h index 8650ba525..9a622112b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,252 +59,68 @@ #include #include -static inline u32 nvlinkip_discovery_common_entry_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvlinkip_discovery_common_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvlinkip_discovery_common_entry_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 nvlinkip_discovery_common_entry_enum_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_entry_data1_v(void) -{ - return 0x00000002U; -} -static inline u32 nvlinkip_discovery_common_entry_data2_v(void) -{ - return 0x00000003U; -} -static inline u32 nvlinkip_discovery_common_contents_f(u32 v) -{ - return (v & 0x1fffffffU) << 2U; -} -static inline u32 nvlinkip_discovery_common_contents_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 nvlinkip_discovery_common_chain_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvlinkip_discovery_common_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvlinkip_discovery_common_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_device_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 nvlinkip_discovery_common_device_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 nvlinkip_discovery_common_device_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 nvlinkip_discovery_common_device_ioctrl_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_device_nvltl_v(void) -{ - return 0x00000002U; -} -static inline u32 nvlinkip_discovery_common_device_nvlink_v(void) -{ - return 0x00000003U; -} -static inline u32 nvlinkip_discovery_common_device_minion_v(void) -{ - return 0x00000004U; -} -static inline u32 nvlinkip_discovery_common_device_nvlipt_v(void) -{ - return 0x00000005U; -} -static inline u32 nvlinkip_discovery_common_device_nvltlc_v(void) -{ - return 0x00000006U; -} -static inline u32 nvlinkip_discovery_common_device_dlpl_v(void) -{ - return 0x0000000bU; -} -static inline u32 nvlinkip_discovery_common_device_ioctrlmif_v(void) -{ - return 0x00000007U; -} -static inline u32 nvlinkip_discovery_common_device_dlpl_multicast_v(void) -{ - return 0x00000008U; -} -static inline u32 nvlinkip_discovery_common_device_nvltlc_multicast_v(void) -{ - return 0x00000009U; -} -static inline u32 nvlinkip_discovery_common_device_ioctrlmif_multicast_v(void) -{ - return 0x0000000aU; -} -static inline u32 nvlinkip_discovery_common_device_sioctrl_v(void) -{ - return 0x0000000cU; -} -static inline u32 nvlinkip_discovery_common_device_tioctrl_v(void) -{ - return 0x0000000dU; -} -static inline u32 nvlinkip_discovery_common_id_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 nvlinkip_discovery_common_id_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 nvlinkip_discovery_common_version_f(u32 v) -{ - return (v & 0x7ffU) << 20U; -} -static inline u32 nvlinkip_discovery_common_version_v(u32 r) -{ - return (r >> 20U) & 0x7ffU; -} -static inline u32 nvlinkip_discovery_common_pri_base_f(u32 v) -{ - return (v & 0xfffU) << 12U; -} -static inline u32 nvlinkip_discovery_common_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 nvlinkip_discovery_common_intr_f(u32 v) -{ - return (v & 0x1fU) << 7U; -} -static inline u32 nvlinkip_discovery_common_intr_v(u32 r) -{ - return (r >> 7U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_reset_f(u32 v) -{ - return (v & 0x1fU) << 2U; -} -static inline u32 nvlinkip_discovery_common_reset_v(u32 r) -{ - return (r >> 2U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_ioctrl_length_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 nvlinkip_discovery_common_ioctrl_length_v(u32 r) -{ - return (r >> 24U) & 0x3fU; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_tx_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_tx_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_rx_f(u32 v) -{ - return (v & 0x7U) << 27U; -} -static inline u32 nvlinkip_discovery_common_dlpl_num_rx_v(u32 r) -{ - return (r >> 27U) & 0x7U; -} -static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_f(u32 v) -{ - return (v & 0x7ffffU) << 12U; -} -static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_v(u32 r) -{ - return (r >> 12U) & 0x7ffffU; -} -static inline u32 nvlinkip_discovery_common_data2_type_f(u32 v) -{ - return (v & 0x1fU) << 26U; -} -static inline u32 nvlinkip_discovery_common_data2_type_v(u32 r) -{ - return (r >> 26U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_data2_type_invalid_v(void) -{ - return 0x00000000U; -} -static inline u32 nvlinkip_discovery_common_data2_type_pllcontrol_v(void) -{ - return 0x00000001U; -} -static inline u32 nvlinkip_discovery_common_data2_type_resetreg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvlinkip_discovery_common_data2_type_intrreg_v(void) -{ - return 0x00000003U; -} -static inline u32 nvlinkip_discovery_common_data2_type_discovery_v(void) -{ - return 0x00000004U; -} -static inline u32 nvlinkip_discovery_common_data2_type_unicast_v(void) -{ - return 0x00000005U; -} -static inline u32 nvlinkip_discovery_common_data2_type_broadcast_v(void) -{ - return 0x00000006U; -} -static inline u32 nvlinkip_discovery_common_data2_addr_f(u32 v) -{ - return (v & 0xffffffU) << 2U; -} -static inline u32 nvlinkip_discovery_common_data2_addr_v(u32 r) -{ - return (r >> 2U) & 0xffffffU; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_type_f(u32 v) -{ - return (v & 0x1fU) << 26U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_type_v(u32 r) -{ - return (r >> 26U) & 0x1fU; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_master_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_master_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_f(u32 v) -{ - return (v & 0x7fU) << 8U; -} -static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} +#define nvlinkip_discovery_common_entry_f(v) (((v)&0x3U) << 0U) +#define nvlinkip_discovery_common_entry_v(r) (((r) >> 0U) & 0x3U) +#define nvlinkip_discovery_common_entry_invalid_v() (0x00000000U) +#define nvlinkip_discovery_common_entry_enum_v() (0x00000001U) +#define nvlinkip_discovery_common_entry_data1_v() (0x00000002U) +#define nvlinkip_discovery_common_entry_data2_v() (0x00000003U) +#define nvlinkip_discovery_common_contents_f(v) (((v)&0x1fffffffU) << 2U) +#define nvlinkip_discovery_common_contents_v(r) (((r) >> 2U) & 0x1fffffffU) +#define nvlinkip_discovery_common_chain_f(v) (((v)&0x1U) << 31U) +#define nvlinkip_discovery_common_chain_v(r) (((r) >> 31U) & 0x1U) +#define nvlinkip_discovery_common_chain_enable_v() (0x00000001U) +#define nvlinkip_discovery_common_device_f(v) (((v)&0x3fU) << 2U) +#define nvlinkip_discovery_common_device_v(r) (((r) >> 2U) & 0x3fU) +#define nvlinkip_discovery_common_device_invalid_v() (0x00000000U) +#define nvlinkip_discovery_common_device_ioctrl_v() (0x00000001U) +#define nvlinkip_discovery_common_device_nvltl_v() (0x00000002U) +#define nvlinkip_discovery_common_device_nvlink_v() (0x00000003U) +#define nvlinkip_discovery_common_device_minion_v() (0x00000004U) +#define nvlinkip_discovery_common_device_nvlipt_v() (0x00000005U) +#define nvlinkip_discovery_common_device_nvltlc_v() (0x00000006U) +#define nvlinkip_discovery_common_device_dlpl_v() (0x0000000bU) +#define nvlinkip_discovery_common_device_ioctrlmif_v() (0x00000007U) +#define nvlinkip_discovery_common_device_dlpl_multicast_v() (0x00000008U) +#define nvlinkip_discovery_common_device_nvltlc_multicast_v() (0x00000009U) +#define nvlinkip_discovery_common_device_ioctrlmif_multicast_v() (0x0000000aU) +#define nvlinkip_discovery_common_device_sioctrl_v() (0x0000000cU) +#define nvlinkip_discovery_common_device_tioctrl_v() (0x0000000dU) +#define nvlinkip_discovery_common_id_f(v) (((v)&0xffU) << 8U) +#define nvlinkip_discovery_common_id_v(r) (((r) >> 8U) & 0xffU) +#define nvlinkip_discovery_common_version_f(v) (((v)&0x7ffU) << 20U) +#define nvlinkip_discovery_common_version_v(r) (((r) >> 20U) & 0x7ffU) +#define nvlinkip_discovery_common_pri_base_f(v) (((v)&0xfffU) << 12U) +#define nvlinkip_discovery_common_pri_base_v(r) (((r) >> 12U) & 0xfffU) +#define nvlinkip_discovery_common_intr_f(v) (((v)&0x1fU) << 7U) +#define nvlinkip_discovery_common_intr_v(r) (((r) >> 7U) & 0x1fU) +#define nvlinkip_discovery_common_reset_f(v) (((v)&0x1fU) << 2U) +#define nvlinkip_discovery_common_reset_v(r) (((r) >> 2U) & 0x1fU) +#define nvlinkip_discovery_common_ioctrl_length_f(v) (((v)&0x3fU) << 24U) +#define nvlinkip_discovery_common_ioctrl_length_v(r) (((r) >> 24U) & 0x3fU) +#define nvlinkip_discovery_common_dlpl_num_tx_f(v) (((v)&0x7U) << 24U) +#define nvlinkip_discovery_common_dlpl_num_tx_v(r) (((r) >> 24U) & 0x7U) +#define nvlinkip_discovery_common_dlpl_num_rx_f(v) (((v)&0x7U) << 27U) +#define nvlinkip_discovery_common_dlpl_num_rx_v(r) (((r) >> 27U) & 0x7U) +#define nvlinkip_discovery_common_data1_ioctrl_length_f(v)\ + (((v)&0x7ffffU) << 12U) +#define nvlinkip_discovery_common_data1_ioctrl_length_v(r)\ + (((r) >> 12U) & 0x7ffffU) +#define nvlinkip_discovery_common_data2_type_f(v) (((v)&0x1fU) << 26U) +#define nvlinkip_discovery_common_data2_type_v(r) (((r) >> 26U) & 0x1fU) +#define nvlinkip_discovery_common_data2_type_invalid_v() (0x00000000U) +#define nvlinkip_discovery_common_data2_type_pllcontrol_v() (0x00000001U) +#define nvlinkip_discovery_common_data2_type_resetreg_v() (0x00000002U) +#define nvlinkip_discovery_common_data2_type_intrreg_v() (0x00000003U) +#define nvlinkip_discovery_common_data2_type_discovery_v() (0x00000004U) +#define nvlinkip_discovery_common_data2_type_unicast_v() (0x00000005U) +#define nvlinkip_discovery_common_data2_type_broadcast_v() (0x00000006U) +#define nvlinkip_discovery_common_data2_addr_f(v) (((v)&0xffffffU) << 2U) +#define nvlinkip_discovery_common_data2_addr_v(r) (((r) >> 2U) & 0xffffffU) +#define nvlinkip_discovery_common_dlpl_data2_type_f(v) (((v)&0x1fU) << 26U) +#define nvlinkip_discovery_common_dlpl_data2_type_v(r) (((r) >> 26U) & 0x1fU) +#define nvlinkip_discovery_common_dlpl_data2_master_f(v) (((v)&0x1U) << 15U) +#define nvlinkip_discovery_common_dlpl_data2_master_v(r) (((r) >> 15U) & 0x1U) +#define nvlinkip_discovery_common_dlpl_data2_masterid_f(v) (((v)&0x7fU) << 8U) +#define nvlinkip_discovery_common_dlpl_data2_masterid_v(r) (((r) >> 8U) & 0x7fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h index fc6408339..b8e63c229 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,224 +59,61 @@ #include #include -static inline u32 nvlipt_intr_control_link0_r(void) -{ - return 0x000004b4U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_r(void) -{ - return 0x00000524U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_v(u32 r) -{ - return (r >> 14U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_v(u32 r) -{ - return (r >> 19U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvlipt_err_uc_mask_link0_r(void) -{ - return 0x00000528U; -} -static inline u32 nvlipt_err_uc_severity_link0_r(void) -{ - return 0x0000052cU; -} -static inline u32 nvlipt_err_uc_first_link0_r(void) -{ - return 0x00000530U; -} -static inline u32 nvlipt_err_uc_advisory_link0_r(void) -{ - return 0x00000534U; -} -static inline u32 nvlipt_err_c_status_link0_r(void) -{ - return 0x00000538U; -} -static inline u32 nvlipt_err_c_mask_link0_r(void) -{ - return 0x0000053cU; -} -static inline u32 nvlipt_err_c_first_link0_r(void) -{ - return 0x00000540U; -} -static inline u32 nvlipt_err_control_link0_r(void) -{ - return 0x00000544U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_r(void) -{ - return 0x000004b0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_scratch_cold_r(void) -{ - return 0x000007d4U; -} -static inline u32 nvlipt_scratch_cold_data_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 nvlipt_scratch_cold_data_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 nvlipt_scratch_cold_data_init_v(void) -{ - return 0xdeadbaadU; -} +#define nvlipt_intr_control_link0_r() (0x000004b4U) +#define nvlipt_intr_control_link0_stallenable_f(v) (((v)&0x1U) << 0U) +#define nvlipt_intr_control_link0_stallenable_m() (U32(0x1U) << 0U) +#define nvlipt_intr_control_link0_stallenable_v(r) (((r) >> 0U) & 0x1U) +#define nvlipt_intr_control_link0_nostallenable_f(v) (((v)&0x1U) << 1U) +#define nvlipt_intr_control_link0_nostallenable_m() (U32(0x1U) << 1U) +#define nvlipt_intr_control_link0_nostallenable_v(r) (((r) >> 1U) & 0x1U) +#define nvlipt_err_uc_status_link0_r() (0x00000524U) +#define nvlipt_err_uc_status_link0_dlprotocol_f(v) (((v)&0x1U) << 4U) +#define nvlipt_err_uc_status_link0_dlprotocol_v(r) (((r) >> 4U) & 0x1U) +#define nvlipt_err_uc_status_link0_datapoisoned_f(v) (((v)&0x1U) << 12U) +#define nvlipt_err_uc_status_link0_datapoisoned_v(r) (((r) >> 12U) & 0x1U) +#define nvlipt_err_uc_status_link0_flowcontrol_f(v) (((v)&0x1U) << 13U) +#define nvlipt_err_uc_status_link0_flowcontrol_v(r) (((r) >> 13U) & 0x1U) +#define nvlipt_err_uc_status_link0_responsetimeout_f(v) (((v)&0x1U) << 14U) +#define nvlipt_err_uc_status_link0_responsetimeout_v(r) (((r) >> 14U) & 0x1U) +#define nvlipt_err_uc_status_link0_targeterror_f(v) (((v)&0x1U) << 15U) +#define nvlipt_err_uc_status_link0_targeterror_v(r) (((r) >> 15U) & 0x1U) +#define nvlipt_err_uc_status_link0_unexpectedresponse_f(v) (((v)&0x1U) << 16U) +#define nvlipt_err_uc_status_link0_unexpectedresponse_v(r) (((r) >> 16U) & 0x1U) +#define nvlipt_err_uc_status_link0_receiveroverflow_f(v) (((v)&0x1U) << 17U) +#define nvlipt_err_uc_status_link0_receiveroverflow_v(r) (((r) >> 17U) & 0x1U) +#define nvlipt_err_uc_status_link0_malformedpacket_f(v) (((v)&0x1U) << 18U) +#define nvlipt_err_uc_status_link0_malformedpacket_v(r) (((r) >> 18U) & 0x1U) +#define nvlipt_err_uc_status_link0_stompedpacketreceived_f(v)\ + (((v)&0x1U) << 19U) +#define nvlipt_err_uc_status_link0_stompedpacketreceived_v(r)\ + (((r) >> 19U) & 0x1U) +#define nvlipt_err_uc_status_link0_unsupportedrequest_f(v) (((v)&0x1U) << 20U) +#define nvlipt_err_uc_status_link0_unsupportedrequest_v(r) (((r) >> 20U) & 0x1U) +#define nvlipt_err_uc_status_link0_ucinternal_f(v) (((v)&0x1U) << 22U) +#define nvlipt_err_uc_status_link0_ucinternal_v(r) (((r) >> 22U) & 0x1U) +#define nvlipt_err_uc_mask_link0_r() (0x00000528U) +#define nvlipt_err_uc_severity_link0_r() (0x0000052cU) +#define nvlipt_err_uc_first_link0_r() (0x00000530U) +#define nvlipt_err_uc_advisory_link0_r() (0x00000534U) +#define nvlipt_err_c_status_link0_r() (0x00000538U) +#define nvlipt_err_c_mask_link0_r() (0x0000053cU) +#define nvlipt_err_c_first_link0_r() (0x00000540U) +#define nvlipt_err_control_link0_r() (0x00000544U) +#define nvlipt_err_control_link0_fatalenable_f(v) (((v)&0x1U) << 1U) +#define nvlipt_err_control_link0_fatalenable_m() (U32(0x1U) << 1U) +#define nvlipt_err_control_link0_fatalenable_v(r) (((r) >> 1U) & 0x1U) +#define nvlipt_err_control_link0_nonfatalenable_f(v) (((v)&0x1U) << 2U) +#define nvlipt_err_control_link0_nonfatalenable_m() (U32(0x1U) << 2U) +#define nvlipt_err_control_link0_nonfatalenable_v(r) (((r) >> 2U) & 0x1U) +#define nvlipt_intr_control_common_r() (0x000004b0U) +#define nvlipt_intr_control_common_stallenable_f(v) (((v)&0x1U) << 0U) +#define nvlipt_intr_control_common_stallenable_m() (U32(0x1U) << 0U) +#define nvlipt_intr_control_common_stallenable_v(r) (((r) >> 0U) & 0x1U) +#define nvlipt_intr_control_common_nonstallenable_f(v) (((v)&0x1U) << 1U) +#define nvlipt_intr_control_common_nonstallenable_m() (U32(0x1U) << 1U) +#define nvlipt_intr_control_common_nonstallenable_v(r) (((r) >> 1U) & 0x1U) +#define nvlipt_scratch_cold_r() (0x000007d4U) +#define nvlipt_scratch_cold_data_f(v) (((v)&0xffffffffU) << 0U) +#define nvlipt_scratch_cold_data_v(r) (((r) >> 0U) & 0xffffffffU) +#define nvlipt_scratch_cold_data_init_v() (0xdeadbaadU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h index ff2bc3477..ed8ff69f5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,40 +59,13 @@ #include #include -static inline u32 nvtlc_tx_err_report_en_0_r(void) -{ - return 0x00000708U; -} -static inline u32 nvtlc_rx_err_report_en_0_r(void) -{ - return 0x00000f08U; -} -static inline u32 nvtlc_rx_err_report_en_1_r(void) -{ - return 0x00000f20U; -} -static inline u32 nvtlc_tx_err_status_0_r(void) -{ - return 0x00000700U; -} -static inline u32 nvtlc_rx_err_status_0_r(void) -{ - return 0x00000f00U; -} -static inline u32 nvtlc_rx_err_status_1_r(void) -{ - return 0x00000f18U; -} -static inline u32 nvtlc_tx_err_first_0_r(void) -{ - return 0x00000714U; -} -static inline u32 nvtlc_rx_err_first_0_r(void) -{ - return 0x00000f14U; -} -static inline u32 nvtlc_rx_err_first_1_r(void) -{ - return 0x00000f2cU; -} +#define nvtlc_tx_err_report_en_0_r() (0x00000708U) +#define nvtlc_rx_err_report_en_0_r() (0x00000f08U) +#define nvtlc_rx_err_report_en_1_r() (0x00000f20U) +#define nvtlc_tx_err_status_0_r() (0x00000700U) +#define nvtlc_rx_err_status_0_r() (0x00000f00U) +#define nvtlc_rx_err_status_1_r() (0x00000f18U) +#define nvtlc_tx_err_first_0_r() (0x00000714U) +#define nvtlc_rx_err_first_0_r() (0x00000f14U) +#define nvtlc_rx_err_first_1_r() (0x00000f2cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index 8c4913d77..4d35edac3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,596 +59,193 @@ #include #include -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x0000000eU; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method3_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_data0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_config_l2_evict_first_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_l2_evict_normal_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_config_ce_split_enable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_ce_split_disable_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_config_auth_level_non_privileged_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_config_userd_writeback_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_userd_writeback_enable_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_eng_reset_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_1_ctxnotvalid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_target_eng_ctx_valid_true_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_target_eng_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_ce_ctx_valid_true_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_target_ce_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) -{ - return 0x3000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_true_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_set_channel_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_set_channel_info_veid_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout_period_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_timeout_period_init_f(void) -{ - return 0x10000U; -} +#define pbdma_gp_entry1_r() (0x10000004U) +#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) +#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) +#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) +#define pbdma_gp_base_r(i)\ + (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base__size_1_v() (0x0000000eU) +#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) +#define pbdma_gp_base_rsvd_s() (3U) +#define pbdma_gp_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) +#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) +#define pbdma_gp_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_get_r(i)\ + (nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_put_r(i)\ + (nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_r(i)\ + (nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_r(i)\ + (nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_r(i)\ + (nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_priv_user_f() (0x0U) +#define pbdma_pb_header_method_zero_f() (0x0U) +#define pbdma_pb_header_subchannel_zero_f() (0x0U) +#define pbdma_pb_header_level_main_f() (0x0U) +#define pbdma_pb_header_first_true_f() (0x400000U) +#define pbdma_pb_header_type_inc_f() (0x20000000U) +#define pbdma_pb_header_type_non_inc_f() (0x60000000U) +#define pbdma_hdr_shadow_r(i)\ + (nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_0_r(i)\ + (nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_1_r(i)\ + (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_r(i)\ + (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) +#define pbdma_subdevice_status_active_f() (0x10000000U) +#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) +#define pbdma_method0_r(i)\ + (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method0_fifo_size_v() (0x00000004U) +#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) +#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) +#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) +#define pbdma_method0_first_true_f() (0x400000U) +#define pbdma_method0_valid_true_f() (0x80000000U) +#define pbdma_method1_r(i)\ + (nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method2_r(i)\ + (nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method3_r(i)\ + (nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_data0_r(i)\ + (nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_r(i)\ + (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_retry_man_2_f() (0x2U) +#define pbdma_acquire_retry_exp_2_f() (0x100U) +#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) +#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) +#define pbdma_acquire_timeout_exp_max_f() (0x7800U) +#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) +#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) +#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) +#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) +#define pbdma_acquire_timeout_en_disable_f() (0x0U) +#define pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_channel_r(i)\ + (nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_r(i)\ + (nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_hw_valid_f() (0xfaceU) +#define pbdma_signature_sw_zero_f() (0x0U) +#define pbdma_userd_r(i)\ + (nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_target_vid_mem_f() (0x0U) +#define pbdma_userd_target_sys_mem_coh_f() (0x2U) +#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) +#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) +#define pbdma_config_r(i)\ + (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_config_l2_evict_first_f() (0x0U) +#define pbdma_config_l2_evict_normal_f() (0x1U) +#define pbdma_config_ce_split_enable_f() (0x0U) +#define pbdma_config_ce_split_disable_f() (0x10U) +#define pbdma_config_auth_level_non_privileged_f() (0x0U) +#define pbdma_config_auth_level_privileged_f() (0x100U) +#define pbdma_config_userd_writeback_disable_f() (0x0U) +#define pbdma_config_userd_writeback_enable_f() (0x1000U) +#define pbdma_userd_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) +#define pbdma_hce_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) +#define pbdma_intr_0_r(i)\ + (nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_intr_0_memreq_pending_f() (0x1U) +#define pbdma_intr_0_memack_timeout_pending_f() (0x2U) +#define pbdma_intr_0_memack_extra_pending_f() (0x4U) +#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U) +#define pbdma_intr_0_memdat_extra_pending_f() (0x10U) +#define pbdma_intr_0_memflush_pending_f() (0x20U) +#define pbdma_intr_0_memop_pending_f() (0x40U) +#define pbdma_intr_0_lbconnect_pending_f() (0x80U) +#define pbdma_intr_0_lbreq_pending_f() (0x100U) +#define pbdma_intr_0_lback_timeout_pending_f() (0x200U) +#define pbdma_intr_0_lback_extra_pending_f() (0x400U) +#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U) +#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U) +#define pbdma_intr_0_gpfifo_pending_f() (0x2000U) +#define pbdma_intr_0_gpptr_pending_f() (0x4000U) +#define pbdma_intr_0_gpentry_pending_f() (0x8000U) +#define pbdma_intr_0_gpcrc_pending_f() (0x10000U) +#define pbdma_intr_0_pbptr_pending_f() (0x20000U) +#define pbdma_intr_0_pbentry_pending_f() (0x40000U) +#define pbdma_intr_0_pbcrc_pending_f() (0x80000U) +#define pbdma_intr_0_clear_faulted_error_pending_f() (0x100000U) +#define pbdma_intr_0_method_pending_f() (0x200000U) +#define pbdma_intr_0_methodcrc_pending_f() (0x400000U) +#define pbdma_intr_0_device_pending_f() (0x800000U) +#define pbdma_intr_0_eng_reset_pending_f() (0x1000000U) +#define pbdma_intr_0_semaphore_pending_f() (0x2000000U) +#define pbdma_intr_0_acquire_pending_f() (0x4000000U) +#define pbdma_intr_0_pri_pending_f() (0x8000000U) +#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U) +#define pbdma_intr_0_pbseg_pending_f() (0x40000000U) +#define pbdma_intr_0_signature_pending_f() (0x80000000U) +#define pbdma_intr_1_r(i)\ + (nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_1_ctxnotvalid_m() (U32(0x1U) << 31U) +#define pbdma_intr_1_ctxnotvalid_pending_f() (0x80000000U) +#define pbdma_intr_en_0_r(i)\ + (nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U) +#define pbdma_intr_en_1_r(i)\ + (nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_r(i)\ + (nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_lbreq_enabled_f() (0x100U) +#define pbdma_intr_stall_1_r(i)\ + (nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U) +#define pbdma_udma_nop_r() (0x00000008U) +#define pbdma_runlist_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_runlist_timeslice_timeout_128_f() (0x80U) +#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U) +#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U) +#define pbdma_target_r(i)\ + (nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_engine_sw_f() (0x1fU) +#define pbdma_target_eng_ctx_valid_true_f() (0x10000U) +#define pbdma_target_eng_ctx_valid_false_f() (0x0U) +#define pbdma_target_ce_ctx_valid_true_f() (0x20000U) +#define pbdma_target_ce_ctx_valid_false_f() (0x0U) +#define pbdma_target_host_tsg_event_reason_pbdma_idle_f() (0x0U) +#define pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f()\ + (0x1000000U) +#define pbdma_target_host_tsg_event_reason_tsg_yield_f() (0x2000000U) +#define pbdma_target_host_tsg_event_reason_host_subchannel_switch_f()\ + (0x3000000U) +#define pbdma_target_should_send_tsg_event_true_f() (0x20000000U) +#define pbdma_target_should_send_tsg_event_false_f() (0x0U) +#define pbdma_target_needs_host_tsg_event_true_f() (0x80000000U) +#define pbdma_target_needs_host_tsg_event_false_f() (0x0U) +#define pbdma_set_channel_info_r(i)\ + (nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_set_channel_info_veid_f(v) (((v)&0x3fU) << 8U) +#define pbdma_timeout_r(i)\ + (nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U) +#define pbdma_timeout_period_max_f() (0xffffffffU) +#define pbdma_timeout_period_init_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h index 1bd6439a0..c0db9ca1d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,208 +59,58 @@ #include #include -static inline u32 perf_pmmgpc_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmsys_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmgpc_base_v(void) -{ - return 0x00180000U; -} -static inline u32 perf_pmmgpc_extent_v(void) -{ - return 0x00183fffU; -} -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x00240000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x00243fffU; -} -static inline u32 perf_pmmfbp_base_v(void) -{ - return 0x00200000U; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x0024a000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x0024a070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x0024a074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x0024a078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x0024a07cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x0024a084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x0024a088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x0024a0a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmmsys_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0024006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmsys_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmfbp_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmfbp_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmgpc_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmgpc_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} +#define perf_pmmgpc_perdomain_offset_v() (0x00000200U) +#define perf_pmmsys_perdomain_offset_v() (0x00000200U) +#define perf_pmmgpc_base_v() (0x00180000U) +#define perf_pmmgpc_extent_v() (0x00183fffU) +#define perf_pmmsys_base_v() (0x00240000U) +#define perf_pmmsys_extent_v() (0x00243fffU) +#define perf_pmmfbp_base_v() (0x00200000U) +#define perf_pmasys_control_r() (0x0024a000U) +#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) +#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) +#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) +#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) +#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) +#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) +#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_mem_block_r() (0x0024a070U) +#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) +#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) +#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) +#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) +#define perf_pmasys_mem_block_target_lfb_f() (0x0U) +#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U) +#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) +#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) +#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) +#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) +#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) +#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) +#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) +#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) +#define perf_pmasys_mem_block_valid_false_f() (0x0U) +#define perf_pmasys_outbase_r() (0x0024a074U) +#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_outbaseupper_r() (0x0024a078U) +#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) +#define perf_pmasys_outsize_r() (0x0024a07cU) +#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_mem_bytes_r() (0x0024a084U) +#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_mem_bump_r() (0x0024a088U) +#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_enginestatus_r() (0x0024a0a4U) +#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) +#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) +#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) +#define perf_pmmsys_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0024006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmsys_engine_sel__size_1_v() (0x00000020U) +#define perf_pmmfbp_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmfbp_engine_sel__size_1_v() (0x00000020U) +#define perf_pmmgpc_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmgpc_engine_sel__size_1_v() (0x00000020U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h index 0645b53e1..fa60172eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,588 +59,156 @@ #include #include -static inline u32 pgsp_falcon_irqsset_r(void) -{ - return 0x00110000U; -} -static inline u32 pgsp_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pgsp_falcon_irqsclr_r(void) -{ - return 0x00110004U; -} -static inline u32 pgsp_falcon_irqstat_r(void) -{ - return 0x00110008U; -} -static inline u32 pgsp_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pgsp_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pgsp_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pgsp_falcon_irqmode_r(void) -{ - return 0x0011000cU; -} -static inline u32 pgsp_falcon_irqmset_r(void) -{ - return 0x00110010U; -} -static inline u32 pgsp_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqmclr_r(void) -{ - return 0x00110014U; -} -static inline u32 pgsp_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_irqmask_r(void) -{ - return 0x00110018U; -} -static inline u32 pgsp_falcon_irqdest_r(void) -{ - return 0x0011001cU; -} -static inline u32 pgsp_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pgsp_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pgsp_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pgsp_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pgsp_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pgsp_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pgsp_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pgsp_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pgsp_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pgsp_falcon_curctx_r(void) -{ - return 0x00110050U; -} -static inline u32 pgsp_falcon_nxtctx_r(void) -{ - return 0x00110054U; -} -static inline u32 pgsp_falcon_nxtctx_ctxptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_fb_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pgsp_falcon_nxtctx_ctxvalid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pgsp_falcon_mailbox0_r(void) -{ - return 0x00110040U; -} -static inline u32 pgsp_falcon_mailbox1_r(void) -{ - return 0x00110044U; -} -static inline u32 pgsp_falcon_itfen_r(void) -{ - return 0x00110048U; -} -static inline u32 pgsp_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_falcon_idlestate_r(void) -{ - return 0x0011004cU; -} -static inline u32 pgsp_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pgsp_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pgsp_falcon_os_r(void) -{ - return 0x00110080U; -} -static inline u32 pgsp_falcon_engctl_r(void) -{ - return 0x001100a4U; -} -static inline u32 pgsp_falcon_engctl_switch_context_true_f(void) -{ - return 0x8U; -} -static inline u32 pgsp_falcon_engctl_switch_context_false_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_falcon_cpuctl_r(void) -{ - return 0x00110100U; -} -static inline u32 pgsp_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pgsp_falcon_cpuctl_alias_r(void) -{ - return 0x00110130U; -} -static inline u32 pgsp_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pgsp_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pgsp_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pgsp_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pgsp_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pgsp_falcon_sctl_r(void) -{ - return 0x00110240U; -} -static inline u32 pgsp_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pgsp_falcon_bootvec_r(void) -{ - return 0x00110104U; -} -static inline u32 pgsp_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pgsp_falcon_dmactl_r(void) -{ - return 0x0011010cU; -} -static inline u32 pgsp_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pgsp_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pgsp_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_hwcfg_r(void) -{ - return 0x00110108U; -} -static inline u32 pgsp_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pgsp_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pgsp_falcon_dmatrfbase_r(void) -{ - return 0x00110110U; -} -static inline u32 pgsp_falcon_dmatrfbase1_r(void) -{ - return 0x00110128U; -} -static inline u32 pgsp_falcon_dmatrfmoffs_r(void) -{ - return 0x00110114U; -} -static inline u32 pgsp_falcon_dmatrfcmd_r(void) -{ - return 0x00110118U; -} -static inline u32 pgsp_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pgsp_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pgsp_falcon_dmatrffboffs_r(void) -{ - return 0x0011011cU; -} -static inline u32 pgsp_falcon_exterraddr_r(void) -{ - return 0x00110168U; -} -static inline u32 pgsp_falcon_exterrstat_r(void) -{ - return 0x0011016cU; -} -static inline u32 pgsp_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pgsp_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pgsp_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_r(void) -{ - return 0x00110200U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pgsp_sec2_falcon_icd_rdata_r(void) -{ - return 0x0011020cU; -} -static inline u32 pgsp_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x001101c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pgsp_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pgsp_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pgsp_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pgsp_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pgsp_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pgsp_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x001101c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pgsp_falcon_debug1_r(void) -{ - return 0x00110090U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110600U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pgsp_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 pgsp_falcon_engine_r(void) -{ - return 0x001103c0U; -} -static inline u32 pgsp_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_r(void) -{ - return 0x00110624U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_init_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_disallow_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_allow_f(void) -{ - return 0x80U; -} +#define pgsp_falcon_irqsset_r() (0x00110000U) +#define pgsp_falcon_irqsset_swgen0_set_f() (0x40U) +#define pgsp_falcon_irqsclr_r() (0x00110004U) +#define pgsp_falcon_irqstat_r() (0x00110008U) +#define pgsp_falcon_irqstat_halt_true_f() (0x10U) +#define pgsp_falcon_irqstat_exterr_true_f() (0x20U) +#define pgsp_falcon_irqstat_swgen0_true_f() (0x40U) +#define pgsp_falcon_irqmode_r() (0x0011000cU) +#define pgsp_falcon_irqmset_r() (0x00110010U) +#define pgsp_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pgsp_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pgsp_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pgsp_falcon_irqmclr_r() (0x00110014U) +#define pgsp_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pgsp_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pgsp_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pgsp_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_irqmask_r() (0x00110018U) +#define pgsp_falcon_irqdest_r() (0x0011001cU) +#define pgsp_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pgsp_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pgsp_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pgsp_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pgsp_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pgsp_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pgsp_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pgsp_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pgsp_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pgsp_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pgsp_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pgsp_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pgsp_falcon_curctx_r() (0x00110050U) +#define pgsp_falcon_nxtctx_r() (0x00110054U) +#define pgsp_falcon_nxtctx_ctxptr_f(v) (((v)&0xfffffffU) << 0U) +#define pgsp_falcon_nxtctx_ctxtgt_fb_f() (0x0U) +#define pgsp_falcon_nxtctx_ctxtgt_sys_coh_f() (0x20000000U) +#define pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f() (0x30000000U) +#define pgsp_falcon_nxtctx_ctxvalid_f(v) (((v)&0x1U) << 30U) +#define pgsp_falcon_mailbox0_r() (0x00110040U) +#define pgsp_falcon_mailbox1_r() (0x00110044U) +#define pgsp_falcon_itfen_r() (0x00110048U) +#define pgsp_falcon_itfen_ctxen_enable_f() (0x1U) +#define pgsp_falcon_idlestate_r() (0x0011004cU) +#define pgsp_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pgsp_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pgsp_falcon_os_r() (0x00110080U) +#define pgsp_falcon_engctl_r() (0x001100a4U) +#define pgsp_falcon_engctl_switch_context_true_f() (0x8U) +#define pgsp_falcon_engctl_switch_context_false_f() (0x0U) +#define pgsp_falcon_cpuctl_r() (0x00110100U) +#define pgsp_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pgsp_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pgsp_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pgsp_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pgsp_falcon_cpuctl_alias_r() (0x00110130U) +#define pgsp_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00110180U, nvgpu_safe_mult_u32((i), 16U))) +#define pgsp_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pgsp_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pgsp_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00110184U, nvgpu_safe_mult_u32((i), 16U))) +#define pgsp_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00110188U, nvgpu_safe_mult_u32((i), 16U))) +#define pgsp_falcon_sctl_r() (0x00110240U) +#define pgsp_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pgsp_falcon_bootvec_r() (0x00110104U) +#define pgsp_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pgsp_falcon_dmactl_r() (0x0011010cU) +#define pgsp_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pgsp_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pgsp_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_hwcfg_r() (0x00110108U) +#define pgsp_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pgsp_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pgsp_falcon_dmatrfbase_r() (0x00110110U) +#define pgsp_falcon_dmatrfbase1_r() (0x00110128U) +#define pgsp_falcon_dmatrfmoffs_r() (0x00110114U) +#define pgsp_falcon_dmatrfcmd_r() (0x00110118U) +#define pgsp_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pgsp_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pgsp_falcon_dmatrffboffs_r() (0x0011011cU) +#define pgsp_falcon_exterraddr_r() (0x00110168U) +#define pgsp_falcon_exterrstat_r() (0x0011016cU) +#define pgsp_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pgsp_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pgsp_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pgsp_sec2_falcon_icd_cmd_r() (0x00110200U) +#define pgsp_sec2_falcon_icd_cmd_opc_s() (4U) +#define pgsp_sec2_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pgsp_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pgsp_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pgsp_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pgsp_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pgsp_sec2_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pgsp_sec2_falcon_icd_rdata_r() (0x0011020cU) +#define pgsp_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x001101c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pgsp_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pgsp_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pgsp_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pgsp_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pgsp_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pgsp_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x001101c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pgsp_falcon_debug1_r() (0x00110090U) +#define pgsp_falcon_debug1_ctxsw_mode_s() (1U) +#define pgsp_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define pgsp_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define pgsp_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define pgsp_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define pgsp_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x00110600U, nvgpu_safe_mult_u32((i), 4U))) +#define pgsp_fbif_transcfg_target_local_fb_f() (0x0U) +#define pgsp_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pgsp_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pgsp_fbif_transcfg_mem_type_s() (1U) +#define pgsp_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pgsp_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pgsp_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pgsp_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pgsp_fbif_transcfg_mem_type_physical_f() (0x4U) +#define pgsp_falcon_engine_r() (0x001103c0U) +#define pgsp_falcon_engine_reset_true_f() (0x1U) +#define pgsp_falcon_engine_reset_false_f() (0x0U) +#define pgsp_fbif_ctl_r() (0x00110624U) +#define pgsp_fbif_ctl_allow_phys_no_ctx_init_f() (0x0U) +#define pgsp_fbif_ctl_allow_phys_no_ctx_disallow_f() (0x0U) +#define pgsp_fbif_ctl_allow_phys_no_ctx_allow_f() (0x80U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h index 679932714..5bd32eb90 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pram_data032_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U)); -} +#define pram_data032_r(i)\ + (nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h index 8c325377e..61dfd4f77 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,112 +59,33 @@ #include #include -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} +#define pri_ringmaster_command_r() (0x0012004cU) +#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U) +#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU) +#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U) +#define pri_ringmaster_command_cmd_start_ring_f() (0x1U) +#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U) +#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U) +#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U) +#define pri_ringmaster_command_data_r() (0x00120048U) +#define pri_ringmaster_start_results_r() (0x00120050U) +#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U) +#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U) +#define pri_ringmaster_intr_status0_r() (0x00120058U) +#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\ + (((r) >> 0U) & 0x1U) +#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U) +#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U) +#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\ + (((r) >> 8U) & 0x1U) +#define pri_ringmaster_intr_status1_r() (0x0012005cU) +#define pri_ringmaster_global_ctl_r() (0x00120060U) +#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U) +#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U) +#define pri_ringmaster_enum_fbp_r() (0x00120074U) +#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_gpc_r() (0x00120078U) +#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_ltc_r() (0x0012006cU) +#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h index a237ff66d..fa15589a0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,24 +59,10 @@ #include #include -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} +#define pri_ringstation_gpc_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U) +#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) +#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) +#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h index 4f24cd5d5..3b8f2f818 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,36 +59,14 @@ #include #include -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} +#define pri_ringstation_sys_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_sys_decode_config_r() (0x00122204U) +#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U) +#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\ + (0x1U) +#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U) +#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) +#define pri_ringstation_sys_priv_error_info_r() (0x00122128U) +#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index c7ebf2cca..0b8489ba5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,144 +59,39 @@ #include #include -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_smpc_base_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_smpc_shared_base_v(void) -{ - return 0x00000300U; -} -static inline u32 proj_smpc_unique_base_v(void) -{ - return 0x00000600U; -} -static inline u32 proj_smpc_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x0000000fU; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x0000000eU; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000007U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000010U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_sm_stride_v(void) -{ - return 0x00000080U; -} +#define proj_gpc_base_v() (0x00500000U) +#define proj_gpc_shared_base_v() (0x00418000U) +#define proj_gpc_stride_v() (0x00008000U) +#define proj_gpc_priv_stride_v() (0x00000800U) +#define proj_ltc_stride_v() (0x00002000U) +#define proj_lts_stride_v() (0x00000200U) +#define proj_fbpa_base_v() (0x00900000U) +#define proj_fbpa_shared_base_v() (0x009a0000U) +#define proj_fbpa_stride_v() (0x00004000U) +#define proj_ppc_in_gpc_base_v() (0x00003000U) +#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U) +#define proj_ppc_in_gpc_stride_v() (0x00000200U) +#define proj_rop_base_v() (0x00410000U) +#define proj_rop_shared_base_v() (0x00408800U) +#define proj_rop_stride_v() (0x00000400U) +#define proj_tpc_in_gpc_base_v() (0x00004000U) +#define proj_tpc_in_gpc_stride_v() (0x00000800U) +#define proj_tpc_in_gpc_shared_base_v() (0x00001800U) +#define proj_smpc_base_v() (0x00000200U) +#define proj_smpc_shared_base_v() (0x00000300U) +#define proj_smpc_unique_base_v() (0x00000600U) +#define proj_smpc_stride_v() (0x00000100U) +#define proj_host_num_engines_v() (0x0000000fU) +#define proj_host_num_pbdma_v() (0x0000000eU) +#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000007U) +#define proj_scal_litter_num_fbps_v() (0x00000008U) +#define proj_scal_litter_num_fbpas_v() (0x00000010U) +#define proj_scal_litter_num_gpcs_v() (0x00000006U) +#define proj_scal_litter_num_pes_per_gpc_v() (0x00000003U) +#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000003U) +#define proj_scal_litter_num_zcull_banks_v() (0x00000004U) +#define proj_scal_litter_num_sm_per_tpc_v() (0x00000002U) +#define proj_scal_max_gpcs_v() (0x00000020U) +#define proj_scal_max_tpc_per_gpc_v() (0x00000008U) +#define proj_sm_stride_v() (0x00000080U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h index ff2e8e50b..8b27e742c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,956 +59,264 @@ #include #include -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) -{ - return 0x800U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmset_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_host_error_r(void) -{ - return 0x0010a990U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} +#define pwr_falcon_irqsset_r() (0x0010a000U) +#define pwr_falcon_irqsset_swgen0_set_f() (0x40U) +#define pwr_falcon_irqsclr_r() (0x0010a004U) +#define pwr_falcon_irqstat_r() (0x0010a008U) +#define pwr_falcon_irqstat_halt_true_f() (0x10U) +#define pwr_falcon_irqstat_exterr_true_f() (0x20U) +#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) +#define pwr_falcon_irqstat_ext_second_true_f() (0x800U) +#define pwr_falcon_irqmode_r() (0x0010a00cU) +#define pwr_falcon_irqmset_r() (0x0010a010U) +#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmset_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmset_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqmset_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqmset_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqmset_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqmset_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqmset_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqmclr_r() (0x0010a014U) +#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmclr_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqmclr_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqmclr_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqmclr_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqmclr_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqmclr_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqmask_r() (0x0010a018U) +#define pwr_falcon_irqdest_r() (0x0010a01cU) +#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqdest_host_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqdest_host_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqdest_host_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqdest_host_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqdest_host_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqdest_host_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pwr_falcon_irqdest_target_ext_ctxe_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_irqdest_target_ext_limitv_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_irqdest_target_ext_second_f(v) (((v)&0x1U) << 27U) +#define pwr_falcon_irqdest_target_ext_therm_f(v) (((v)&0x1U) << 28U) +#define pwr_falcon_irqdest_target_ext_miscio_f(v) (((v)&0x1U) << 29U) +#define pwr_falcon_irqdest_target_ext_rttimer_f(v) (((v)&0x1U) << 30U) +#define pwr_falcon_curctx_r() (0x0010a050U) +#define pwr_falcon_nxtctx_r() (0x0010a054U) +#define pwr_falcon_mailbox0_r() (0x0010a040U) +#define pwr_falcon_mailbox1_r() (0x0010a044U) +#define pwr_falcon_itfen_r() (0x0010a048U) +#define pwr_falcon_itfen_ctxen_enable_f() (0x1U) +#define pwr_falcon_idlestate_r() (0x0010a04cU) +#define pwr_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pwr_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pwr_falcon_os_r() (0x0010a080U) +#define pwr_falcon_engctl_r() (0x0010a0a4U) +#define pwr_falcon_cpuctl_r() (0x0010a100U) +#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) +#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) +#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) +#define pwr_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_sctl_r() (0x0010a240U) +#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pwr_falcon_bootvec_r() (0x0010a104U) +#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_falcon_dmactl_r() (0x0010a10cU) +#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pwr_falcon_hwcfg_r() (0x0010a108U) +#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pwr_falcon_dmatrfbase_r() (0x0010a110U) +#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) +#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) +#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) +#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) +#define pwr_falcon_exterraddr_r() (0x0010a168U) +#define pwr_falcon_exterrstat_r() (0x0010a16cU) +#define pwr_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pwr_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) +#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) +#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) +#define pwr_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_new_instblk_r() (0x0010a480U) +#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define pwr_pmu_new_instblk_target_fb_f() (0x0U) +#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) +#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) +#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) +#define pwr_pmu_mutex_id_r() (0x0010a488U) +#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) +#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) +#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) +#define pwr_pmu_mutex_r(i)\ + (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mutex__size_1_v() (0x00000010U) +#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) +#define pwr_pmu_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_head__size_1_v() (0x00000008U) +#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_tail__size_1_v() (0x00000008U) +#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_head_r() (0x0010a4c8U) +#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) +#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_idle_mask_r(i)\ + (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U) +#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) +#define pwr_pmu_idle_count_r(i)\ + (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) +#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_idle_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) +#define pwr_pmu_idle_ctrl_value_busy_f() (0x2U) +#define pwr_pmu_idle_ctrl_value_always_f() (0x3U) +#define pwr_pmu_idle_ctrl_filter_m() (U32(0x1U) << 2U) +#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) +#define pwr_pmu_idle_threshold_r(i)\ + (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_intr_r() (0x0010a9e8U) +#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) +#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) +#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) +#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_intr_clear_v() (0x00000001U) +#define pwr_pmu_idle_mask_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_mask_1_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_ctrl_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_debug_r(i)\ + (nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_debug__size_1_v() (0x00000004U) +#define pwr_pmu_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mailbox__size_1_v() (0x0000000cU) +#define pwr_pmu_bar0_addr_r() (0x0010a7a0U) +#define pwr_pmu_bar0_data_r() (0x0010a7a4U) +#define pwr_pmu_bar0_ctl_r() (0x0010a7acU) +#define pwr_pmu_bar0_timeout_r() (0x0010a7a8U) +#define pwr_pmu_bar0_fecs_error_r() (0x0010a988U) +#define pwr_pmu_bar0_host_error_r() (0x0010a990U) +#define pwr_pmu_bar0_error_status_r() (0x0010a7b0U) +#define pwr_pmu_bar0_error_status_timeout_host_m() (U32(0x1U) << 0U) +#define pwr_pmu_bar0_error_status_timeout_fecs_m() (U32(0x1U) << 1U) +#define pwr_pmu_bar0_error_status_cmd_hwerr_m() (U32(0x1U) << 2U) +#define pwr_pmu_bar0_error_status_err_cmd_m() (U32(0x1U) << 3U) +#define pwr_pmu_bar0_error_status_hosterr_m() (U32(0x1U) << 30U) +#define pwr_pmu_bar0_error_status_fecserr_m() (U32(0x1U) << 31U) +#define pwr_pmu_pg_idlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_ppuidlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_idle_cnt_r(i)\ + (nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_intren_r(i)\ + (nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_target_local_fb_f() (0x0U) +#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pwr_fbif_transcfg_mem_type_s() (1U) +#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pwr_fbif_transcfg_mem_type_physical_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index 786852847..9839cc2df 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,760 +59,205 @@ #include #include -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_engine_wfi_mode_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_engine_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_wfi_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_engine_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_engine_wfi_target_local_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_engine_wfi_veid_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ram_in_engine_wfi_veid_w(void) -{ - return 134U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) -{ - return 136U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) -{ - return 137U; -} -static inline u32 ram_in_sc_pdb_valid_w(u32 i) -{ - return 166U + ((i*1U)/32U); -} -static inline u32 ram_in_sc_pdb_valid__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) -{ - return (v & 0x3U) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) -{ - return (v & 0x1U) << (2U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_vol_w(u32 i) -{ - return 168U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) -{ - return (v & 0x1U) << (4U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) -{ - return (v & 0x1U) << (5U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) -{ - return (v & 0x1U) << (10U + i*0U); -} -static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) -{ - return (v & 0x1U) << (11U + i*0U); -} -static inline u32 ram_in_sc_big_page_size__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_big_page_size_64kb_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) -{ - return (v & 0xfffffU) << (12U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_lo_w(u32 i) -{ - return 168U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) -{ - return (v & 0xffffffffU) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_hi_w(u32 i) -{ - return 169U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_big_page_size_0_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_sc_big_page_size_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) -{ - return 169U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_sem_addr_hi_w(void) -{ - return 14U; -} -static inline u32 ram_fc_sem_addr_lo_w(void) -{ - return 15U; -} -static inline u32 ram_fc_sem_payload_lo_w(void) -{ - return 16U; -} -static inline u32 ram_fc_sem_payload_hi_w(void) -{ - return 39U; -} -static inline u32 ram_fc_sem_execute_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_fc_set_channel_info_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000010U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ram_rl_entry_type_channel_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_type_tsg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) -{ - return (v & 0x3U) << 6U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_length_init_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_tsg_length_min_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_tsg_length_max_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} +#define ram_in_ramfc_s() (4096U) +#define ram_in_ramfc_w() (0U) +#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_page_dir_base_target_w() (128U) +#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) +#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) +#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) +#define ram_in_page_dir_base_vol_w() (128U) +#define ram_in_page_dir_base_vol_true_f() (0x4U) +#define ram_in_page_dir_base_vol_false_f() (0x0U) +#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_w() (128U) +#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) +#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) +#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) +#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) +#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) +#define ram_in_use_ver2_pt_format_w() (128U) +#define ram_in_use_ver2_pt_format_true_f() (0x400U) +#define ram_in_use_ver2_pt_format_false_f() (0x0U) +#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) +#define ram_in_big_page_size_m() (U32(0x1U) << 11U) +#define ram_in_big_page_size_w() (128U) +#define ram_in_big_page_size_128kb_f() (0x0U) +#define ram_in_big_page_size_64kb_f() (0x800U) +#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_page_dir_base_lo_w() (128U) +#define ram_in_page_dir_base_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_page_dir_base_hi_w() (129U) +#define ram_in_engine_cs_w() (132U) +#define ram_in_engine_cs_wfi_v() (0x00000000U) +#define ram_in_engine_cs_wfi_f() (0x0U) +#define ram_in_engine_cs_fg_v() (0x00000001U) +#define ram_in_engine_cs_fg_f() (0x8U) +#define ram_in_engine_wfi_mode_f(v) (((v)&0x1U) << 2U) +#define ram_in_engine_wfi_mode_w() (132U) +#define ram_in_engine_wfi_mode_physical_v() (0x00000000U) +#define ram_in_engine_wfi_mode_virtual_v() (0x00000001U) +#define ram_in_engine_wfi_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_engine_wfi_target_w() (132U) +#define ram_in_engine_wfi_target_sys_mem_coh_v() (0x00000002U) +#define ram_in_engine_wfi_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_in_engine_wfi_target_local_mem_v() (0x00000000U) +#define ram_in_engine_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_engine_wfi_ptr_lo_w() (132U) +#define ram_in_engine_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_engine_wfi_ptr_hi_w() (133U) +#define ram_in_engine_wfi_veid_f(v) (((v)&0x3fU) << 0U) +#define ram_in_engine_wfi_veid_w() (134U) +#define ram_in_eng_method_buffer_addr_lo_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_eng_method_buffer_addr_lo_w() (136U) +#define ram_in_eng_method_buffer_addr_hi_f(v) (((v)&0x1ffffU) << 0U) +#define ram_in_eng_method_buffer_addr_hi_w() (137U) +#define ram_in_sc_pdb_valid_w(i)\ + (166U + ((i*1U)/32U)) +#define ram_in_sc_pdb_valid__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_f(v, i)\ + (((v) & 0x3) << (0U + i*0U)) +#define ram_in_sc_page_dir_base_target__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_vid_mem_v() (0x00000000U) +#define ram_in_sc_page_dir_base_target_invalid_v() (0x00000001U) +#define ram_in_sc_page_dir_base_target_sys_mem_coh_v() (0x00000002U) +#define ram_in_sc_page_dir_base_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_in_sc_page_dir_base_vol_f(v, i)\ + (((v) & 0x1) << (2U + i*0U)) +#define ram_in_sc_page_dir_base_vol_w(i)\ + (168U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_vol__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_vol_true_v() (0x00000001U) +#define ram_in_sc_page_dir_base_vol_false_v() (0x00000000U) +#define ram_in_sc_page_dir_base_fault_replay_tex_f(v, i)\ + (((v) & 0x1) << (4U + i*0U)) +#define ram_in_sc_page_dir_base_fault_replay_tex__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_fault_replay_tex_enabled_v() (0x00000001U) +#define ram_in_sc_page_dir_base_fault_replay_tex_disabled_v() (0x00000000U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_f(v, i)\ + (((v) & 0x1) << (5U + i*0U)) +#define ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v() (0x00000001U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v() (0x00000000U) +#define ram_in_sc_use_ver2_pt_format_f(v, i)\ + (((v) & 0x1) << (10U + i*0U)) +#define ram_in_sc_use_ver2_pt_format__size_1_v() (0x00000040U) +#define ram_in_sc_use_ver2_pt_format_false_v() (0x00000000U) +#define ram_in_sc_use_ver2_pt_format_true_v() (0x00000001U) +#define ram_in_sc_big_page_size_f(v, i)\ + (((v) & 0x1) << (11U + i*0U)) +#define ram_in_sc_big_page_size__size_1_v() (0x00000040U) +#define ram_in_sc_big_page_size_64kb_v() (0x00000001U) +#define ram_in_sc_page_dir_base_lo_f(v, i)\ + (((v) & 0xfffff) << (12U + i*0U)) +#define ram_in_sc_page_dir_base_lo_w(i)\ + (168U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_lo__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_hi_f(v, i)\ + (((v) & 0xffffffff) << (0U + i*0U)) +#define ram_in_sc_page_dir_base_hi_w(i)\ + (169U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_hi__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_0_f(v) (((v)&0x3U) << 0U) +#define ram_in_sc_page_dir_base_target_0_w() (168U) +#define ram_in_sc_page_dir_base_vol_0_f(v) (((v)&0x1U) << 2U) +#define ram_in_sc_page_dir_base_vol_0_w() (168U) +#define ram_in_sc_page_dir_base_fault_replay_tex_0_f(v) (((v)&0x1U) << 4U) +#define ram_in_sc_page_dir_base_fault_replay_tex_0_w() (168U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_0_f(v) (((v)&0x1U) << 5U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_0_w() (168U) +#define ram_in_sc_use_ver2_pt_format_0_f(v) (((v)&0x1U) << 10U) +#define ram_in_sc_use_ver2_pt_format_0_w() (168U) +#define ram_in_sc_big_page_size_0_f(v) (((v)&0x1U) << 11U) +#define ram_in_sc_big_page_size_0_w() (168U) +#define ram_in_sc_page_dir_base_lo_0_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_sc_page_dir_base_lo_0_w() (168U) +#define ram_in_sc_page_dir_base_hi_0_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_sc_page_dir_base_hi_0_w() (169U) +#define ram_in_base_shift_v() (0x0000000cU) +#define ram_in_alloc_size_v() (0x00001000U) +#define ram_fc_size_val_v() (0x00000200U) +#define ram_fc_gp_put_w() (0U) +#define ram_fc_userd_w() (2U) +#define ram_fc_userd_hi_w() (3U) +#define ram_fc_signature_w() (4U) +#define ram_fc_gp_get_w() (5U) +#define ram_fc_pb_get_w() (6U) +#define ram_fc_pb_get_hi_w() (7U) +#define ram_fc_pb_top_level_get_w() (8U) +#define ram_fc_pb_top_level_get_hi_w() (9U) +#define ram_fc_acquire_w() (12U) +#define ram_fc_sem_addr_hi_w() (14U) +#define ram_fc_sem_addr_lo_w() (15U) +#define ram_fc_sem_payload_lo_w() (16U) +#define ram_fc_sem_payload_hi_w() (39U) +#define ram_fc_sem_execute_w() (17U) +#define ram_fc_gp_base_w() (18U) +#define ram_fc_gp_base_hi_w() (19U) +#define ram_fc_gp_fetch_w() (20U) +#define ram_fc_pb_fetch_w() (21U) +#define ram_fc_pb_fetch_hi_w() (22U) +#define ram_fc_pb_put_w() (23U) +#define ram_fc_pb_put_hi_w() (24U) +#define ram_fc_pb_header_w() (33U) +#define ram_fc_pb_count_w() (34U) +#define ram_fc_subdevice_w() (37U) +#define ram_fc_target_w() (43U) +#define ram_fc_hce_ctrl_w() (57U) +#define ram_fc_chid_w() (58U) +#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) +#define ram_fc_chid_id_w() (0U) +#define ram_fc_config_w() (61U) +#define ram_fc_runlist_timeslice_w() (62U) +#define ram_fc_set_channel_info_w() (63U) +#define ram_userd_base_shift_v() (0x00000009U) +#define ram_userd_chan_size_v() (0x00000200U) +#define ram_userd_put_w() (16U) +#define ram_userd_get_w() (17U) +#define ram_userd_ref_w() (18U) +#define ram_userd_put_hi_w() (19U) +#define ram_userd_top_level_get_w() (22U) +#define ram_userd_top_level_get_hi_w() (23U) +#define ram_userd_get_hi_w() (24U) +#define ram_userd_gp_get_w() (34U) +#define ram_userd_gp_put_w() (35U) +#define ram_userd_gp_top_level_get_w() (22U) +#define ram_userd_gp_top_level_get_hi_w() (23U) +#define ram_rl_entry_size_v() (0x00000010U) +#define ram_rl_entry_type_f(v) (((v)&0x1U) << 0U) +#define ram_rl_entry_type_channel_v() (0x00000000U) +#define ram_rl_entry_type_tsg_v() (0x00000001U) +#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_runqueue_selector_f(v) (((v)&0x1U) << 1U) +#define ram_rl_entry_chan_inst_target_f(v) (((v)&0x3U) << 4U) +#define ram_rl_entry_chan_inst_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_rl_entry_chan_inst_target_sys_mem_coh_v() (0x00000002U) +#define ram_rl_entry_chan_inst_target_vid_mem_v() (0x00000000U) +#define ram_rl_entry_chan_userd_target_f(v) (((v)&0x3U) << 6U) +#define ram_rl_entry_chan_userd_target_vid_mem_v() (0x00000000U) +#define ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v() (0x00000001U) +#define ram_rl_entry_chan_userd_target_sys_mem_coh_v() (0x00000002U) +#define ram_rl_entry_chan_userd_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_rl_entry_chan_userd_ptr_lo_f(v) (((v)&0xffffffU) << 8U) +#define ram_rl_entry_chan_userd_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_inst_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_rl_entry_chan_inst_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_rl_entry_tsg_timeslice_scale_f(v) (((v)&0xfU) << 16U) +#define ram_rl_entry_tsg_timeslice_scale_v(r) (((r) >> 16U) & 0xfU) +#define ram_rl_entry_tsg_timeslice_scale_3_v() (0x00000003U) +#define ram_rl_entry_tsg_timeslice_timeout_f(v) (((v)&0xffU) << 24U) +#define ram_rl_entry_tsg_timeslice_timeout_v(r) (((r) >> 24U) & 0xffU) +#define ram_rl_entry_tsg_timeslice_timeout_128_v() (0x00000080U) +#define ram_rl_entry_tsg_length_f(v) (((v)&0xffU) << 0U) +#define ram_rl_entry_tsg_length_init_v() (0x00000000U) +#define ram_rl_entry_tsg_length_min_v() (0x00000001U) +#define ram_rl_entry_tsg_length_max_v() (0x00000080U) +#define ram_rl_entry_tsg_tsgid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_userd_ptr_align_shift_v() (0x00000008U) +#define ram_rl_entry_chan_userd_align_shift_v() (0x00000008U) +#define ram_rl_entry_chan_inst_ptr_align_shift_v() (0x0000000cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h index 1721508a3..61d4d72cf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,244 +59,68 @@ #include #include -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return U32(0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return U32(0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return U32(0xfU) << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return U32(0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return U32(0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return U32(0x3fU) << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} +#define therm_weight_1_r() (0x00020024U) +#define therm_config1_r() (0x00020050U) +#define therm_config2_r() (0x00020130U) +#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) +#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) +#define therm_gate_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) +#define therm_gate_ctrl_eng_clk_run_f() (0x0U) +#define therm_gate_ctrl_eng_clk_auto_f() (0x1U) +#define therm_gate_ctrl_eng_clk_stop_f() (0x2U) +#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) +#define therm_gate_ctrl_blk_clk_run_f() (0x0U) +#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) +#define therm_gate_ctrl_idle_holdoff_m() (U32(0x1U) << 4U) +#define therm_gate_ctrl_idle_holdoff_off_f() (0x0U) +#define therm_gate_ctrl_idle_holdoff_on_f() (0x10U) +#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) +#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) +#define therm_fecs_idle_filter_r() (0x00020288U) +#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_hubmmu_idle_filter_r() (0x0002028cU) +#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_clk_slowdown_r(i)\ + (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) +#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) +#define therm_grad_stepping_table_r(i)\ + (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) +#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) +#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) +#define therm_grad_stepping0_r() (0x000202c0U) +#define therm_grad_stepping0_feature_s() (1U) +#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) +#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) +#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) +#define therm_grad_stepping0_feature_enable_f() (0x1U) +#define therm_grad_stepping1_r() (0x000202c4U) +#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) +#define therm_clk_timing_r(i)\ + (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h index 78ecf0db6..83d022063 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,60 +59,18 @@ #include #include -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} +#define timer_pri_timeout_r() (0x00009080U) +#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) +#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) +#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) +#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) +#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) +#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) +#define timer_pri_timeout_en_en_disabled_f() (0x0U) +#define timer_pri_timeout_save_0_r() (0x00009084U) +#define timer_pri_timeout_save_1_r() (0x00009088U) +#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU) +#define timer_time_0_r() (0x00009400U) +#define timer_time_1_r() (0x00009410U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h index 130355aff..46255bb86 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,308 +59,81 @@ #include #include -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbpas_r(void) -{ - return 0x0002243cU; -} -static inline u32 top_num_fbpas_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_num_ces_r(void) -{ - return 0x00022444U; -} -static inline u32 top_num_ces_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_chain_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_type_enum_ioctrl_v(void) -{ - return 0x00000012U; -} -static inline u32 top_device_info_type_enum_ioctrl_f(void) -{ - return 0x48U; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_engine_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_runlist_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_intr_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_reset_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x7fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_nvhsclk_ctrl_r(void) -{ - return 0x00022424U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_nvl_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_nvl_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_nvl_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_pcie_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_pcie_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_pcie_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_core_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_core_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 top_nvhsclk_ctrl_e_clk_core_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_nvhsclk_ctrl_rfu_f(u32 v) -{ - return (v & 0xfU) << 5U; -} -static inline u32 top_nvhsclk_ctrl_rfu_m(void) -{ - return U32(0xfU) << 5U; -} -static inline u32 top_nvhsclk_ctrl_rfu_v(u32 r) -{ - return (r >> 5U) & 0xfU; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_f(u32 v) -{ - return (v & 0x7U) << 10U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_m(void) -{ - return U32(0x7U) << 10U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_v(u32 r) -{ - return (r >> 10U) & 0x7U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_v(u32 r) -{ - return (r >> 9U) & 0x1U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_core_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_core_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 top_nvhsclk_ctrl_swap_clk_core_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} +#define top_num_gpcs_r() (0x00022430U) +#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_tpc_per_gpc_r() (0x00022434U) +#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbps_r() (0x00022438U) +#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbpas_r() (0x0002243cU) +#define top_num_fbpas_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_ltc_per_fbp_r() (0x00022450U) +#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_slices_per_ltc_r() (0x0002245cU) +#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_ltcs_r() (0x00022454U) +#define top_num_ces_r() (0x00022444U) +#define top_num_ces_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_device_info_r(i)\ + (nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U))) +#define top_device_info__size_1_v() (0x00000040U) +#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U) +#define top_device_info_chain_enable_v() (0x00000001U) +#define top_device_info_chain_disable_v() (0x00000000U) +#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU) +#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU) +#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU) +#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU) +#define top_device_info_type_enum_graphics_v() (0x00000000U) +#define top_device_info_type_enum_graphics_f() (0x0U) +#define top_device_info_type_enum_copy2_v() (0x00000003U) +#define top_device_info_type_enum_copy2_f() (0xcU) +#define top_device_info_type_enum_lce_v() (0x00000013U) +#define top_device_info_type_enum_lce_f() (0x4cU) +#define top_device_info_type_enum_ioctrl_v() (0x00000012U) +#define top_device_info_type_enum_ioctrl_f() (0x48U) +#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U) +#define top_device_info_engine_valid_v() (0x00000001U) +#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U) +#define top_device_info_runlist_valid_v() (0x00000001U) +#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U) +#define top_device_info_intr_valid_v() (0x00000001U) +#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_reset_valid_v() (0x00000001U) +#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) +#define top_device_info_entry_not_valid_v() (0x00000000U) +#define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_data_v() (0x00000001U) +#define top_device_info_entry_engine_type_v() (0x00000003U) +#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U) +#define top_device_info_data_type_enum2_v() (0x00000000U) +#define top_device_info_data_inst_id_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0xfffU) +#define top_device_info_data_pri_base_align_v() (0x0000000cU) +#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x7fU) +#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_data_fault_id_valid_v() (0x00000001U) +#define top_nvhsclk_ctrl_r() (0x00022424U) +#define top_nvhsclk_ctrl_e_clk_nvl_f(v) (((v)&0x7U) << 0U) +#define top_nvhsclk_ctrl_e_clk_nvl_m() (U32(0x7U) << 0U) +#define top_nvhsclk_ctrl_e_clk_nvl_v(r) (((r) >> 0U) & 0x7U) +#define top_nvhsclk_ctrl_e_clk_pcie_f(v) (((v)&0x1U) << 3U) +#define top_nvhsclk_ctrl_e_clk_pcie_m() (U32(0x1U) << 3U) +#define top_nvhsclk_ctrl_e_clk_pcie_v(r) (((r) >> 3U) & 0x1U) +#define top_nvhsclk_ctrl_e_clk_core_f(v) (((v)&0x1U) << 4U) +#define top_nvhsclk_ctrl_e_clk_core_m() (U32(0x1U) << 4U) +#define top_nvhsclk_ctrl_e_clk_core_v(r) (((r) >> 4U) & 0x1U) +#define top_nvhsclk_ctrl_rfu_f(v) (((v)&0xfU) << 5U) +#define top_nvhsclk_ctrl_rfu_m() (U32(0xfU) << 5U) +#define top_nvhsclk_ctrl_rfu_v(r) (((r) >> 5U) & 0xfU) +#define top_nvhsclk_ctrl_swap_clk_nvl_f(v) (((v)&0x7U) << 10U) +#define top_nvhsclk_ctrl_swap_clk_nvl_m() (U32(0x7U) << 10U) +#define top_nvhsclk_ctrl_swap_clk_nvl_v(r) (((r) >> 10U) & 0x7U) +#define top_nvhsclk_ctrl_swap_clk_pcie_f(v) (((v)&0x1U) << 9U) +#define top_nvhsclk_ctrl_swap_clk_pcie_m() (U32(0x1U) << 9U) +#define top_nvhsclk_ctrl_swap_clk_pcie_v(r) (((r) >> 9U) & 0x1U) +#define top_nvhsclk_ctrl_swap_clk_core_f(v) (((v)&0x1U) << 13U) +#define top_nvhsclk_ctrl_swap_clk_core_m() (U32(0x1U) << 13U) +#define top_nvhsclk_ctrl_swap_clk_core_v(r) (((r) >> 13U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h index 1e7d4ab3a..6b73d873d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,192 +59,54 @@ #include #include -static inline u32 trim_sys_nvlink_uphy_cfg_r(void) -{ - return 0x00132410U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void) -{ - return U32(0x3ffU) << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 trim_sys_nvlink0_ctrl_r(void) -{ - return 0x00132420U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_nvlink0_status_r(void) -{ - return 0x00132424U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_r(void) -{ - return 0x001371c4U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v) -{ - return (v & 0x3U) << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void) -{ - return U32(0x3U) << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f(void) -{ - return 0x30000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v(void) -{ - return 0x00000002U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f(void) -{ - return 0x2U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void) -{ - return 0x3U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(void) -{ - return 0x00132a70U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(void) -{ - return 0x10000000U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(void) -{ - return 0x00132a74U; -} -static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r(void) -{ - return 0x00132a78U; -} -static inline u32 trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r(void) -{ - return 0x00136470U; -} -static inline u32 trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(void) -{ - return 0x10000000U; -} -static inline u32 trim_sys_fll_fr_clk_cntr_xbarclk_cntr0_r(void) -{ - return 0x00136474U; -} -static inline u32 trim_sys_fll_fr_clk_cntr_xbarclk_cntr1_r(void) -{ - return 0x00136478U; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_r(void) -{ - return 0x0013762cU; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(void) -{ - return 0x20000000U; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr0_r(void) -{ - return 0x00137630U; -} -static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr1_r(void) -{ - return 0x00137634U; -} +#define trim_sys_nvlink_uphy_cfg_r() (0x00132410U) +#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(v)\ + (((v)&0x3ffU) << 0U) +#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m()\ + (U32(0x3ffU) << 0U) +#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(r)\ + (((r) >> 0U) & 0x3ffU) +#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(v) (((v)&0x1U) << 12U) +#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m() (U32(0x1U) << 12U) +#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(r) (((r) >> 12U) & 0x1U) +#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(v) (((v)&0xffU) << 16U) +#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m() (U32(0xffU) << 16U) +#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(r) (((r) >> 16U) & 0xffU) +#define trim_sys_nvlink0_ctrl_r() (0x00132420U) +#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(v) (((v)&0x1U) << 0U) +#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m() (U32(0x1U) << 0U) +#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(r) (((r) >> 0U) & 0x1U) +#define trim_sys_nvlink0_status_r() (0x00132424U) +#define trim_sys_nvlink0_status_pll_off_f(v) (((v)&0x1U) << 5U) +#define trim_sys_nvlink0_status_pll_off_m() (U32(0x1U) << 5U) +#define trim_sys_nvlink0_status_pll_off_v(r) (((r) >> 5U) & 0x1U) +#define trim_sys_nvl_common_clk_alt_switch_r() (0x001371c4U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_f(v) (((v)&0x3U) << 16U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_m() (U32(0x3U) << 16U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_v(r) (((r) >> 16U) & 0x3U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v() (0x00000003U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f() (0x30000U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v() (0x00000000U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f() (0x0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_f(v) (((v)&0x3U) << 0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_m() (U32(0x3U) << 0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_v(r) (((r) >> 0U) & 0x3U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v() (0x00000000U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f() (0x0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v() (0x00000002U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f() (0x2U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v() (0x00000003U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f() (0x3U) +#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r() (0x00132a70U) +#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f() (0x10000000U) +#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r() (0x00132a74U) +#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r() (0x00132a78U) +#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r() (0x00136470U) +#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f() (0x10000000U) +#define trim_sys_fll_fr_clk_cntr_xbarclk_cntr0_r() (0x00136474U) +#define trim_sys_fll_fr_clk_cntr_xbarclk_cntr1_r() (0x00136478U) +#define trim_sys_fr_clk_cntr_sysclk_cfg_r() (0x0013762cU) +#define trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f() (0x20000000U) +#define trim_sys_fr_clk_cntr_sysclk_cntr0_r() (0x00137630U) +#define trim_sys_fr_clk_cntr_sysclk_cntr1_r() (0x00137634U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h index a392eac96..98971eae2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,40 +59,13 @@ #include #include -static inline u32 usermode_cfg0_r(void) -{ - return 0x00810000U; -} -static inline u32 usermode_cfg0_class_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 usermode_cfg0_class_id_value_v(void) -{ - return 0x0000c361U; -} -static inline u32 usermode_time_0_r(void) -{ - return 0x00810080U; -} -static inline u32 usermode_time_0_nsec_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 usermode_time_1_r(void) -{ - return 0x00810084U; -} -static inline u32 usermode_time_1_nsec_f(u32 v) -{ - return (v & 0x1fffffffU) << 0U; -} -static inline u32 usermode_notify_channel_pending_r(void) -{ - return 0x00810090U; -} -static inline u32 usermode_notify_channel_pending_id_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} +#define usermode_cfg0_r() (0x00810000U) +#define usermode_cfg0_class_id_f(v) (((v)&0xffffU) << 0U) +#define usermode_cfg0_class_id_value_v() (0x0000c361U) +#define usermode_time_0_r() (0x00810080U) +#define usermode_time_0_nsec_f(v) (((v)&0x7ffffffU) << 5U) +#define usermode_time_1_r() (0x00810084U) +#define usermode_time_1_nsec_f(v) (((v)&0x1fffffffU) << 0U) +#define usermode_notify_channel_pending_r() (0x00810090U) +#define usermode_notify_channel_pending_id_f(v) (((v)&0xffffffffU) << 0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h index e33498c5a..ad2e26b35 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,88 +59,27 @@ #include #include -static inline u32 xp_dl_mgr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 xp_dl_mgr_safe_timing_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 xp_pl_link_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) -{ - return (v & 0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_m(void) -{ - return U32(0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) -{ - return 0x00000002U; -} -static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_m(void) -{ - return U32(0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) -{ - return 0x00000007U; -} -static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) -{ - return 0x00000006U; -} -static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) -{ - return 0x00000005U; -} -static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) -{ - return 0x00000004U; -} -static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) -{ - return 0x00000000U; -} +#define xp_dl_mgr_r(i)\ + (nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32((i), 4U))) +#define xp_dl_mgr_safe_timing_f(v) (((v)&0x1U) << 2U) +#define xp_pl_link_config_r(i)\ + (nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32((i), 4U))) +#define xp_pl_link_config_ltssm_status_f(v) (((v)&0x1U) << 4U) +#define xp_pl_link_config_ltssm_status_idle_v() (0x00000000U) +#define xp_pl_link_config_ltssm_directive_f(v) (((v)&0xfU) << 0U) +#define xp_pl_link_config_ltssm_directive_m() (U32(0xfU) << 0U) +#define xp_pl_link_config_ltssm_directive_normal_operations_v() (0x00000000U) +#define xp_pl_link_config_ltssm_directive_change_speed_v() (0x00000001U) +#define xp_pl_link_config_max_link_rate_f(v) (((v)&0x3U) << 18U) +#define xp_pl_link_config_max_link_rate_m() (U32(0x3U) << 18U) +#define xp_pl_link_config_max_link_rate_2500_mtps_v() (0x00000002U) +#define xp_pl_link_config_max_link_rate_5000_mtps_v() (0x00000001U) +#define xp_pl_link_config_max_link_rate_8000_mtps_v() (0x00000000U) +#define xp_pl_link_config_target_tx_width_f(v) (((v)&0x7U) << 20U) +#define xp_pl_link_config_target_tx_width_m() (U32(0x7U) << 20U) +#define xp_pl_link_config_target_tx_width_x1_v() (0x00000007U) +#define xp_pl_link_config_target_tx_width_x2_v() (0x00000006U) +#define xp_pl_link_config_target_tx_width_x4_v() (0x00000005U) +#define xp_pl_link_config_target_tx_width_x8_v() (0x00000004U) +#define xp_pl_link_config_target_tx_width_x16_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h index 6f43b53f4..eee0d684d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,152 +59,41 @@ #include #include -static inline u32 xve_rom_ctrl_r(void) -{ - return 0x00000050U; -} -static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) -{ - return 0x0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) -{ - return 0x1U; -} -static inline u32 xve_link_control_status_r(void) -{ - return 0x00000088U; -} -static inline u32 xve_link_control_status_link_speed_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 xve_link_control_status_link_speed_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) -{ - return 0x00000003U; -} -static inline u32 xve_link_control_status_link_width_m(void) -{ - return U32(0x3fU) << 20U; -} -static inline u32 xve_link_control_status_link_width_v(u32 r) -{ - return (r >> 20U) & 0x3fU; -} -static inline u32 xve_link_control_status_link_width_x1_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_width_x2_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_width_x4_v(void) -{ - return 0x00000004U; -} -static inline u32 xve_link_control_status_link_width_x8_v(void) -{ - return 0x00000008U; -} -static inline u32 xve_link_control_status_link_width_x16_v(void) -{ - return 0x00000010U; -} -static inline u32 xve_priv_xv_r(void) -{ - return 0x00000150U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 xve_cya_2_r(void) -{ - return 0x00000704U; -} -static inline u32 xve_reset_r(void) -{ - return 0x00000718U; -} -static inline u32 xve_reset_reset_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 xve_reset_gpu_on_sw_reset_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 xve_reset_counter_en_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 xve_reset_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_m(void) -{ - return U32(0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_v(u32 r) -{ - return (r >> 4U) & 0x7ffU; -} -static inline u32 xve_reset_clock_on_sw_reset_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 xve_reset_clock_counter_en_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 xve_reset_clock_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_m(void) -{ - return U32(0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_v(u32 r) -{ - return (r >> 17U) & 0x7ffU; -} +#define xve_rom_ctrl_r() (0x00000050U) +#define xve_rom_ctrl_rom_shadow_f(v) (((v)&0x1U) << 0U) +#define xve_rom_ctrl_rom_shadow_disabled_f() (0x0U) +#define xve_rom_ctrl_rom_shadow_enabled_f() (0x1U) +#define xve_link_control_status_r() (0x00000088U) +#define xve_link_control_status_link_speed_m() (U32(0xfU) << 16U) +#define xve_link_control_status_link_speed_v(r) (((r) >> 16U) & 0xfU) +#define xve_link_control_status_link_speed_link_speed_2p5_v() (0x00000001U) +#define xve_link_control_status_link_speed_link_speed_5p0_v() (0x00000002U) +#define xve_link_control_status_link_speed_link_speed_8p0_v() (0x00000003U) +#define xve_link_control_status_link_width_m() (U32(0x3fU) << 20U) +#define xve_link_control_status_link_width_v(r) (((r) >> 20U) & 0x3fU) +#define xve_link_control_status_link_width_x1_v() (0x00000001U) +#define xve_link_control_status_link_width_x2_v() (0x00000002U) +#define xve_link_control_status_link_width_x4_v() (0x00000004U) +#define xve_link_control_status_link_width_x8_v() (0x00000008U) +#define xve_link_control_status_link_width_x16_v() (0x00000010U) +#define xve_priv_xv_r() (0x00000150U) +#define xve_priv_xv_cya_l0s_enable_f(v) (((v)&0x1U) << 7U) +#define xve_priv_xv_cya_l0s_enable_m() (U32(0x1U) << 7U) +#define xve_priv_xv_cya_l0s_enable_v(r) (((r) >> 7U) & 0x1U) +#define xve_priv_xv_cya_l1_enable_f(v) (((v)&0x1U) << 8U) +#define xve_priv_xv_cya_l1_enable_m() (U32(0x1U) << 8U) +#define xve_priv_xv_cya_l1_enable_v(r) (((r) >> 8U) & 0x1U) +#define xve_cya_2_r() (0x00000704U) +#define xve_reset_r() (0x00000718U) +#define xve_reset_reset_m() (U32(0x1U) << 0U) +#define xve_reset_gpu_on_sw_reset_m() (U32(0x1U) << 1U) +#define xve_reset_counter_en_m() (U32(0x1U) << 2U) +#define xve_reset_counter_val_f(v) (((v)&0x7ffU) << 4U) +#define xve_reset_counter_val_m() (U32(0x7ffU) << 4U) +#define xve_reset_counter_val_v(r) (((r) >> 4U) & 0x7ffU) +#define xve_reset_clock_on_sw_reset_m() (U32(0x1U) << 15U) +#define xve_reset_clock_counter_en_m() (U32(0x1U) << 16U) +#define xve_reset_clock_counter_val_f(v) (((v)&0x7ffU) << 17U) +#define xve_reset_clock_counter_val_m() (U32(0x7ffU) << 17U) +#define xve_reset_clock_counter_val_v(r) (((r) >> 17U) & 0x7ffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h index cbd6c8052..40ad9b382 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,184 +59,49 @@ #include #include -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} +#define bus_bar0_window_r() (0x00001700U) +#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) +#define bus_bar0_window_target_vid_mem_f() (0x0U) +#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) +#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) +#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) +#define bus_bar1_block_r() (0x00001704U) +#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar1_block_target_vid_mem_f() (0x0U) +#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar1_block_mode_virtual_f() (0x80000000U) +#define bus_bar2_block_r() (0x00001714U) +#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar2_block_target_vid_mem_f() (0x0U) +#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar2_block_mode_virtual_f() (0x80000000U) +#define bus_bar1_block_ptr_shift_v() (0x0000000cU) +#define bus_bar2_block_ptr_shift_v() (0x0000000cU) +#define bus_bind_status_r() (0x00001710U) +#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U) +#define bus_bind_status_bar1_pending_empty_f() (0x0U) +#define bus_bind_status_bar1_pending_busy_f() (0x1U) +#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define bus_bind_status_bar1_outstanding_false_f() (0x0U) +#define bus_bind_status_bar1_outstanding_true_f() (0x2U) +#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U) +#define bus_bind_status_bar2_pending_empty_v() (0x00000000U) +#define bus_bind_status_bar2_pending_empty_f() (0x0U) +#define bus_bind_status_bar2_pending_busy_v() (0x00000001U) +#define bus_bind_status_bar2_pending_busy_f() (0x4U) +#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U) +#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U) +#define bus_bind_status_bar2_outstanding_false_f() (0x0U) +#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U) +#define bus_bind_status_bar2_outstanding_true_f() (0x8U) +#define bus_intr_0_r() (0x00001100U) +#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U) +#define bus_intr_en_0_r() (0x00001140U) +#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index f4e4982a6..3178e8de8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,172 +59,48 @@ #include #include -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_in_use_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 ccsr_channel_status_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acquire_v(void) -{ - return 0x00000003U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_v(void) -{ - return 0x00000005U; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void) -{ - return 0x00000006U; -} -static inline u32 ccsr_channel_status_on_eng_v(void) -{ - return 0x00000007U; -} -static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void) -{ - return 0x00000008U; -} -static inline u32 ccsr_channel_status_on_eng_pending_v(void) -{ - return 0x00000009U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) -{ - return 0x400000U; -} -static inline u32 ccsr_channel_eng_faulted_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 ccsr_channel_eng_faulted_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 ccsr_channel_eng_faulted_reset_f(void) -{ - return 0x800000U; -} -static inline u32 ccsr_channel_eng_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ccsr_channel_busy_true_v(void) -{ - return 0x00000001U; -} +#define ccsr_channel_inst_r(i)\ + (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel_inst__size_1_v() (0x00000200U) +#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define ccsr_channel_inst_target_vid_mem_f() (0x0U) +#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) +#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) +#define ccsr_channel_inst_bind_false_f() (0x0U) +#define ccsr_channel_inst_bind_true_f() (0x80000000U) +#define ccsr_channel_r(i)\ + (nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel__size_1_v() (0x00000200U) +#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) +#define ccsr_channel_enable_in_use_v() (0x00000001U) +#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) +#define ccsr_channel_enable_set_true_f() (0x400U) +#define ccsr_channel_enable_clr_true_f() (0x800U) +#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) +#define ccsr_channel_status_idle_v() (0x00000000U) +#define ccsr_channel_status_pending_v() (0x00000001U) +#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U) +#define ccsr_channel_status_pending_acquire_v() (0x00000003U) +#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U) +#define ccsr_channel_status_on_pbdma_v() (0x00000005U) +#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U) +#define ccsr_channel_status_on_eng_v() (0x00000007U) +#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U) +#define ccsr_channel_status_on_eng_pending_v() (0x00000009U) +#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU) +#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU) +#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU) +#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU) +#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU) +#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) +#define ccsr_channel_next_true_v() (0x00000001U) +#define ccsr_channel_force_ctx_reload_true_f() (0x100U) +#define ccsr_channel_pbdma_faulted_f(v) (((v)&0x1U) << 22U) +#define ccsr_channel_pbdma_faulted_reset_f() (0x400000U) +#define ccsr_channel_eng_faulted_f(v) (((v)&0x1U) << 23U) +#define ccsr_channel_eng_faulted_v(r) (((r) >> 23U) & 0x1U) +#define ccsr_channel_eng_faulted_reset_f() (0x800000U) +#define ccsr_channel_eng_faulted_true_v() (0x00000001U) +#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U) +#define ccsr_channel_busy_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index 0c6dc9fd6..6a75115ba 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,52 +59,17 @@ #include #include -static inline u32 ce_intr_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32(i, 128U)); -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_invalid_config_pending_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_invalid_config_reset_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) -{ - return 0x10U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) -{ - return 0x10U; -} -static inline u32 ce_pce_map_r(void) -{ - return 0x00104028U; -} +#define ce_intr_status_r(i)\ + (nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U))) +#define ce_intr_status_blockpipe_pending_f() (0x1U) +#define ce_intr_status_blockpipe_reset_f() (0x1U) +#define ce_intr_status_nonblockpipe_pending_f() (0x2U) +#define ce_intr_status_nonblockpipe_reset_f() (0x2U) +#define ce_intr_status_launcherr_pending_f() (0x4U) +#define ce_intr_status_launcherr_reset_f() (0x4U) +#define ce_intr_status_invalid_config_pending_f() (0x8U) +#define ce_intr_status_invalid_config_reset_f() (0x8U) +#define ce_intr_status_mthd_buffer_fault_pending_f() (0x10U) +#define ce_intr_status_mthd_buffer_fault_reset_f() (0x10U) +#define ce_pce_map_r() (0x00104028U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index 84ce647ad..58349d0cf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,412 +59,123 @@ #include #include -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_gpccs_header_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) -{ - return 0x00000011U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) -{ - return 0x00000012U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) -{ - return 0x00000021U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) -{ - return 0x00000094U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) -{ - return 0x00000064U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) -{ - return 0x00000074U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) -{ - return 0x00000078U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) -{ - return 0x0000007cU; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) -{ - return 0x000000b8U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) -{ - return 0x000000bcU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) -{ - return 0x000000c0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) -{ - return 0x000000c4U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) -{ - return 0x000000c8U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) -{ - return 0x000000ccU; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) -{ - return 0x000000e0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) -{ - return 0x000000e4U; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} +#define ctxsw_prog_fecs_header_v() (0x00000100U) +#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) +#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) +#define ctxsw_prog_main_image_ctl_o() (0x0000000cU) +#define ctxsw_prog_main_image_ctl_type_f(v) (((v)&0x3fU) << 0U) +#define ctxsw_prog_main_image_ctl_type_undefined_v() (0x00000000U) +#define ctxsw_prog_main_image_ctl_type_opengl_v() (0x00000008U) +#define ctxsw_prog_main_image_ctl_type_dx9_v() (0x00000010U) +#define ctxsw_prog_main_image_ctl_type_dx10_v() (0x00000011U) +#define ctxsw_prog_main_image_ctl_type_dx11_v() (0x00000012U) +#define ctxsw_prog_main_image_ctl_type_compute_v() (0x00000020U) +#define ctxsw_prog_main_image_ctl_type_per_veid_header_v() (0x00000021U) +#define ctxsw_prog_main_image_patch_count_o() (0x00000010U) +#define ctxsw_prog_main_image_context_id_o() (0x000000f0U) +#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U) +#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U) +#define ctxsw_prog_main_image_zcull_o() (0x0000001cU) +#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U) +#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U) +#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U) +#define ctxsw_prog_main_image_pm_o() (0x00000028U) +#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U) +#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U) +#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f() (0x2U) +#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) +#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) +#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) +#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) +#define ctxsw_prog_main_image_num_wfi_save_ops_o() (0x000000d0U) +#define ctxsw_prog_main_image_num_cta_save_ops_o() (0x000000d4U) +#define ctxsw_prog_main_image_num_gfxp_save_ops_o() (0x000000d8U) +#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU) +#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) +#define ctxsw_prog_main_image_zcull_ptr_hi_o() (0x00000060U) +#define ctxsw_prog_main_image_zcull_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_pm_ptr_hi_o() (0x00000094U) +#define ctxsw_prog_main_image_full_preemption_ptr_hi_o() (0x00000064U) +#define ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) +#define ctxsw_prog_main_image_full_preemption_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o() (0x00000070U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_o() (0x00000074U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_context_buffer_ptr_hi_o() (0x00000078U) +#define ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_context_buffer_ptr_o() (0x0000007cU) +#define ctxsw_prog_main_image_context_buffer_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) +#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) +#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) +#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_image_global_cb_ptr_o() (0x000000b8U) +#define ctxsw_prog_main_image_global_cb_ptr_v_f(v) (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_global_cb_ptr_hi_o() (0x000000bcU) +#define ctxsw_prog_main_image_global_cb_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_o() (0x000000c0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_hi_o() (0x000000c4U) +#define ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_control_block_ptr_o() (0x000000c8U) +#define ctxsw_prog_main_image_control_block_ptr_v_f(v) (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_control_block_ptr_hi_o() (0x000000ccU) +#define ctxsw_prog_main_image_control_block_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o() (0x000000e0U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o() (0x000000e4U) +#define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) +#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) +#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U) +#define ctxsw_prog_local_magic_value_o() (0x000000fcU) +#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU) +#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU) +#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU) +#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U) +#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\ + (0x00000000U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\ + (0x00000002U) +#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ + (((r) >> 0U) & 0x3U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U) +#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U) +#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U) +#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU) +#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U) +#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) +#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ + (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) +#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 67e4fbf57..c859019f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,548 +59,145 @@ #include #include -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} +#define falcon_falcon_irqsset_r() (0x00000000U) +#define falcon_falcon_irqsset_swgen0_set_f() (0x40U) +#define falcon_falcon_irqsclr_r() (0x00000004U) +#define falcon_falcon_irqstat_r() (0x00000008U) +#define falcon_falcon_irqstat_halt_true_f() (0x10U) +#define falcon_falcon_irqstat_exterr_true_f() (0x20U) +#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) +#define falcon_falcon_irqmode_r() (0x0000000cU) +#define falcon_falcon_irqmset_r() (0x00000010U) +#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_r() (0x00000014U) +#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqmask_r() (0x00000018U) +#define falcon_falcon_irqdest_r() (0x0000001cU) +#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define falcon_falcon_curctx_r() (0x00000050U) +#define falcon_falcon_nxtctx_r() (0x00000054U) +#define falcon_falcon_mailbox0_r() (0x00000040U) +#define falcon_falcon_mailbox1_r() (0x00000044U) +#define falcon_falcon_itfen_r() (0x00000048U) +#define falcon_falcon_itfen_ctxen_enable_f() (0x1U) +#define falcon_falcon_idlestate_r() (0x0000004cU) +#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define falcon_falcon_os_r() (0x00000080U) +#define falcon_falcon_engctl_r() (0x000000a4U) +#define falcon_falcon_cpuctl_r() (0x00000100U) +#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define falcon_falcon_cpuctl_alias_r() (0x00000130U) +#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) +#define falcon_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_sctl_r() (0x00000240U) +#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define falcon_falcon_bootvec_r() (0x00000104U) +#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define falcon_falcon_dmactl_r() (0x0000010cU) +#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_hwcfg_r() (0x00000108U) +#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define falcon_falcon_dmatrfbase_r() (0x00000110U) +#define falcon_falcon_dmatrfbase1_r() (0x00000128U) +#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) +#define falcon_falcon_dmatrfcmd_r() (0x00000118U) +#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) +#define falcon_falcon_imctl_debug_r() (0x0000015cU) +#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) +#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) +#define falcon_falcon_imstat_r() (0x00000144U) +#define falcon_falcon_traceidx_r() (0x00000148U) +#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) +#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) +#define falcon_falcon_tracepc_r() (0x0000014cU) +#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) +#define falcon_falcon_exterraddr_r() (0x0010a168U) +#define falcon_falcon_exterrstat_r() (0x0010a16cU) +#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) +#define falcon_falcon_icd_cmd_r() (0x00000200U) +#define falcon_falcon_icd_cmd_opc_s() (4U) +#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define falcon_falcon_icd_rdata_r() (0x0000020cU) +#define falcon_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define falcon_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_debug1_r() (0x00000090U) +#define falcon_falcon_debug1_ctxsw_mode_s() (1U) +#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define falcon_falcon_debuginfo_r() (0x00000094U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 6acbf0f85..afd94acdb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,1836 +59,502 @@ #include #include -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void) -{ - return U32(0x1U) << 26U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_r(void) -{ - return 0x001fbc20U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return U32(0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return U32(0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return U32(0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return U32(0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_l2tlb_ecc_control_r(void) -{ - return 0x00100e6cU; -} -static inline u32 fb_mmu_l2tlb_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_r(void) -{ - return 0x00100e70U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e74U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e78U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_r(void) -{ - return 0x00100e7cU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_control_r(void) -{ - return 0x00100e80U; -} -static inline u32 fb_mmu_hubtlb_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_r(void) -{ - return 0x00100e84U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e88U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e8cU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_address_r(void) -{ - return 0x00100e90U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fillunit_ecc_control_r(void) -{ - return 0x00100e94U; -} -static inline u32 fb_mmu_fillunit_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 fb_mmu_fillunit_ecc_status_r(void) -{ - return 0x00100e98U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) -{ - return 0x00100e9cU; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) -{ - return 0x00100ea0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_address_r(void) -{ - return 0x00100ea4U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_niso_intr_r(void) -{ - return 0x00100a20U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) -{ - return U32(0x1U) << 26U; -} -static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) -{ - return (v & 0x1U) << 26U; -} -static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en_set__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) -{ - return U32(0x1U) << 26U; -} -static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_clr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a34U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en_clr__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) -{ - return U32(0x1U) << 26U; -} -static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) -{ - return (r >> 1U) & 0x3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x6U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_b(void) -{ - return 12U; -} -static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_buffer_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) -{ - return U32(0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_addr_lo_r(void) -{ - return 0x00100e4cU; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_addr_lo_addr_b(void) -{ - return 12U; -} -static inline u32 fb_mmu_fault_addr_hi_r(void) -{ - return 0x00100e50U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_inst_lo_r(void) -{ - return 0x00100e54U; -} -static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_inst_lo_addr_b(void) -{ - return 12U; -} -static inline u32 fb_mmu_fault_inst_hi_r(void) -{ - return 0x00100e58U; -} -static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_info_r(void) -{ - return 0x00100e5cU; -} -static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fb_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_status_r(void) -{ - return 0x00100e60U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_replayable_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fb_mmu_fault_status_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_set_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_fault_status_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) -{ - return 0x200U; -} -static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_error_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) -{ - return 0x400U; -} -static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) -{ - return 0x1000U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) -{ - return 0x2000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) -{ - return U32(0x1U) << 14U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) -{ - return 0x4000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) -{ - return 0x8000U; -} -static inline u32 fb_mmu_fault_status_busy_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_mmu_fault_status_busy_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_busy_true_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_status_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_status_valid_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_status_valid_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_num_active_ltcs_r(void) -{ - return 0x00100ec0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_cbc_base_r(void) -{ - return 0x00100ec4U; -} -static inline u32 fb_mmu_cbc_base_address_f(u32 v) -{ - return (v & 0x3ffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_top_r(void) -{ - return 0x00100ec8U; -} -static inline u32 fb_mmu_cbc_top_size_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 fb_mmu_cbc_top_size_v(u32 r) -{ - return (r >> 0U) & 0x7fffU; -} -static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_max_r(void) -{ - return 0x00100eccU; -} -static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 fb_mmu_cbc_max_safe_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_cbc_max_safe_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_cbc_max_safe_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) -{ - return 0x00000001U; -} +#define fb_fbhub_num_active_ltcs_r() (0x00100800U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f() (0x2000000U) +#define fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m() (U32(0x1U) << 26U) +#define fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f() (0x0U) +#define fb_mmu_ctrl_r() (0x00100c80U) +#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) +#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) +#define fb_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define fb_mmu_ctrl_atomic_capability_mode_l2_f() (0x0U) +#define fb_mmu_ctrl_atomic_capability_mode_rmw_f() (0x2000000U) +#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m() (U32(0x1U) << 27U) +#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f() (0x0U) +#define fb_hshub_num_active_ltcs_r() (0x001fbc20U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f() (0x0U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f() (0x2000000U) +#define fb_priv_mmu_phy_secure_r() (0x00100ce4U) +#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) +#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) +#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_invalidate_r() (0x00100cbcU) +#define fb_mmu_invalidate_all_va_true_f() (0x1U) +#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) +#define fb_mmu_invalidate_hubtlb_only_s() (1U) +#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) +#define fb_mmu_invalidate_replay_s() (3U) +#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) +#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) +#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) +#define fb_mmu_invalidate_replay_none_f() (0x0U) +#define fb_mmu_invalidate_replay_start_f() (0x8U) +#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U) +#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) +#define fb_mmu_invalidate_sys_membar_s() (1U) +#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) +#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) +#define fb_mmu_invalidate_ack_s() (2U) +#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) +#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) +#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) +#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) +#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) +#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) +#define fb_mmu_invalidate_cancel_client_id_s() (6U) +#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) +#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) +#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) +#define fb_mmu_invalidate_cancel_client_type_s() (1U) +#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) +#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) +#define fb_mmu_invalidate_cancel_cache_level_s() (3U) +#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) +#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) +#define fb_mmu_invalidate_cancel_cache_level_pte_only_f() (0x1000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f() (0x2000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f() (0x3000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f() (0x4000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f() (0x5000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) +#define fb_mmu_invalidate_trigger_s() (1U) +#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) +#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) +#define fb_mmu_debug_wr_r() (0x00100cc8U) +#define fb_mmu_debug_wr_aperture_s() (2U) +#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_wr_vol_false_f() (0x0U) +#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) +#define fb_mmu_debug_wr_vol_true_f() (0x4U) +#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_rd_r() (0x00100cccU) +#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_rd_vol_false_f() (0x0U) +#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_ctrl_r() (0x00100cc4U) +#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_mmu_vpr_info_r() (0x00100cd0U) +#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U) +#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U) +#define fb_mmu_l2tlb_ecc_control_r() (0x00100e6cU) +#define fb_mmu_l2tlb_ecc_control_inject_uncorrected_err_f(v) (((v)&0x1U) << 5U) +#define fb_mmu_l2tlb_ecc_status_r() (0x00100e70U) +#define fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()\ + (U32(0x1U) << 0U) +#define fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m()\ + (U32(0x1U) << 1U) +#define fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define fb_mmu_l2tlb_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_l2tlb_ecc_status_reset_clear_f() (0x40000000U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_r() (0x00100e74U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_s() (16U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_v(r) (((r) >> 0U) & 0xffffU) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_r() (0x00100e78U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s() (16U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_l2tlb_ecc_address_r() (0x00100e7cU) +#define fb_mmu_l2tlb_ecc_address_index_s() (32U) +#define fb_mmu_l2tlb_ecc_address_index_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_l2tlb_ecc_address_index_m() (U32(0xffffffffU) << 0U) +#define fb_mmu_l2tlb_ecc_address_index_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_hubtlb_ecc_control_r() (0x00100e80U) +#define fb_mmu_hubtlb_ecc_control_inject_uncorrected_err_f(v) (((v)&0x1U) << 5U) +#define fb_mmu_hubtlb_ecc_status_r() (0x00100e84U) +#define fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m() (U32(0x1U) << 0U) +#define fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m() (U32(0x1U) << 1U) +#define fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define fb_mmu_hubtlb_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_hubtlb_ecc_status_reset_clear_f() (0x40000000U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_r() (0x00100e88U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_s() (16U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_v(r) (((r) >> 0U) & 0xffffU) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_r() (0x00100e8cU) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s() (16U) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_hubtlb_ecc_address_r() (0x00100e90U) +#define fb_mmu_hubtlb_ecc_address_index_s() (32U) +#define fb_mmu_hubtlb_ecc_address_index_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_hubtlb_ecc_address_index_m() (U32(0xffffffffU) << 0U) +#define fb_mmu_hubtlb_ecc_address_index_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fillunit_ecc_control_r() (0x00100e94U) +#define fb_mmu_fillunit_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 5U) +#define fb_mmu_fillunit_ecc_status_r() (0x00100e98U) +#define fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m() (U32(0x1U) << 0U) +#define fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m()\ + (U32(0x1U) << 1U) +#define fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m() (U32(0x1U) << 2U) +#define fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m()\ + (U32(0x1U) << 3U) +#define fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define fb_mmu_fillunit_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fillunit_ecc_status_reset_clear_f() (0x40000000U) +#define fb_mmu_fillunit_ecc_corrected_err_count_r() (0x00100e9cU) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_s() (16U) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_r() (0x00100ea0U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_s() (16U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_fillunit_ecc_address_r() (0x00100ea4U) +#define fb_mmu_fillunit_ecc_address_index_s() (32U) +#define fb_mmu_fillunit_ecc_address_index_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fillunit_ecc_address_index_m() (U32(0xffffffffU) << 0U) +#define fb_mmu_fillunit_ecc_address_index_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_niso_flush_sysmem_addr_r() (0x00100c10U) +#define fb_niso_intr_r() (0x00100a20U) +#define fb_niso_intr_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_hub_access_counter_notify_pending_f() (0x1U) +#define fb_niso_intr_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_hub_access_counter_error_pending_f() (0x2U) +#define fb_niso_intr_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_mmu_replayable_fault_notify_pending_f() (0x8000000U) +#define fb_niso_intr_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_mmu_replayable_fault_overflow_pending_f() (0x10000000U) +#define fb_niso_intr_mmu_nonreplayable_fault_notify_m() (U32(0x1U) << 29U) +#define fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() (0x20000000U) +#define fb_niso_intr_mmu_nonreplayable_fault_overflow_m() (U32(0x1U) << 30U) +#define fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f() (0x40000000U) +#define fb_niso_intr_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_mmu_other_fault_notify_pending_f() (0x80000000U) +#define fb_niso_intr_mmu_ecc_uncorrected_error_notify_m() (U32(0x1U) << 26U) +#define fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f() (0x4000000U) +#define fb_niso_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en__size_1_v() (0x00000002U) +#define fb_niso_intr_en_hub_access_counter_notify_f(v) (((v)&0x1U) << 0U) +#define fb_niso_intr_en_hub_access_counter_notify_enabled_f() (0x1U) +#define fb_niso_intr_en_hub_access_counter_error_f(v) (((v)&0x1U) << 1U) +#define fb_niso_intr_en_hub_access_counter_error_enabled_f() (0x2U) +#define fb_niso_intr_en_mmu_replayable_fault_notify_f(v) (((v)&0x1U) << 27U) +#define fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f() (0x8000000U) +#define fb_niso_intr_en_mmu_replayable_fault_overflow_f(v) (((v)&0x1U) << 28U) +#define fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f() (0x10000000U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(v) (((v)&0x1U) << 29U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f() (0x20000000U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(v)\ + (((v)&0x1U) << 30U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f()\ + (0x40000000U) +#define fb_niso_intr_en_mmu_other_fault_notify_f(v) (((v)&0x1U) << 31U) +#define fb_niso_intr_en_mmu_other_fault_notify_enabled_f() (0x80000000U) +#define fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(v)\ + (((v)&0x1U) << 26U) +#define fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f()\ + (0x4000000U) +#define fb_niso_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en_set__size_1_v() (0x00000002U) +#define fb_niso_intr_en_set_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_en_set_hub_access_counter_notify_set_f() (0x1U) +#define fb_niso_intr_en_set_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_en_set_hub_access_counter_error_set_f() (0x2U) +#define fb_niso_intr_en_set_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f() (0x8000000U) +#define fb_niso_intr_en_set_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f() (0x10000000U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m()\ + (U32(0x1U) << 29U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f() (0x20000000U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m()\ + (U32(0x1U) << 30U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f()\ + (0x40000000U) +#define fb_niso_intr_en_set_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_en_set_mmu_other_fault_notify_set_f() (0x80000000U) +#define fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m()\ + (U32(0x1U) << 26U) +#define fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f()\ + (0x4000000U) +#define fb_niso_intr_en_clr_r(i)\ + (nvgpu_safe_add_u32(0x00100a34U, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en_clr__size_1_v() (0x00000002U) +#define fb_niso_intr_en_clr_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_en_clr_hub_access_counter_notify_set_f() (0x1U) +#define fb_niso_intr_en_clr_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_en_clr_hub_access_counter_error_set_f() (0x2U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f() (0x8000000U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f() (0x10000000U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m()\ + (U32(0x1U) << 29U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f() (0x20000000U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m()\ + (U32(0x1U) << 30U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f()\ + (0x40000000U) +#define fb_niso_intr_en_clr_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_en_clr_mmu_other_fault_notify_set_f() (0x80000000U) +#define fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m()\ + (U32(0x1U) << 26U) +#define fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f()\ + (0x4000000U) +#define fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v() (0x00000000U) +#define fb_niso_intr_en_clr_mmu_replay_fault_buffer_v() (0x00000001U) +#define fb_mmu_fault_buffer_lo_r(i)\ + (nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_lo__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_lo_addr_mode_f(v) (((v)&0x1U) << 0U) +#define fb_mmu_fault_buffer_lo_addr_mode_v(r) (((r) >> 0U) & 0x1U) +#define fb_mmu_fault_buffer_lo_addr_mode_virtual_v() (0x00000000U) +#define fb_mmu_fault_buffer_lo_addr_mode_virtual_f() (0x0U) +#define fb_mmu_fault_buffer_lo_addr_mode_physical_v() (0x00000001U) +#define fb_mmu_fault_buffer_lo_addr_mode_physical_f() (0x1U) +#define fb_mmu_fault_buffer_lo_phys_aperture_f(v) (((v)&0x3U) << 1U) +#define fb_mmu_fault_buffer_lo_phys_aperture_v(r) (((r) >> 1U) & 0x3U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f() (0x4U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f() (0x6U) +#define fb_mmu_fault_buffer_lo_phys_vol_f(v) (((v)&0x1U) << 3U) +#define fb_mmu_fault_buffer_lo_phys_vol_v(r) (((r) >> 3U) & 0x1U) +#define fb_mmu_fault_buffer_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_buffer_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_buffer_lo_addr_b() (12U) +#define fb_mmu_fault_buffer_hi_r(i)\ + (nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_hi__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_hi_addr_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fault_buffer_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_buffer_get_r(i)\ + (nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_get__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_get_ptr_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_get_ptr_m() (U32(0xfffffU) << 0U) +#define fb_mmu_fault_buffer_get_ptr_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_get_getptr_corrupted_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_m() (U32(0x1U) << 30U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_v() (0x00000001U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_f() (0x40000000U) +#define fb_mmu_fault_buffer_get_overflow_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_get_overflow_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_buffer_get_overflow_clear_v() (0x00000001U) +#define fb_mmu_fault_buffer_get_overflow_clear_f() (0x80000000U) +#define fb_mmu_fault_buffer_put_r(i)\ + (nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_put__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_put_ptr_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_put_ptr_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_put_getptr_corrupted_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_f() (0x40000000U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_no_v() (0x00000000U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_no_f() (0x0U) +#define fb_mmu_fault_buffer_put_overflow_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_put_overflow_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_buffer_put_overflow_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_put_overflow_yes_f() (0x80000000U) +#define fb_mmu_fault_buffer_size_r(i)\ + (nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_size__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_size_val_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_size_val_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_size_overflow_intr_f(v) (((v)&0x1U) << 29U) +#define fb_mmu_fault_buffer_size_overflow_intr_v(r) (((r) >> 29U) & 0x1U) +#define fb_mmu_fault_buffer_size_overflow_intr_enable_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_overflow_intr_enable_f() (0x20000000U) +#define fb_mmu_fault_buffer_size_set_default_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_size_set_default_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_buffer_size_set_default_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_set_default_yes_f() (0x40000000U) +#define fb_mmu_fault_buffer_size_enable_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_size_enable_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_buffer_size_enable_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_buffer_size_enable_true_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_enable_true_f() (0x80000000U) +#define fb_mmu_fault_addr_lo_r() (0x00100e4cU) +#define fb_mmu_fault_addr_lo_phys_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_fault_addr_lo_phys_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f() (0x2U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f() (0x3U) +#define fb_mmu_fault_addr_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_addr_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_addr_lo_addr_b() (12U) +#define fb_mmu_fault_addr_hi_r() (0x00100e50U) +#define fb_mmu_fault_addr_hi_addr_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fault_addr_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_inst_lo_r() (0x00100e54U) +#define fb_mmu_fault_inst_lo_engine_id_v(r) (((r) >> 0U) & 0x1ffU) +#define fb_mmu_fault_inst_lo_aperture_v(r) (((r) >> 10U) & 0x3U) +#define fb_mmu_fault_inst_lo_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_inst_lo_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_inst_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_inst_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_inst_lo_addr_b() (12U) +#define fb_mmu_fault_inst_hi_r() (0x00100e58U) +#define fb_mmu_fault_inst_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_info_r() (0x00100e5cU) +#define fb_mmu_fault_info_fault_type_v(r) (((r) >> 0U) & 0x1fU) +#define fb_mmu_fault_info_replayable_fault_v(r) (((r) >> 7U) & 0x1U) +#define fb_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU) +#define fb_mmu_fault_info_access_type_v(r) (((r) >> 16U) & 0xfU) +#define fb_mmu_fault_info_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_fault_info_gpc_id_v(r) (((r) >> 24U) & 0x1fU) +#define fb_mmu_fault_info_protected_mode_v(r) (((r) >> 29U) & 0x1U) +#define fb_mmu_fault_info_replayable_fault_en_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_info_valid_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_status_r() (0x00100e60U) +#define fb_mmu_fault_status_dropped_bar1_phys_m() (U32(0x1U) << 0U) +#define fb_mmu_fault_status_dropped_bar1_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_phys_set_f() (0x1U) +#define fb_mmu_fault_status_dropped_bar1_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_phys_clear_f() (0x1U) +#define fb_mmu_fault_status_dropped_bar1_virt_m() (U32(0x1U) << 1U) +#define fb_mmu_fault_status_dropped_bar1_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_virt_set_f() (0x2U) +#define fb_mmu_fault_status_dropped_bar1_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_virt_clear_f() (0x2U) +#define fb_mmu_fault_status_dropped_bar2_phys_m() (U32(0x1U) << 2U) +#define fb_mmu_fault_status_dropped_bar2_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_phys_set_f() (0x4U) +#define fb_mmu_fault_status_dropped_bar2_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_phys_clear_f() (0x4U) +#define fb_mmu_fault_status_dropped_bar2_virt_m() (U32(0x1U) << 3U) +#define fb_mmu_fault_status_dropped_bar2_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_virt_set_f() (0x8U) +#define fb_mmu_fault_status_dropped_bar2_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_virt_clear_f() (0x8U) +#define fb_mmu_fault_status_dropped_ifb_phys_m() (U32(0x1U) << 4U) +#define fb_mmu_fault_status_dropped_ifb_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_phys_set_f() (0x10U) +#define fb_mmu_fault_status_dropped_ifb_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_phys_clear_f() (0x10U) +#define fb_mmu_fault_status_dropped_ifb_virt_m() (U32(0x1U) << 5U) +#define fb_mmu_fault_status_dropped_ifb_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_virt_set_f() (0x20U) +#define fb_mmu_fault_status_dropped_ifb_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_virt_clear_f() (0x20U) +#define fb_mmu_fault_status_dropped_other_phys_m() (U32(0x1U) << 6U) +#define fb_mmu_fault_status_dropped_other_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_phys_set_f() (0x40U) +#define fb_mmu_fault_status_dropped_other_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_phys_clear_f() (0x40U) +#define fb_mmu_fault_status_dropped_other_virt_m() (U32(0x1U) << 7U) +#define fb_mmu_fault_status_dropped_other_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_virt_set_f() (0x80U) +#define fb_mmu_fault_status_dropped_other_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_virt_clear_f() (0x80U) +#define fb_mmu_fault_status_replayable_m() (U32(0x1U) << 8U) +#define fb_mmu_fault_status_replayable_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_set_f() (0x100U) +#define fb_mmu_fault_status_replayable_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_m() (U32(0x1U) << 9U) +#define fb_mmu_fault_status_non_replayable_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_set_f() (0x200U) +#define fb_mmu_fault_status_non_replayable_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_error_m() (U32(0x1U) << 10U) +#define fb_mmu_fault_status_replayable_error_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_error_set_f() (0x400U) +#define fb_mmu_fault_status_replayable_error_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_error_m() (U32(0x1U) << 11U) +#define fb_mmu_fault_status_non_replayable_error_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_error_set_f() (0x800U) +#define fb_mmu_fault_status_non_replayable_error_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_overflow_m() (U32(0x1U) << 12U) +#define fb_mmu_fault_status_replayable_overflow_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_overflow_set_f() (0x1000U) +#define fb_mmu_fault_status_replayable_overflow_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_overflow_m() (U32(0x1U) << 13U) +#define fb_mmu_fault_status_non_replayable_overflow_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_overflow_set_f() (0x2000U) +#define fb_mmu_fault_status_non_replayable_overflow_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_m() (U32(0x1U) << 14U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_set_f() (0x4000U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_m()\ + (U32(0x1U) << 15U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v()\ + (0x00000001U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f() (0x8000U) +#define fb_mmu_fault_status_busy_m() (U32(0x1U) << 30U) +#define fb_mmu_fault_status_busy_true_v() (0x00000001U) +#define fb_mmu_fault_status_busy_true_f() (0x40000000U) +#define fb_mmu_fault_status_valid_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_status_valid_set_v() (0x00000001U) +#define fb_mmu_fault_status_valid_set_f() (0x80000000U) +#define fb_mmu_fault_status_valid_clear_v() (0x00000001U) +#define fb_mmu_fault_status_valid_clear_f() (0x80000000U) +#define fb_mmu_num_active_ltcs_r() (0x00100ec0U) +#define fb_mmu_num_active_ltcs_count_f(v) (((v)&0x1fU) << 0U) +#define fb_mmu_num_active_ltcs_count_v(r) (((r) >> 0U) & 0x1fU) +#define fb_mmu_cbc_base_r() (0x00100ec4U) +#define fb_mmu_cbc_base_address_f(v) (((v)&0x3ffffffU) << 0U) +#define fb_mmu_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define fb_mmu_cbc_base_address_alignment_shift_v() (0x0000000bU) +#define fb_mmu_cbc_top_r() (0x00100ec8U) +#define fb_mmu_cbc_top_size_f(v) (((v)&0x7fffU) << 0U) +#define fb_mmu_cbc_top_size_v(r) (((r) >> 0U) & 0x7fffU) +#define fb_mmu_cbc_top_size_alignment_shift_v() (0x0000000bU) +#define fb_mmu_cbc_max_r() (0x00100eccU) +#define fb_mmu_cbc_max_comptagline_f(v) (((v)&0xffffffU) << 0U) +#define fb_mmu_cbc_max_comptagline_v(r) (((r) >> 0U) & 0xffffffU) +#define fb_mmu_cbc_max_safe_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_cbc_max_safe_true_v() (0x00000001U) +#define fb_mmu_cbc_max_safe_false_v() (0x00000000U) +#define fb_mmu_cbc_max_unsafe_fault_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_cbc_max_unsafe_fault_enabled_v() (0x00000000U) +#define fb_mmu_cbc_max_unsafe_fault_disabled_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 8c628f3d4..fc6e278e4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,604 +59,170 @@ #include #include -static inline u32 fifo_userd_writeback_r(void) -{ - return 0x0000225cU; -} -static inline u32 fifo_userd_writeback_timer_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_userd_writeback_timer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_userd_writeback_timer_shorter_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_userd_writeback_timer_100us_v(void) -{ - return 0x00000064U; -} -static inline u32 fifo_userd_writeback_timescale_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fifo_userd_writeback_timescale_0_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270U; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274U; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10U; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_memop_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_memop_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_lb_error_r(void) -{ - return 0x0000258cU; -} -static inline u32 fifo_intr_ctxsw_timeout_r(void) -{ - return 0x00002a30U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) -{ - return 0x1U << (0U + i*1U); -} -static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) -{ - return (r >> 14U) & 0x3U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) -{ - return (r >> 0U) & 0x3fffU; -} -static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) -{ - return (r >> 16U) & 0x3fffU; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) -{ - return (r >> 30U) & 0x3U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) -{ - return 0x00000002U; -} -static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return U32(0x3fffffffU) << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_fb_timeout_period_init_f(void) -{ - return 0x3c00U; -} -static inline u32 fifo_fb_timeout_detection_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fifo_fb_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_fb_timeout_detection_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_runlist_preempt_r(void) -{ - return 0x00002638U; -} -static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_eng_reload_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_eng_ctxsw_timeout_r(void) -{ - return 0x00002a0cU; -} -static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 fifo_eng_ctxsw_timeout_period_m(void) -{ - return U32(0x7fffffffU) << 0U; -} -static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) -{ - return 0x3fffffU; -} -static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) -{ - return 0x7fffffffU; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) -{ - return 0x0U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_cfg0_r(void) -{ - return 0x00002004U; -} -static inline u32 fifo_cfg0_num_pbdma_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} +#define fifo_userd_writeback_r() (0x0000225cU) +#define fifo_userd_writeback_timer_f(v) (((v)&0xffU) << 0U) +#define fifo_userd_writeback_timer_disabled_v() (0x00000000U) +#define fifo_userd_writeback_timer_shorter_v() (0x00000003U) +#define fifo_userd_writeback_timer_100us_v() (0x00000064U) +#define fifo_userd_writeback_timescale_f(v) (((v)&0xfU) << 12U) +#define fifo_userd_writeback_timescale_0_v() (0x00000000U) +#define fifo_runlist_base_r() (0x00002270U) +#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define fifo_runlist_base_target_vid_mem_f() (0x0U) +#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) +#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) +#define fifo_runlist_r() (0x00002274U) +#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) +#define fifo_eng_runlist_base_r(i)\ + (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist_base__size_1_v() (0x00000002U) +#define fifo_eng_runlist_r(i)\ + (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_eng_runlist__size_1_v() (0x00000002U) +#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) +#define fifo_eng_runlist_length_max_v() (0x0000ffffU) +#define fifo_eng_runlist_pending_true_f() (0x100000U) +#define fifo_pb_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x00002350U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pb_timeslice_timeout_16_f() (0x10U) +#define fifo_pb_timeslice_timescale_0_f() (0x0U) +#define fifo_pb_timeslice_enable_true_f() (0x10000000U) +#define fifo_pbdma_map_r(i)\ + (nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_0_r() (0x00002100U) +#define fifo_intr_0_bind_error_pending_f() (0x1U) +#define fifo_intr_0_bind_error_reset_f() (0x1U) +#define fifo_intr_0_sched_error_pending_f() (0x100U) +#define fifo_intr_0_sched_error_reset_f() (0x100U) +#define fifo_intr_0_chsw_error_pending_f() (0x10000U) +#define fifo_intr_0_chsw_error_reset_f() (0x10000U) +#define fifo_intr_0_memop_timeout_pending_f() (0x800000U) +#define fifo_intr_0_memop_timeout_reset_f() (0x800000U) +#define fifo_intr_0_lb_error_pending_f() (0x1000000U) +#define fifo_intr_0_lb_error_reset_f() (0x1000000U) +#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U) +#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) +#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) +#define fifo_intr_0_ctxsw_timeout_pending_f() (0x2U) +#define fifo_intr_en_0_r() (0x00002140U) +#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) +#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) +#define fifo_intr_en_0_ctxsw_timeout_pending_f() (0x2U) +#define fifo_intr_en_1_r() (0x00002528U) +#define fifo_intr_bind_error_r() (0x0000252cU) +#define fifo_intr_sched_error_r() (0x0000254cU) +#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) +#define fifo_intr_chsw_error_r() (0x0000256cU) +#define fifo_intr_lb_error_r() (0x0000258cU) +#define fifo_intr_ctxsw_timeout_r() (0x00002a30U) +#define fifo_intr_ctxsw_timeout_engine_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_ctxsw_timeout_engine_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_ctxsw_timeout_engine__size_1_v() (0x00000020U) +#define fifo_intr_ctxsw_timeout_engine_pending_v() (0x00000001U) +#define fifo_intr_ctxsw_timeout_engine_pending_f(i)\ + ((0x1U << (0U +((i)*1U)))) +#define fifo_intr_ctxsw_timeout_info_r(i)\ + (nvgpu_safe_add_u32(0x00003200U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_ctxsw_timeout_info__size_1_v() (0x00000004U) +#define fifo_intr_ctxsw_timeout_info_ctxsw_state_v(r) (((r) >> 14U) & 0x3U) +#define fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v() (0x00000001U) +#define fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v() (0x00000002U) +#define fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v() (0x00000003U) +#define fifo_intr_ctxsw_timeout_info_prev_tsgid_v(r) (((r) >> 0U) & 0x3fffU) +#define fifo_intr_ctxsw_timeout_info_next_tsgid_v(r) (((r) >> 16U) & 0x3fffU) +#define fifo_intr_ctxsw_timeout_info_status_v(r) (((r) >> 30U) & 0x3U) +#define fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v() (0x00000000U) +#define fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v() (0x00000001U) +#define fifo_intr_ctxsw_timeout_info_status_ack_received_v() (0x00000002U) +#define fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v() (0x00000003U) +#define fifo_intr_pbdma_id_r() (0x000025a0U) +#define fifo_intr_pbdma_id_status_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_pbdma_id_status_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_pbdma_id_status__size_1_v() (0x00000003U) +#define fifo_intr_runlist_r() (0x00002a00U) +#define fifo_fb_timeout_r() (0x00002a04U) +#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U) +#define fifo_fb_timeout_period_max_f() (0x3fffffffU) +#define fifo_fb_timeout_period_init_f() (0x3c00U) +#define fifo_fb_timeout_detection_m() (U32(0x1U) << 31U) +#define fifo_fb_timeout_detection_enabled_f() (0x80000000U) +#define fifo_fb_timeout_detection_disabled_f() (0x0U) +#define fifo_sched_disable_r() (0x00002630U) +#define fifo_sched_disable_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_sched_disable_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_sched_disable_true_v() (0x00000001U) +#define fifo_runlist_preempt_r() (0x00002638U) +#define fifo_runlist_preempt_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_runlist_preempt_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_runlist_preempt_runlist_pending_v() (0x00000001U) +#define fifo_preempt_r() (0x00002634U) +#define fifo_preempt_pending_true_f() (0x100000U) +#define fifo_preempt_type_channel_f() (0x0U) +#define fifo_preempt_type_tsg_f() (0x1000000U) +#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) +#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) +#define fifo_engine_status_r(i)\ + (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_engine_status__size_1_v() (0x00000004U) +#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_engine_status_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_engine_status_ctx_status_valid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U) +#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U) +#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U) +#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_engine_status_next_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_eng_reload_v(r) (((r) >> 29U) & 0x1U) +#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U) +#define fifo_engine_status_faulted_true_v() (0x00000001U) +#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U) +#define fifo_engine_status_engine_idle_v() (0x00000000U) +#define fifo_engine_status_engine_busy_v() (0x00000001U) +#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U) +#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U) +#define fifo_eng_ctxsw_timeout_r() (0x00002a0cU) +#define fifo_eng_ctxsw_timeout_period_f(v) (((v)&0x7fffffffU) << 0U) +#define fifo_eng_ctxsw_timeout_period_m() (U32(0x7fffffffU) << 0U) +#define fifo_eng_ctxsw_timeout_period_v(r) (((r) >> 0U) & 0x7fffffffU) +#define fifo_eng_ctxsw_timeout_period_init_f() (0x3fffffU) +#define fifo_eng_ctxsw_timeout_period_max_f() (0x7fffffffU) +#define fifo_eng_ctxsw_timeout_detection_f(v) (((v)&0x1U) << 31U) +#define fifo_eng_ctxsw_timeout_detection_m() (U32(0x1U) << 31U) +#define fifo_eng_ctxsw_timeout_detection_enabled_f() (0x80000000U) +#define fifo_eng_ctxsw_timeout_detection_disabled_f() (0x0U) +#define fifo_pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pbdma_status__size_1_v() (0x00000003U) +#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_pbdma_status_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U) +#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U) +#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U) +#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U) +#define fifo_cfg0_r() (0x00002004U) +#define fifo_cfg0_num_pbdma_v(r) (((r) >> 0U) & 0xffU) +#define fifo_cfg0_pbdma_fault_id_v(r) (((r) >> 16U) & 0xffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h index 131d4dd80..a0a5108c4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,132 +59,36 @@ #include #include -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} +#define flush_l2_system_invalidate_r() (0x00070004U) +#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U) +#define flush_l2_system_invalidate_pending_busy_f() (0x1U) +#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U) +#define flush_l2_flush_dirty_r() (0x00070010U) +#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U) +#define flush_l2_flush_dirty_pending_empty_f() (0x0U) +#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U) +#define flush_l2_flush_dirty_pending_busy_f() (0x1U) +#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U) +#define flush_l2_flush_dirty_outstanding_false_f() (0x0U) +#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U) +#define flush_l2_clean_comptags_r() (0x0007000cU) +#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U) +#define flush_l2_clean_comptags_pending_empty_f() (0x0U) +#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U) +#define flush_l2_clean_comptags_pending_busy_f() (0x1U) +#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U) +#define flush_l2_clean_comptags_outstanding_false_f() (0x0U) +#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U) +#define flush_fb_flush_r() (0x00070000U) +#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_fb_flush_pending_busy_v() (0x00000001U) +#define flush_fb_flush_pending_busy_f() (0x1U) +#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_fb_flush_outstanding_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index 6641f35a3..9da569a44 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,100 +59,32 @@ #include #include -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1U; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0U; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} -static inline u32 fuse_opt_sec_debug_en_r(void) -{ - return 0x00021218U; -} -static inline u32 fuse_opt_priv_sec_en_r(void) -{ - return 0x00021434U; -} +#define fuse_status_opt_gpc_r() (0x00021c1cU) +#define fuse_status_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) +#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0xffU) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU) +#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) +#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) +#define fuse_status_opt_fbio_r() (0x00021c14U) +#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) +#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) +#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) +#define fuse_status_opt_rop_l2_fbp_r(i)\ + (nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_status_opt_fbp_r() (0x00021d38U) +#define fuse_status_opt_fbp_idx_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fuse_opt_ecc_en_r() (0x00021228U) +#define fuse_opt_feature_fuses_override_disable_r() (0x000213f0U) +#define fuse_opt_sec_debug_en_r() (0x00021218U) +#define fuse_opt_priv_sec_en_r() (0x00021434U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index cfebe6c45..6499039a8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,516 +59,132 @@ #include #include -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ffU; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_type_unbound_inst_block_v(void) -{ - return 0x00000004U; -} -static inline u32 gmmu_fault_type_pte_v(void) -{ - return 0x00000002U; -} -static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) -{ - return 0x00000005U; -} -static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) -{ - return 0x0000001fU; -} -static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) -{ - return 0x0000000fU; -} -static inline u32 gmmu_fault_buf_size_v(void) -{ - return 0x00000020U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) -{ - return (r >> 8U) & 0x3U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_b(void) -{ - return 12U; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) -{ - return 0U; -} -static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) -{ - return 1U; -} -static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) -{ - return 2U; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_b(void) -{ - return 12U; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) -{ - return 2U; -} -static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) -{ - return 3U; -} -static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) -{ - return 4U; -} -static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) -{ - return 5U; -} -static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 gmmu_fault_buf_entry_engine_id_w(void) -{ - return 6U; -} -static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gmmu_fault_buf_entry_fault_type_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) -{ - return 0x80U; -} -static inline u32 gmmu_fault_buf_entry_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 gmmu_fault_buf_entry_client_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 gmmu_fault_buf_entry_access_type_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) -{ - return 0x20000000U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) -{ - return 0x40000000U; -} -static inline u32 gmmu_fault_buf_entry_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gmmu_fault_buf_entry_valid_w(void) -{ - return 7U; -} -static inline u32 gmmu_fault_buf_entry_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_buf_entry_valid_true_f(void) -{ - return 0x80000000U; -} +#define gmmu_new_pde_is_pte_w() (0U) +#define gmmu_new_pde_is_pte_false_f() (0x0U) +#define gmmu_new_pde_aperture_w() (0U) +#define gmmu_new_pde_aperture_invalid_f() (0x0U) +#define gmmu_new_pde_aperture_video_memory_f() (0x2U) +#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pde_address_sys_w() (0U) +#define gmmu_new_pde_vol_w() (0U) +#define gmmu_new_pde_vol_true_f() (0x8U) +#define gmmu_new_pde_vol_false_f() (0x0U) +#define gmmu_new_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_pde__size_v() (0x00000008U) +#define gmmu_new_dual_pde_is_pte_w() (0U) +#define gmmu_new_dual_pde_is_pte_false_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_w() (0U) +#define gmmu_new_dual_pde_aperture_big_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_new_dual_pde_address_big_sys_w() (0U) +#define gmmu_new_dual_pde_aperture_small_w() (2U) +#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_small_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_vol_small_w() (2U) +#define gmmu_new_dual_pde_vol_small_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_small_false_f() (0x0U) +#define gmmu_new_dual_pde_vol_big_w() (0U) +#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) +#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_dual_pde_address_small_sys_w() (2U) +#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) +#define gmmu_new_dual_pde__size_v() (0x00000010U) +#define gmmu_new_pte__size_v() (0x00000008U) +#define gmmu_new_pte_valid_w() (0U) +#define gmmu_new_pte_valid_true_f() (0x1U) +#define gmmu_new_pte_valid_false_f() (0x0U) +#define gmmu_new_pte_privilege_w() (0U) +#define gmmu_new_pte_privilege_true_f() (0x20U) +#define gmmu_new_pte_privilege_false_f() (0x0U) +#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_sys_w() (0U) +#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_vid_w() (0U) +#define gmmu_new_pte_vol_w() (0U) +#define gmmu_new_pte_vol_true_f() (0x8U) +#define gmmu_new_pte_vol_false_f() (0x0U) +#define gmmu_new_pte_aperture_w() (0U) +#define gmmu_new_pte_aperture_video_memory_f() (0x0U) +#define gmmu_new_pte_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pte_read_only_w() (0U) +#define gmmu_new_pte_read_only_true_f() (0x40U) +#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U) +#define gmmu_new_pte_comptagline_w() (1U) +#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) +#define gmmu_new_pte_kind_w() (1U) +#define gmmu_new_pte_address_shift_v() (0x0000000cU) +#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) +#define gmmu_pte_kind_w() (1U) +#define gmmu_pte_kind_invalid_v() (0x000000ffU) +#define gmmu_pte_kind_pitch_v() (0x00000000U) +#define gmmu_fault_client_type_gpc_v() (0x00000000U) +#define gmmu_fault_client_type_hub_v() (0x00000001U) +#define gmmu_fault_type_unbound_inst_block_v() (0x00000004U) +#define gmmu_fault_type_pte_v() (0x00000002U) +#define gmmu_fault_mmu_eng_id_bar2_v() (0x00000005U) +#define gmmu_fault_mmu_eng_id_physical_v() (0x0000001fU) +#define gmmu_fault_mmu_eng_id_ce0_v() (0x0000000fU) +#define gmmu_fault_buf_size_v() (0x00000020U) +#define gmmu_fault_buf_entry_inst_aperture_v(r) (((r) >> 8U) & 0x3U) +#define gmmu_fault_buf_entry_inst_aperture_w() (0U) +#define gmmu_fault_buf_entry_inst_aperture_vid_mem_v() (0x00000000U) +#define gmmu_fault_buf_entry_inst_aperture_sys_coh_v() (0x00000002U) +#define gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v() (0x00000003U) +#define gmmu_fault_buf_entry_inst_lo_f(v) (((v)&0xfffffU) << 12U) +#define gmmu_fault_buf_entry_inst_lo_v(r) (((r) >> 12U) & 0xfffffU) +#define gmmu_fault_buf_entry_inst_lo_b() (12U) +#define gmmu_fault_buf_entry_inst_lo_w() (0U) +#define gmmu_fault_buf_entry_inst_hi_v(r) (((r) >> 0U) & 0xffffffffU) +#define gmmu_fault_buf_entry_inst_hi_w() (1U) +#define gmmu_fault_buf_entry_addr_phys_aperture_v(r) (((r) >> 0U) & 0x3U) +#define gmmu_fault_buf_entry_addr_phys_aperture_w() (2U) +#define gmmu_fault_buf_entry_addr_lo_f(v) (((v)&0xfffffU) << 12U) +#define gmmu_fault_buf_entry_addr_lo_v(r) (((r) >> 12U) & 0xfffffU) +#define gmmu_fault_buf_entry_addr_lo_b() (12U) +#define gmmu_fault_buf_entry_addr_lo_w() (2U) +#define gmmu_fault_buf_entry_addr_hi_v(r) (((r) >> 0U) & 0xffffffffU) +#define gmmu_fault_buf_entry_addr_hi_w() (3U) +#define gmmu_fault_buf_entry_timestamp_lo_v(r) (((r) >> 0U) & 0xffffffffU) +#define gmmu_fault_buf_entry_timestamp_lo_w() (4U) +#define gmmu_fault_buf_entry_timestamp_hi_v(r) (((r) >> 0U) & 0xffffffffU) +#define gmmu_fault_buf_entry_timestamp_hi_w() (5U) +#define gmmu_fault_buf_entry_engine_id_v(r) (((r) >> 0U) & 0x1ffU) +#define gmmu_fault_buf_entry_engine_id_w() (6U) +#define gmmu_fault_buf_entry_fault_type_v(r) (((r) >> 0U) & 0x1fU) +#define gmmu_fault_buf_entry_fault_type_w() (7U) +#define gmmu_fault_buf_entry_replayable_fault_v(r) (((r) >> 7U) & 0x1U) +#define gmmu_fault_buf_entry_replayable_fault_w() (7U) +#define gmmu_fault_buf_entry_replayable_fault_true_v() (0x00000001U) +#define gmmu_fault_buf_entry_replayable_fault_true_f() (0x80U) +#define gmmu_fault_buf_entry_client_v(r) (((r) >> 8U) & 0x7fU) +#define gmmu_fault_buf_entry_client_w() (7U) +#define gmmu_fault_buf_entry_access_type_v(r) (((r) >> 16U) & 0xfU) +#define gmmu_fault_buf_entry_access_type_w() (7U) +#define gmmu_fault_buf_entry_mmu_client_type_v(r) (((r) >> 20U) & 0x1U) +#define gmmu_fault_buf_entry_mmu_client_type_w() (7U) +#define gmmu_fault_buf_entry_gpc_id_v(r) (((r) >> 24U) & 0x1fU) +#define gmmu_fault_buf_entry_gpc_id_w() (7U) +#define gmmu_fault_buf_entry_protected_mode_v(r) (((r) >> 29U) & 0x1U) +#define gmmu_fault_buf_entry_protected_mode_w() (7U) +#define gmmu_fault_buf_entry_protected_mode_true_v() (0x00000001U) +#define gmmu_fault_buf_entry_protected_mode_true_f() (0x20000000U) +#define gmmu_fault_buf_entry_replayable_fault_en_v(r) (((r) >> 30U) & 0x1U) +#define gmmu_fault_buf_entry_replayable_fault_en_w() (7U) +#define gmmu_fault_buf_entry_replayable_fault_en_true_v() (0x00000001U) +#define gmmu_fault_buf_entry_replayable_fault_en_true_f() (0x40000000U) +#define gmmu_fault_buf_entry_valid_m() (U32(0x1U) << 31U) +#define gmmu_fault_buf_entry_valid_v(r) (((r) >> 31U) & 0x1U) +#define gmmu_fault_buf_entry_valid_w() (7U) +#define gmmu_fault_buf_entry_valid_true_v() (0x00000001U) +#define gmmu_fault_buf_entry_valid_true_f() (0x80000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 7537bd681..76a3e6e2c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,5728 +59,1696 @@ #include #include -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120U; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_en_fe_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception_en_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_en_gpc_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 gr_exception_en_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_en_memfmt_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_exception_en_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_en_ds_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_exception_en_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_en_pd_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_exception_en_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_en_scc_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_exception_en_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_en_ssync_enabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_exception_en_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception_en_mme_enabled_f(void) -{ - return 0x80U; -} -static inline u32 gr_exception_en_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_en_sked_enabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x0050433cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419b3cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_fe_chip_def_info_r(void) -{ - return 0x00404030U; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x00504358U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) -{ - return U32(0x1U) << 14U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 26U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) -{ - return 0x0050435cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) -{ - return 0x00504360U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) -{ - return 0x0050436cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) -{ - return 0x00504370U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) -{ - return 0x00504374U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) -{ - return 0x0050464cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) -{ - return 0x00504650U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) -{ - return 0x00504654U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) -{ - return 0x00504624U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) -{ - return 0x00504628U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) -{ - return 0x0050462cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) -{ - return 0x0050463cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) -{ - return 0x00504640U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r(void) -{ - return 0x00419b54U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f(void) -{ - return 0x4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f(void) -{ - return 0x8U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f(void) -{ - return 0x40U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f(void) -{ - return 0x80U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r(void) -{ - return 0x00504354U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r(void) -{ - return 0x00419b68U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r(void) -{ - return 0x00504368U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r(void) -{ - return 0x00419e20U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_task_f(void) -{ - return 0x10U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_task_f(void) -{ - return 0x20U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(void) -{ - return 0x00504620U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_corrected_err_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(void) -{ - return 0x00419e34U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f(void) -{ - return 0x4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f(void) -{ - return 0x8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r(void) -{ - return 0x00504634U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_r(void) -{ - return 0x00419e48U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f(void) -{ - return 0x2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f(void) -{ - return 0x4U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f(void) -{ - return 0x8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_r(void) -{ - return 0x00504648U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) -{ - return 0x00504430U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) -{ - return 0x00504434U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_address_veid_f(u32 v) -{ - return (v & 0x3fU) << 20U; -} -static inline u32 gr_pipe_bundle_address_veid_w(void) -{ - return 0U; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x0050472cU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) -{ - return 0x00419eb4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_tpc_pesmask_r(void) -{ - return 0x0040a260U; -} -static inline u32 gr_fe_tpc_pesmask_pesid_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 gr_fe_tpc_pesmask_gpcid_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_fe_tpc_pesmask_action_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_fe_tpc_pesmask_action_write_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_tpc_pesmask_action_read_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_tpc_pesmask_req_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fe_tpc_pesmask_req_send_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_tpc_pesmask_mask_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_irqsset_r(void) -{ - return 0x00409000U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_irqsset_r(void) -{ - return 0x0041a000U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_active_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_watchdog_active_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr0_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_clear_fault_during_ctxsw_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr0_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_host_int_enable_flush_when_busy_enable_f(void) -{ - return 0x100000U; -} -static inline u32 gr_fecs_host_int_enable_ecc_corrected_enable_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_host_int_enable_ecc_uncorrected_enable_f(void) -{ - return 0x400000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v(void) -{ - return 0x00000021U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return U32(0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_override_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_override_v(u32 r) -{ - return (r >> 11U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_cbu_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_cbu_override_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_r(void) -{ - return 0x0040965cU; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000380U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000302U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804U; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808U; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580cU; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810U; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814U; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7fU) << 0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028U; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818U; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32U; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581cU; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820U; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_scc_debug_r(void) -{ - return 0x00408000U; -} -static inline u32 gr_scc_debug_pagepool_invalidates_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 gr_scc_debug_pagepool_invalidates_disable_f(void) -{ - return 0x200U; -} -static inline u32 gr_scc_debug_pagepool_invalidates_enable_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return U32(0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ssync_hww_esr_r(void) -{ - return 0x00405a14U; -} -static inline u32 gr_ssync_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ssync_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x00504330U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00001100U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419e00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419e04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return U32(0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return U32(0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000170U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_r(void) -{ - return 0x0041bec4U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_enable_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_ppcs_cbm_debug_invalidate_beta_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00418100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0041814cU; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) -{ - return 0x00418198U; -} -static inline u32 gr_gpcs_swdx_spill_unit_r(void) -{ - return 0x00418e9cU; -} -static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) -{ - return 0x00504728U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void) -{ - return 0x4000000U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) -{ - return U32(0x1U) << 14U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) -{ - return 0x8000U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_control_r(void) -{ - return 0x00501044U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_control_inject_corrected_err_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) -{ - return 0x00501048U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) -{ - return 0x0050104cU; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) -{ - return 0x00501054U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00504710U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504714U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) -{ - return 0x00504718U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x0050471cU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00419e90U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00419e94U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) -{ - return 0x00419e80U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void) -{ - return 0x5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void) -{ - return 0x6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void) -{ - return 0x9U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void) -{ - return 0xbU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void) -{ - return 0xdU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void) -{ - return 0xeU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) -{ - return 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void) -{ - return 0x12U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void) -{ - return 0x16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void) -{ - return 0x17U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void) -{ - return 0x19U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) -{ - return U32(0xfU) << 24U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x005043a0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419ba0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x005043b0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419bb0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) -{ - return 0x00000005U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) -{ - return 0x00419a00U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) -{ - return U32(0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) -{ - return 0x00419bf0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00584200U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00584204U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x00584208U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00584210U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00584214U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00584218U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0058421cU; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x0058420cU; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00584220U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00584224U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00584228U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0058422cU; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00584230U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00584234U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00584238U; -} -static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0058423cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) -{ - return 0x00584600U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) -{ - return 0x00584604U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) -{ - return 0x00584624U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) -{ - return 0x00584628U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) -{ - return 0x0058462cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) -{ - return 0x00584630U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) -{ - return 0x00584634U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) -{ - return 0x00584638U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) -{ - return 0x0058463cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) -{ - return 0x00584640U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) -{ - return 0x00584644U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) -{ - return 0x00584648U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) -{ - return 0x0058464cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) -{ - return 0x00584650U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) -{ - return 0x00584654U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) -{ - return 0x00584658U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) -{ - return 0x0058465cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) -{ - return 0x00584660U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) -{ - return 0x00584614U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) -{ - return 0x00584618U; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) -{ - return 0x0058461cU; -} -static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) -{ - return 0x00584620U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return U32(0x3U) << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return U32(0x3U) << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) -{ - return 0x00419e84U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_init_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419bd8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return U32(0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419ba4U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return U32(0x3U) << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return U32(0x1ffU) << 0U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) -{ - return 0x00500324U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_control_r(void) -{ - return 0x00500310U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) -{ - return 0x00500314U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 19U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) -{ - return 0x00500320U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) -{ - return 0x00500318U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) -{ - return 0x0050031cU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_hww_esr_r(void) -{ - return 0x00502c98U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpccs_falcon_ecc_control_r(void) -{ - return 0x0050268cU; -} -static inline u32 gr_gpccs_falcon_ecc_control_inject_corrected_err_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_falcon_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) -{ - return 0x00502678U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) -{ - return 0x00502684U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) -{ - return (v & 0x7fffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) -{ - return 20U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) -{ - return U32(0xfffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) -{ - return 0x0050267cU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) -{ - return 0x00502680U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_control_r(void) -{ - return 0x0040968cU; -} -static inline u32 gr_fecs_falcon_ecc_control_inject_corrected_err_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_falcon_ecc_status_r(void) -{ - return 0x00409678U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x800U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_falcon_ecc_address_r(void) -{ - return 0x00409684U; -} -static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) -{ - return (v & 0x7fffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) -{ - return 20U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) -{ - return U32(0xfffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) -{ - return 0x0040967cU; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) -{ - return 0x00409680U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 gr_debug_0_r(void) -{ - return 0x00400080U; -} -static inline u32 gr_debug_0_scg_force_slow_drain_tpc_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_debug_0_scg_force_slow_drain_tpc_enabled_f(void) -{ - return 0x800U; -} -static inline u32 gr_debug_0_scg_force_slow_drain_tpc_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_debug_2_r(void) -{ - return 0x00400088U; -} -static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_usec_f(void) -{ - return 0x0U; -} -static inline u32 gr_debug_2_gfxp_wfi_timeout_unit_sysclk_f(void) -{ - return 0x8000000U; -} +#define gr_intr_r() (0x00400100U) +#define gr_intr_notify_pending_f() (0x1U) +#define gr_intr_notify_reset_f() (0x1U) +#define gr_intr_semaphore_pending_f() (0x2U) +#define gr_intr_semaphore_reset_f() (0x2U) +#define gr_intr_illegal_method_pending_f() (0x10U) +#define gr_intr_illegal_method_reset_f() (0x10U) +#define gr_intr_illegal_notify_pending_f() (0x40U) +#define gr_intr_illegal_notify_reset_f() (0x40U) +#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) +#define gr_intr_firmware_method_pending_f() (0x100U) +#define gr_intr_firmware_method_reset_f() (0x100U) +#define gr_intr_illegal_class_pending_f() (0x20U) +#define gr_intr_illegal_class_reset_f() (0x20U) +#define gr_intr_fecs_error_pending_f() (0x80000U) +#define gr_intr_fecs_error_reset_f() (0x80000U) +#define gr_intr_class_error_pending_f() (0x100000U) +#define gr_intr_class_error_reset_f() (0x100000U) +#define gr_intr_exception_pending_f() (0x200000U) +#define gr_intr_exception_reset_f() (0x200000U) +#define gr_fecs_intr_r() (0x00400144U) +#define gr_class_error_r() (0x00400110U) +#define gr_class_error_code_v(r) (((r) >> 0U) & 0xffffU) +#define gr_intr_nonstall_r() (0x00400120U) +#define gr_intr_nonstall_trap_pending_f() (0x2U) +#define gr_intr_en_r() (0x0040013cU) +#define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception1_r() (0x00400118U) +#define gr_exception1_gpc_0_pending_f() (0x1U) +#define gr_exception2_r() (0x0040011cU) +#define gr_exception_en_r() (0x00400138U) +#define gr_exception_en_fe_m() (U32(0x1U) << 0U) +#define gr_exception_en_fe_enabled_f() (0x1U) +#define gr_exception_en_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_en_gpc_enabled_f() (0x1000000U) +#define gr_exception_en_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_en_memfmt_enabled_f() (0x2U) +#define gr_exception_en_ds_m() (U32(0x1U) << 4U) +#define gr_exception_en_ds_enabled_f() (0x10U) +#define gr_exception_en_pd_m() (U32(0x1U) << 2U) +#define gr_exception_en_pd_enabled_f() (0x4U) +#define gr_exception_en_scc_m() (U32(0x1U) << 3U) +#define gr_exception_en_scc_enabled_f() (0x8U) +#define gr_exception_en_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_en_ssync_enabled_f() (0x20U) +#define gr_exception_en_mme_m() (U32(0x1U) << 7U) +#define gr_exception_en_mme_enabled_f() (0x80U) +#define gr_exception_en_sked_m() (U32(0x1U) << 8U) +#define gr_exception_en_sked_enabled_f() (0x100U) +#define gr_exception1_en_r() (0x00400130U) +#define gr_exception2_en_r() (0x00400134U) +#define gr_gpfifo_ctl_r() (0x00400500U) +#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) +#define gr_gpfifo_ctl_access_disabled_f() (0x0U) +#define gr_gpfifo_ctl_access_enabled_f() (0x1U) +#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) +#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) +#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) +#define gr_gpfifo_status_r() (0x00400504U) +#define gr_trapped_addr_r() (0x00400704U) +#define gr_trapped_addr_mthd_v(r) (((r) >> 2U) & 0xfffU) +#define gr_trapped_addr_subch_v(r) (((r) >> 16U) & 0x7U) +#define gr_trapped_addr_mme_generated_v(r) (((r) >> 20U) & 0x1U) +#define gr_trapped_addr_datahigh_v(r) (((r) >> 24U) & 0x1U) +#define gr_trapped_addr_priv_v(r) (((r) >> 28U) & 0x1U) +#define gr_trapped_addr_status_v(r) (((r) >> 31U) & 0x1U) +#define gr_trapped_data_lo_r() (0x00400708U) +#define gr_trapped_data_hi_r() (0x0040070cU) +#define gr_trapped_data_mme_r() (0x00400710U) +#define gr_trapped_data_mme_pc_v(r) (((r) >> 0U) & 0xfffU) +#define gr_status_r() (0x00400700U) +#define gr_status_fe_method_upper_v(r) (((r) >> 1U) & 0x1U) +#define gr_status_fe_method_lower_v(r) (((r) >> 2U) & 0x1U) +#define gr_status_fe_method_lower_idle_v() (0x00000000U) +#define gr_status_fe_gi_v(r) (((r) >> 21U) & 0x1U) +#define gr_status_mask_r() (0x00400610U) +#define gr_status_1_r() (0x00400604U) +#define gr_status_2_r() (0x00400608U) +#define gr_engine_status_r() (0x0040060cU) +#define gr_engine_status_value_busy_f() (0x1U) +#define gr_pri_be0_becs_be_exception_r() (0x00410204U) +#define gr_pri_be0_becs_be_exception_en_r() (0x00410208U) +#define gr_pri_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_pri_gpc0_gpccs_gpc_exception_en_r() (0x00502c94U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_activity_0_r() (0x00400380U) +#define gr_activity_1_r() (0x00400384U) +#define gr_activity_2_r() (0x00400388U) +#define gr_activity_4_r() (0x00400390U) +#define gr_activity_4_gpc0_s() (3U) +#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) +#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) +#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) +#define gr_activity_4_gpc0_empty_v() (0x00000000U) +#define gr_activity_4_gpc0_preempted_v() (0x00000004U) +#define gr_pri_gpc0_gcc_dbg_r() (0x00501000U) +#define gr_pri_gpcs_gcc_dbg_r() (0x00419000U) +#define gr_pri_gpcs_gcc_dbg_invalidate_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cache_control_r() (0x0050433cU) +#define gr_pri_gpcs_tpcs_sm_cache_control_r() (0x00419b3cU) +#define gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m() (U32(0x1U) << 0U) +#define gr_pri_sked_activity_r() (0x00407054U) +#define gr_pri_gpc0_gpccs_gpc_activity0_r() (0x00502c80U) +#define gr_pri_gpc0_gpccs_gpc_activity1_r() (0x00502c84U) +#define gr_pri_gpc0_gpccs_gpc_activity2_r() (0x00502c88U) +#define gr_pri_gpc0_gpccs_gpc_activity3_r() (0x00502c8cU) +#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() (0x00504500U) +#define gr_pri_gpcs_gpccs_gpc_activity_0_r() (0x0041ac80U) +#define gr_pri_gpcs_gpccs_gpc_activity_1_r() (0x0041ac84U) +#define gr_pri_gpcs_gpccs_gpc_activity_2_r() (0x0041ac88U) +#define gr_pri_gpcs_gpccs_gpc_activity_3_r() (0x0041ac8cU) +#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r() (0x00419d00U) +#define gr_pri_be0_becs_be_activity0_r() (0x00410200U) +#define gr_pri_bes_becs_be_activity0_r() (0x00408a00U) +#define gr_pri_ds_mpipe_status_r() (0x00405858U) +#define gr_pri_fe_go_idle_info_r() (0x00404194U) +#define gr_pri_fe_chip_def_info_r() (0x00404030U) +#define gr_pri_fe_chip_def_info_max_veid_count_v(r) (((r) >> 0U) & 0xfffU) +#define gr_pri_fe_chip_def_info_max_veid_count_init_v() (0x00000040U) +#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r() (0x00504238U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() (0x00504358U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m()\ + (U32(0x1U) << 8U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m()\ + (U32(0x1U) << 9U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m()\ + (U32(0x1U) << 10U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m()\ + (U32(0x1U) << 11U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m()\ + (U32(0x1U) << 12U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m()\ + (U32(0x1U) << 13U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m()\ + (U32(0x1U) << 14U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m()\ + (U32(0x1U) << 15U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 24U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 26U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() (0x0050435cU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() (0x00504360U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r() (0x0050436cU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 8U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 10U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() (0x00504370U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() (0x00504374U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_r() (0x0050464cU) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 16U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 18U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() (0x00504650U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() (0x00504654U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r() (0x00504624U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 8U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 10U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() (0x00504628U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() (0x0050462cU) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r() (0x00504638U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 16U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 18U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() (0x0050463cU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() (0x00504640U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r() (0x00419b54U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_f(v) (((v)&0x1U) << 0U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f() (0x1U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_f(v) (((v)&0x1U) << 1U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f() (0x2U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_f(v) (((v)&0x1U) << 2U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f() (0x4U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_f(v) (((v)&0x1U) << 3U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f() (0x8U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_f(v) (((v)&0x1U) << 4U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f() (0x10U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_f(v) (((v)&0x1U) << 5U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f() (0x20U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_f(v) (((v)&0x1U) << 6U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f() (0x40U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_f(v) (((v)&0x1U) << 7U) +#define gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f() (0x80U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r() (0x00504354U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_f(v) (((v)&0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_f(v) (((v)&0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_f(v) (((v)&0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_f(v) (((v)&0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_f(v) (((v)&0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_f(v) (((v)&0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_f(v) (((v)&0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_f(v) (((v)&0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 9U) +#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r() (0x00419b68U) +#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f() (0x1U) +#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f() (0x2U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r() (0x00504368U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 3U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r() (0x00419e20U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f() (0x1U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f() (0x2U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_f(v)\ + (((v)&0x1U) << 4U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_task_f() (0x10U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_f(v)\ + (((v)&0x1U) << 5U) +#define gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_task_f() (0x20U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r() (0x00504620U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_corrected_err_f(v)\ + (((v)&0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_f(v)\ + (((v)&0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_f(v)\ + (((v)&0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_init_f() (0x0U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r() (0x00419e34U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f() (0x1U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f() (0x2U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_f(v)\ + (((v)&0x1U) << 2U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f() (0x4U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_f(v)\ + (((v)&0x1U) << 3U) +#define gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f() (0x8U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r() (0x00504634U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_f(v)\ + (((v)&0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_f(v)\ + (((v)&0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 5U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_r() (0x00419e48U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f() (0x1U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f()\ + (0x2U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_f(v)\ + (((v)&0x1U) << 2U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f() (0x4U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_f(v)\ + (((v)&0x1U) << 3U) +#define gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f()\ + (0x8U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_r() (0x00504648U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f()\ + (0x0U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_f(v)\ + (((v)&0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f() (0x0U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_f(v)\ + (((v)&0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f()\ + (0x0U) +#define gr_pri_gpc0_tpc0_sm_icache_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 5U) +#define gr_pri_gpc0_tpc0_tex_m_routing_r() (0x005042c4U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f() (0x0U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f() (0x1U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f() (0x2U) +#define gr_gpc0_tpc0_mpc_hww_esr_r() (0x00504430U) +#define gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f() (0x40000000U) +#define gr_gpc0_tpc0_mpc_hww_esr_info_r() (0x00504434U) +#define gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(r) (((r) >> 0U) & 0x3fU) +#define gr_pri_be0_crop_status1_r() (0x00410134U) +#define gr_pri_bes_crop_status1_r() (0x00408934U) +#define gr_pri_be0_zrop_status_r() (0x00410048U) +#define gr_pri_be0_zrop_status2_r() (0x0041004cU) +#define gr_pri_bes_zrop_status_r() (0x00408848U) +#define gr_pri_bes_zrop_status2_r() (0x0040884cU) +#define gr_pipe_bundle_address_r() (0x00400200U) +#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pipe_bundle_address_veid_f(v) (((v)&0x3fU) << 20U) +#define gr_pipe_bundle_address_veid_w() (0U) +#define gr_pipe_bundle_data_r() (0x00400204U) +#define gr_pipe_bundle_config_r() (0x00400208U) +#define gr_pipe_bundle_config_override_pipe_mode_disabled_f() (0x0U) +#define gr_pipe_bundle_config_override_pipe_mode_enabled_f() (0x80000000U) +#define gr_fe_hww_esr_r() (0x00404000U) +#define gr_fe_hww_esr_reset_active_f() (0x40000000U) +#define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) +#define gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() (0x00419eacU) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() (0x0050472cU) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()\ + (0x4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f()\ + (0x40U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f()\ + (0x100U) +#define gr_gpcs_tpcs_sms_hww_global_esr_r() (0x00419eb4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_r() (0x00504734U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m() (U32(0x1U) << 5U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m()\ + (U32(0x1U) << 6U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m()\ + (U32(0x1U) << 2U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m() (U32(0x1U) << 8U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f() (0x100U) +#define gr_fe_go_idle_timeout_r() (0x00404154U) +#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) +#define gr_fe_go_idle_timeout_count_prod_f() (0x1800U) +#define gr_fe_object_table_r(i)\ + (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) +#define gr_fe_tpc_fs_r(i)\ + (nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_tpc_pesmask_r() (0x0040a260U) +#define gr_fe_tpc_pesmask_pesid_f(v) (((v)&0x3fU) << 24U) +#define gr_fe_tpc_pesmask_gpcid_f(v) (((v)&0xffU) << 16U) +#define gr_fe_tpc_pesmask_action_m() (U32(0x1U) << 30U) +#define gr_fe_tpc_pesmask_action_write_f() (0x40000000U) +#define gr_fe_tpc_pesmask_action_read_f() (0x0U) +#define gr_fe_tpc_pesmask_req_m() (U32(0x1U) << 31U) +#define gr_fe_tpc_pesmask_req_send_f() (0x80000000U) +#define gr_fe_tpc_pesmask_mask_m() (U32(0xffffU) << 0U) +#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) +#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_mme_hww_esr_r() (0x00404490U) +#define gr_mme_hww_esr_reset_active_f() (0x40000000U) +#define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) +#define gr_memfmt_hww_esr_r() (0x00404600U) +#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) +#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) +#define gr_fecs_cpuctl_r() (0x00409100U) +#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_cpuctl_alias_r() (0x00409130U) +#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_dmactl_r() (0x0040910cU) +#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_fecs_os_r() (0x00409080U) +#define gr_fecs_idlestate_r() (0x0040904cU) +#define gr_fecs_mailbox0_r() (0x00409040U) +#define gr_fecs_mailbox1_r() (0x00409044U) +#define gr_fecs_irqstat_r() (0x00409008U) +#define gr_fecs_irqmode_r() (0x0040900cU) +#define gr_fecs_irqmask_r() (0x00409018U) +#define gr_fecs_irqdest_r() (0x0040901cU) +#define gr_fecs_curctx_r() (0x00409050U) +#define gr_fecs_nxtctx_r() (0x00409054U) +#define gr_fecs_engctl_r() (0x004090a4U) +#define gr_fecs_debug1_r() (0x00409090U) +#define gr_fecs_debuginfo_r() (0x00409094U) +#define gr_fecs_icd_cmd_r() (0x00409200U) +#define gr_fecs_icd_cmd_opc_s() (4U) +#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) +#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) +#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define gr_fecs_icd_rdata_r() (0x0040920cU) +#define gr_fecs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmemc_offs_s() (6U) +#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) +#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmatrfbase_r() (0x00409110U) +#define gr_fecs_dmatrfmoffs_r() (0x00409114U) +#define gr_fecs_dmatrffboffs_r() (0x0040911cU) +#define gr_fecs_dmatrfcmd_r() (0x00409118U) +#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define gr_fecs_bootvec_r() (0x00409104U) +#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_irqsset_r() (0x00409000U) +#define gr_fecs_falcon_hwcfg_r() (0x00409108U) +#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) +#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) +#define gr_fecs_falcon_rm_r() (0x00409084U) +#define gr_fecs_current_ctx_r() (0x00409b00U) +#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_current_ctx_target_s() (2U) +#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_current_ctx_valid_s() (1U) +#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_current_ctx_valid_false_f() (0x0U) +#define gr_fecs_method_data_r() (0x00409500U) +#define gr_fecs_method_push_r() (0x00409504U) +#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) +#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) +#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) +#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) +#define gr_fecs_method_push_adr_wfi_golden_save_v() (0x00000009U) +#define gr_fecs_method_push_adr_restore_golden_v() (0x00000015U) +#define gr_fecs_method_push_adr_discover_zcull_image_size_v() (0x00000016U) +#define gr_fecs_method_push_adr_discover_pm_image_size_v() (0x00000025U) +#define gr_fecs_method_push_adr_discover_reglist_image_size_v() (0x00000030U) +#define gr_fecs_method_push_adr_set_reglist_bind_instance_v() (0x00000031U) +#define gr_fecs_method_push_adr_set_reglist_virtual_address_v() (0x00000032U) +#define gr_fecs_method_push_adr_stop_ctxsw_v() (0x00000038U) +#define gr_fecs_method_push_adr_start_ctxsw_v() (0x00000039U) +#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) +#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU) +#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) +#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\ + (0x0000003aU) +#define gr_fecs_host_int_status_r() (0x00409c18U) +#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) +#define gr_fecs_host_int_status_fault_during_ctxsw_active_v() (0x00000001U) +#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) +#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) +#define gr_fecs_host_int_status_watchdog_active_f() (0x80000U) +#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_host_int_status_ecc_corrected_f(v) (((v)&0x1U) << 21U) +#define gr_fecs_host_int_status_ecc_corrected_m() (U32(0x1U) << 21U) +#define gr_fecs_host_int_status_ecc_uncorrected_f(v) (((v)&0x1U) << 22U) +#define gr_fecs_host_int_status_ecc_uncorrected_m() (U32(0x1U) << 22U) +#define gr_fecs_host_int_clear_r() (0x00409c20U) +#define gr_fecs_host_int_clear_ctxsw_intr0_clear_v() (0x00000001U) +#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) +#define gr_fecs_host_int_clear_fault_during_ctxsw_clear_v() (0x00000001U) +#define gr_fecs_host_int_enable_r() (0x00409c24U) +#define gr_fecs_host_int_enable_ctxsw_intr0_enable_f() (0x1U) +#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) +#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) +#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f() (0x20000U) +#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f() (0x40000U) +#define gr_fecs_host_int_enable_watchdog_enable_f() (0x80000U) +#define gr_fecs_host_int_enable_flush_when_busy_enable_f() (0x100000U) +#define gr_fecs_host_int_enable_ecc_corrected_enable_f() (0x200000U) +#define gr_fecs_host_int_enable_ecc_uncorrected_enable_f() (0x400000U) +#define gr_fecs_ctxsw_reset_ctl_r() (0x00409614U) +#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() (0x10U) +#define gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() (0x20U) +#define gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() (0x40U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() (0x100U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f() (0x400U) +#define gr_fecs_ctx_state_store_major_rev_id_r() (0x0040960cU) +#define gr_fecs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) +#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) +#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) +#define gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v() (0x00000021U) +#define gr_fecs_ctxsw_mailbox_set_r(i)\ + (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_clear_r(i)\ + (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_fs_r() (0x00409604U) +#define gr_fecs_fs_num_available_gpcs_s() (5U) +#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_fs_num_available_fbps_s() (5U) +#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) +#define gr_fecs_cfg_r() (0x00409620U) +#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_fecs_rc_lanes_r() (0x00409880U) +#define gr_fecs_rc_lanes_num_chains_s() (6U) +#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_fecs_ctxsw_status_1_r() (0x00409400U) +#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) +#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) +#define gr_fecs_new_ctx_r() (0x00409b04U) +#define gr_fecs_new_ctx_ptr_s() (28U) +#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_new_ctx_target_s() (2U) +#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_valid_s() (1U) +#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) +#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) +#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_arb_ctx_ptr_target_s() (2U) +#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) +#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) +#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) +#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r() (0x00502c04U) +#define gr_gpc0_gpccs_ctxsw_status_1_r() (0x00502400U) +#define gr_fecs_ctxsw_idlestate_r() (0x00409420U) +#define gr_fecs_feature_override_ecc_r() (0x00409658U) +#define gr_fecs_feature_override_ecc_sm_lrf_v(r) (((r) >> 0U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_lrf_override_v(r) (((r) >> 3U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_l1_data_v(r) (((r) >> 4U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_l1_data_override_v(r)\ + (((r) >> 7U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_l1_tag_v(r) (((r) >> 8U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_l1_tag_override_v(r)\ + (((r) >> 11U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_override_v(r) (((r) >> 15U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_cbu_v(r) (((r) >> 20U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_cbu_override_v(r) (((r) >> 23U) & 0x1U) +#define gr_fecs_feature_override_ecc_1_r() (0x0040965cU) +#define gr_fecs_feature_override_ecc_1_sm_l0_icache_v(r) (((r) >> 0U) & 0x1U) +#define gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(r)\ + (((r) >> 1U) & 0x1U) +#define gr_fecs_feature_override_ecc_1_sm_l1_icache_v(r) (((r) >> 2U) & 0x1U) +#define gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(r)\ + (((r) >> 3U) & 0x1U) +#define gr_gpc0_gpccs_ctxsw_idlestate_r() (0x00502420U) +#define gr_rstr2d_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) +#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_pd_hww_esr_r() (0x00406018U) +#define gr_pd_hww_esr_reset_active_f() (0x40000000U) +#define gr_pd_hww_esr_en_enable_f() (0x80000000U) +#define gr_pd_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) +#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) +#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) +#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) +#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) +#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) +#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) +#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) +#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) +#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) +#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) +#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) +#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) +#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) +#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) +#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) +#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000380U) +#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) +#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) +#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000302U) +#define gr_pd_dist_skip_table_r(i)\ + (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) +#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_ds_debug_r() (0x00405800U) +#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) +#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) +#define gr_ds_zbc_color_r_r() (0x00405804U) +#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_g_r() (0x00405808U) +#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_b_r() (0x0040580cU) +#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_a_r() (0x00405810U) +#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_color_fmt_r() (0x00405814U) +#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) +#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) +#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) +#define gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v() (0x00000004U) +#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) +#define gr_ds_zbc_z_r() (0x00405818U) +#define gr_ds_zbc_z_val_s() (32U) +#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) +#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_ds_zbc_z_val__init_v() (0x00000000U) +#define gr_ds_zbc_z_val__init_f() (0x0U) +#define gr_ds_zbc_z_fmt_r() (0x0040581cU) +#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) +#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) +#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) +#define gr_ds_zbc_tbl_index_r() (0x00405820U) +#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) +#define gr_ds_zbc_tbl_ld_r() (0x00405824U) +#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) +#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) +#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) +#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) +#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) +#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) +#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) +#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) +#define gr_ds_hww_esr_r() (0x00405840U) +#define gr_ds_hww_esr_reset_s() (1U) +#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) +#define gr_ds_hww_esr_2_r() (0x00405848U) +#define gr_ds_hww_esr_2_reset_s() (1U) +#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_2_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_2_en_enabled_f() (0x80000000U) +#define gr_ds_hww_report_mask_r() (0x00405844U) +#define gr_ds_hww_report_mask_sph0_err_report_f() (0x1U) +#define gr_ds_hww_report_mask_sph1_err_report_f() (0x2U) +#define gr_ds_hww_report_mask_sph2_err_report_f() (0x4U) +#define gr_ds_hww_report_mask_sph3_err_report_f() (0x8U) +#define gr_ds_hww_report_mask_sph4_err_report_f() (0x10U) +#define gr_ds_hww_report_mask_sph5_err_report_f() (0x20U) +#define gr_ds_hww_report_mask_sph6_err_report_f() (0x40U) +#define gr_ds_hww_report_mask_sph7_err_report_f() (0x80U) +#define gr_ds_hww_report_mask_sph8_err_report_f() (0x100U) +#define gr_ds_hww_report_mask_sph9_err_report_f() (0x200U) +#define gr_ds_hww_report_mask_sph10_err_report_f() (0x400U) +#define gr_ds_hww_report_mask_sph11_err_report_f() (0x800U) +#define gr_ds_hww_report_mask_sph12_err_report_f() (0x1000U) +#define gr_ds_hww_report_mask_sph13_err_report_f() (0x2000U) +#define gr_ds_hww_report_mask_sph14_err_report_f() (0x4000U) +#define gr_ds_hww_report_mask_sph15_err_report_f() (0x8000U) +#define gr_ds_hww_report_mask_sph16_err_report_f() (0x10000U) +#define gr_ds_hww_report_mask_sph17_err_report_f() (0x20000U) +#define gr_ds_hww_report_mask_sph18_err_report_f() (0x40000U) +#define gr_ds_hww_report_mask_sph19_err_report_f() (0x80000U) +#define gr_ds_hww_report_mask_sph20_err_report_f() (0x100000U) +#define gr_ds_hww_report_mask_sph21_err_report_f() (0x200000U) +#define gr_ds_hww_report_mask_sph22_err_report_f() (0x400000U) +#define gr_ds_hww_report_mask_sph23_err_report_f() (0x800000U) +#define gr_ds_hww_report_mask_2_r() (0x0040584cU) +#define gr_ds_hww_report_mask_2_sph24_err_report_f() (0x1U) +#define gr_ds_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_scc_debug_r() (0x00408000U) +#define gr_scc_debug_pagepool_invalidates_m() (U32(0x1U) << 9U) +#define gr_scc_debug_pagepool_invalidates_disable_f() (0x200U) +#define gr_scc_debug_pagepool_invalidates_enable_f() (0x0U) +#define gr_scc_bundle_cb_base_r() (0x00408004U) +#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_bundle_cb_size_r() (0x00408008U) +#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U) +#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) +#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_scc_pagepool_base_r() (0x0040800cU) +#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_pagepool_r() (0x00408010U) +#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) +#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) +#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) +#define gr_scc_pagepool_max_valid_pages_s() (10U) +#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) +#define gr_scc_pagepool_valid_true_f() (0x80000000U) +#define gr_scc_hww_esr_r() (0x00408030U) +#define gr_scc_hww_esr_reset_active_f() (0x40000000U) +#define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_ssync_hww_esr_r() (0x00405a14U) +#define gr_ssync_hww_esr_reset_active_f() (0x40000000U) +#define gr_ssync_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) +#define gr_sked_hww_esr_en_r() (0x00407024U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m()\ + (U32(0x1U) << 25U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() (0x0U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()\ + (0x2000000U) +#define gr_cwd_fs_r() (0x00405b00U) +#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) +#define gr_cwd_gpc_tpc_id_r(i)\ + (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) +#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) +#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) +#define gr_cwd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_sm_id__size_1_v() (0x00000010U) +#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) +#define gr_gpc0_fs_gpc_r() (0x00502608U) +#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) +#define gr_gpc0_cfg_r() (0x00502620U) +#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpccs_rc_lanes_r() (0x00502880U) +#define gr_gpccs_rc_lanes_num_chains_s() (6U) +#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_rc_lane_size_r() (0x00502910U) +#define gr_gpccs_rc_lane_size_v_s() (24U) +#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) +#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) +#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) +#define gr_gpc0_zcull_fs_r() (0x00500910U) +#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) +#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) +#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ + (((v)&0xfU) << 0U) +#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) +#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) +#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) +#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) +#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_zcull_zcsize_r(i)\ + (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) +#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) +#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) +#define gr_gpc0_gpm_pd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ + (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) +#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_r() (0x00504608U) +#define gr_gpc0_tpc0_sm_cfg_tpc_id_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_tpc_id_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_arch_r() (0x00504330U) +#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU) +#define gr_gpc0_tpc0_sm_arch_sm_version_v(r) (((r) >> 20U) & 0xfffU) +#define gr_gpc0_ppc0_pes_vsc_strem_r() (0x00503018U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000800U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00001100U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ + (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000800U) +#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U) +#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419e04U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) +#define gr_gpccs_falcon_addr_r() (0x0041a0acU) +#define gr_gpccs_falcon_addr_lsb_s() (6U) +#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_msb_s() (6U) +#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) +#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_ext_s() (12U) +#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) +#define gr_gpccs_cpuctl_r() (0x0041a100U) +#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_gpccs_dmactl_r() (0x0041a10cU) +#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_gpccs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt__size_1_v() (0x00000004U) +#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_gpccs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U) +#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x00000170U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ + (0x00000100U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) +#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_ppcs_cbm_debug_r() (0x0041bec4U) +#define gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m() (U32(0x1U) << 0U) +#define gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f() (0x0U) +#define gr_gpcs_ppcs_cbm_debug_invalidate_alpha_enable_f() (0x1U) +#define gr_gpcs_ppcs_cbm_debug_invalidate_beta_m() (U32(0x1U) << 1U) +#define gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f() (0x0U) +#define gr_gpcs_ppcs_cbm_debug_invalidate_beta_enable_f() (0x2U) +#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ + (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ + (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ + (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ + (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ + (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00418100U) +#define gr_gpcs_swdx_dss_zbc_z_r(i)\ + (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0041814cU) +#define gr_gpcs_swdx_dss_zbc_s_r(i)\ + (nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_s_val_f(v) (((v)&0xffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() (0x00418198U) +#define gr_gpcs_swdx_spill_unit_r() (0x00418e9cU) +#define gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m()\ + (U32(0x1U) << 16U) +#define gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_disabled_f() (0x0U) +#define gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_enabled_f()\ + (0x10000U) +#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) +#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) +#define gr_crstr_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_crstr_gpc_map_tile0_f(v) (((v)&0x1fU) << 0U) +#define gr_crstr_gpc_map_tile1_f(v) (((v)&0x1fU) << 5U) +#define gr_crstr_gpc_map_tile2_f(v) (((v)&0x1fU) << 10U) +#define gr_crstr_gpc_map_tile3_f(v) (((v)&0x1fU) << 15U) +#define gr_crstr_gpc_map_tile4_f(v) (((v)&0x1fU) << 20U) +#define gr_crstr_gpc_map_tile5_f(v) (((v)&0x1fU) << 25U) +#define gr_crstr_map_table_cfg_r() (0x00418bb8U) +#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_r(i)\ + (nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) +#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) +#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_gcc_pagepool_r() (0x00419008U) +#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) +#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() (0x00419ea8U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() (0x00504728U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f()\ + (0x4U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f()\ + (0x20U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f()\ + (0x100U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\ + (0x200U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f()\ + (0x800U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f() (0x2000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f() (0x4000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f()\ + (0x8000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f()\ + (0x10000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\ + (0x40000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f()\ + (0x800000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f()\ + (0x400000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f()\ + (0x4000000U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r() (0x00419d0cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f() (0x1U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U) +#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) +#define gr_gpcs_gpccs_gpc_exception_en_gcc_f(v) (((v)&0x1U) << 2U) +#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) +#define gr_gpcs_gpccs_gpc_exception_en_gpccs_f(v) (((v)&0x1U) << 14U) +#define gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(v) (((v)&0x1U) << 15U) +#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) +#define gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v() (0x00000001U) +#define gr_gpc0_gpccs_gpc_exception_gpccs_f(v) (((v)&0x1U) << 14U) +#define gr_gpc0_gpccs_gpc_exception_gpccs_m() (U32(0x1U) << 14U) +#define gr_gpc0_gpccs_gpc_exception_gpccs_pending_f() (0x4000U) +#define gr_gpc0_gpccs_gpc_exception_gpcmmu_f(v) (((v)&0x1U) << 15U) +#define gr_gpc0_gpccs_gpc_exception_gpcmmu_m() (U32(0x1U) << 15U) +#define gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f() (0x8000U) +#define gr_pri_gpc0_gcc_l15_ecc_control_r() (0x00501044U) +#define gr_pri_gpc0_gcc_l15_ecc_control_inject_corrected_err_f(v)\ + (((v)&0x1U) << 0U) +#define gr_pri_gpc0_gcc_l15_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 1U) +#define gr_pri_gpc0_gcc_l15_ecc_status_r() (0x00501048U) +#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m() (U32(0x1U) << 0U) +#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 8U) & 0x1U) +#define gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 10U) & 0x1U) +#define gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() (0x0050104cU) +#define gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() (0x00501054U) +#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_r() (0x00504704U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m() (U32(0x1U) << 0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f() (0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v() (0x00000000U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m() (U32(0x1U) << 3U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_gpc0_tpc0_sm0_warp_valid_mask_0_r() (0x00504708U) +#define gr_gpc0_tpc0_sm0_warp_valid_mask_1_r() (0x0050470cU) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r() (0x00504710U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r() (0x00504714U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r() (0x00504718U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r() (0x0050471cU) +#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r() (0x00419e90U) +#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r() (0x00419e94U) +#define gr_gpcs_tpcs_sms_dbgr_status0_r() (0x00419e80U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_r() (0x00504700U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(r) (((r) >> 4U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v() (0x00000001U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_r() (0x00504730U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v() (0x00000000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f() (0x0U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f() (0x1U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f() (0x2U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f() (0x4U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f() (0x5U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f() (0x6U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f() (0x8U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f() (0x9U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f() (0xbU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f() (0xdU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f() (0xeU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f() (0xfU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f() (0x12U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f() (0x16U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f() (0x17U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f() (0x18U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f() (0x19U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m() (U32(0xffU) << 16U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m() (U32(0xfU) << 24U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r() (0x0050460cU) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() (0x00504738U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() (0x0050473cU) +#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x005043a0U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419ba0U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) +#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x005043b0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419bb0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) +#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) +#define gr_ppcs_wwdx_map_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) +#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ + (((v)&0x1fU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ + (((v)&0x7U) << 21U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_r(i)\ + (nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v() (0x00000005U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(v) (((v)&0xffU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(v) (((v)&0xffU) << 24U) +#define gr_bes_zrop_settings_r() (0x00408850U) +#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_be0_crop_debug3_r() (0x00410108U) +#define gr_bes_crop_debug3_r() (0x00408908U) +#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) +#define gr_bes_crop_debug3_blendopt_read_suppress_m() (U32(0x1U) << 1U) +#define gr_bes_crop_debug3_blendopt_read_suppress_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_read_suppress_enabled_f() (0x2U) +#define gr_bes_crop_debug3_blendopt_fill_override_m() (U32(0x1U) << 2U) +#define gr_bes_crop_debug3_blendopt_fill_override_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_fill_override_enabled_f() (0x4U) +#define gr_bes_crop_debug4_r() (0x0040894cU) +#define gr_bes_crop_debug4_clamp_fp_blend_m() (U32(0x1U) << 18U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) +#define gr_bes_crop_settings_r() (0x00408958U) +#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) +#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) +#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) +#define gr_zcull_subregion_qty_v() (0x00000010U) +#define gr_gpcs_tpcs_tex_in_dbg_r() (0x00419a00U) +#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(v) (((v)&0x1U) << 19U) +#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m() (U32(0x1U) << 19U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_r() (0x00419bf0U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(v) (((v)&0x1U) << 5U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m() (U32(0x1U) << 5U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(v) (((v)&0x1U) << 10U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m() (U32(0x1U) << 10U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m() (U32(0x1U) << 28U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f() (0x10000000U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r() (0x00584200U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r() (0x00584204U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r() (0x00584208U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r() (0x00584210U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r() (0x00584214U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r() (0x00584218U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r() (0x0058421cU) +#define gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r() (0x0058420cU) +#define gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r() (0x00584220U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r() (0x00584224U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r() (0x00584228U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r() (0x0058422cU) +#define gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r() (0x00584230U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r() (0x00584234U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r() (0x00584238U) +#define gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r() (0x0058423cU) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r() (0x00584600U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r() (0x00584604U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r() (0x00584624U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r() (0x00584628U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r() (0x0058462cU) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r() (0x00584630U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r() (0x00584634U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r() (0x00584638U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r() (0x0058463cU) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r() (0x00584640U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r() (0x00584644U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r() (0x00584648U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r() (0x0058464cU) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r() (0x00584650U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r() (0x00584654U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r() (0x00584658U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r() (0x0058465cU) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r() (0x00584660U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter4_r() (0x00584614U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter5_r() (0x00584618U) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter6_r() (0x0058461cU) +#define gr_egpc0_etpc0_sm0_dsm_perf_counter7_r() (0x00584620U) +#define gr_fe_pwr_mode_r() (0x00404170U) +#define gr_fe_pwr_mode_mode_auto_f() (0x0U) +#define gr_fe_pwr_mode_mode_force_on_f() (0x2U) +#define gr_fe_pwr_mode_req_v(r) (((r) >> 4U) & 0x1U) +#define gr_fe_pwr_mode_req_send_f() (0x10U) +#define gr_fe_pwr_mode_req_done_v() (0x00000000U) +#define gr_gpcs_pri_mmu_ctrl_r() (0x00418880U) +#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() (U32(0x1U) << 0U) +#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() (U32(0x1U) << 11U) +#define gr_gpcs_pri_mmu_ctrl_vol_fault_m() (U32(0x1U) << 1U) +#define gr_gpcs_pri_mmu_ctrl_comp_fault_m() (U32(0x1U) << 2U) +#define gr_gpcs_pri_mmu_ctrl_miss_gran_m() (U32(0x3U) << 3U) +#define gr_gpcs_pri_mmu_ctrl_cache_mode_m() (U32(0x3U) << 5U) +#define gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() (U32(0x3U) << 28U) +#define gr_gpcs_pri_mmu_ctrl_mmu_vol_m() (U32(0x1U) << 30U) +#define gr_gpcs_pri_mmu_ctrl_mmu_disable_m() (U32(0x1U) << 31U) +#define gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m()\ + (U32(0x1U) << 27U) +#define gr_gpcs_pri_mmu_pm_unit_mask_r() (0x00418890U) +#define gr_gpcs_pri_mmu_pm_req_mask_r() (0x00418894U) +#define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define gr_gpcs_pri_mmu_debug_wr_r() (0x004188b4U) +#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) +#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) +#define gr_gpcs_tpcs_sms_dbgr_control0_r() (0x00419e84U) +#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) +#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) +#define gr_fe_gfxp_wfi_timeout_count_init_f() (0x800U) +#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419bd8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ + (((v)&0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_disp_ctrl_r() (0x00419ba4U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) +#define gr_gpcs_tc_debug0_r() (0x00418708U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U) +#define gr_gpc0_mmu_gpcmmu_global_esr_r() (0x00500324U) +#define gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(v) (((v)&0x1U) << 0U) +#define gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m() (U32(0x1U) << 0U) +#define gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(v) (((v)&0x1U) << 1U) +#define gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m() (U32(0x1U) << 1U) +#define gr_gpc0_mmu_l1tlb_ecc_control_r() (0x00500310U) +#define gr_gpc0_mmu_l1tlb_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 5U) +#define gr_gpc0_mmu_l1tlb_ecc_status_r() (0x00500314U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(v)\ + (((v)&0x1U) << 0U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()\ + (U32(0x1U) << 0U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(v)\ + (((v)&0x1U) << 2U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()\ + (U32(0x1U) << 2U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(v)\ + (((v)&0x1U) << 1U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()\ + (U32(0x1U) << 1U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(v)\ + (((v)&0x1U) << 3U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()\ + (U32(0x1U) << 3U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 18U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 16U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 19U) +#define gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 19U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 17U) +#define gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 17U) +#define gr_gpc0_mmu_l1tlb_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f() (0x40000000U) +#define gr_gpc0_mmu_l1tlb_ecc_address_r() (0x00500320U) +#define gr_gpc0_mmu_l1tlb_ecc_address_index_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r() (0x00500318U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s() (16U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s() (16U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r() (0x0050031cU) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s() (16U) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m()\ + (U32(0xffffU) << 0U) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s() (16U) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define gr_gpc0_gpccs_hww_esr_r() (0x00502c98U) +#define gr_gpc0_gpccs_hww_esr_ecc_corrected_f(v) (((v)&0x1U) << 0U) +#define gr_gpc0_gpccs_hww_esr_ecc_corrected_m() (U32(0x1U) << 0U) +#define gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f() (0x1U) +#define gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(v) (((v)&0x1U) << 1U) +#define gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m() (U32(0x1U) << 1U) +#define gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f() (0x2U) +#define gr_gpccs_falcon_ecc_control_r() (0x0050268cU) +#define gr_gpccs_falcon_ecc_control_inject_corrected_err_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_falcon_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 1U) +#define gr_gpc0_gpccs_falcon_ecc_status_r() (0x00502678U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(v)\ + (((v)&0x1U) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m() (U32(0x1U) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f() (0x1U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(v)\ + (((v)&0x1U) << 1U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m() (U32(0x1U) << 1U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f() (0x2U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(v)\ + (((v)&0x1U) << 4U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()\ + (U32(0x1U) << 4U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f() (0x10U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(v)\ + (((v)&0x1U) << 5U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()\ + (U32(0x1U) << 5U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f() (0x20U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 10U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 10U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f()\ + (0x400U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 8U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 8U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f()\ + (0x100U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 11U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 11U) +#define gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f()\ + (0x800U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 9U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 9U) +#define gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f()\ + (0x200U) +#define gr_gpc0_gpccs_falcon_ecc_status_reset_f(v) (((v)&0x1U) << 31U) +#define gr_gpc0_gpccs_falcon_ecc_status_reset_task_f() (0x80000000U) +#define gr_gpc0_gpccs_falcon_ecc_address_r() (0x00502684U) +#define gr_gpc0_gpccs_falcon_ecc_address_index_f(v) (((v)&0x7fffffU) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_address_row_address_s() (20U) +#define gr_gpc0_gpccs_falcon_ecc_address_row_address_f(v) (((v)&0xfffffU) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_address_row_address_m() (U32(0xfffffU) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_address_row_address_v(r)\ + (((r) >> 0U) & 0xfffffU) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r() (0x0050267cU) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s() (16U) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m()\ + (U32(0xffffU) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s() (16U) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() (0x00502680U) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m()\ + (U32(0xffffU) << 0U) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s() (16U) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define gr_fecs_falcon_ecc_control_r() (0x0040968cU) +#define gr_fecs_falcon_ecc_control_inject_corrected_err_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_falcon_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 1U) +#define gr_fecs_falcon_ecc_status_r() (0x00409678U) +#define gr_fecs_falcon_ecc_status_corrected_err_imem_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_falcon_ecc_status_corrected_err_imem_m() (U32(0x1U) << 0U) +#define gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f() (0x1U) +#define gr_fecs_falcon_ecc_status_corrected_err_dmem_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_falcon_ecc_status_corrected_err_dmem_m() (U32(0x1U) << 1U) +#define gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f() (0x2U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_imem_m() (U32(0x1U) << 4U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f() (0x10U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m() (U32(0x1U) << 5U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f() (0x20U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 10U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 10U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f()\ + (0x400U) +#define gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 8U) +#define gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 8U) +#define gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f()\ + (0x100U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 11U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 11U) +#define gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f()\ + (0x800U) +#define gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 9U) +#define gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 9U) +#define gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f()\ + (0x200U) +#define gr_fecs_falcon_ecc_status_reset_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_falcon_ecc_status_reset_task_f() (0x80000000U) +#define gr_fecs_falcon_ecc_address_r() (0x00409684U) +#define gr_fecs_falcon_ecc_address_index_f(v) (((v)&0x7fffffU) << 0U) +#define gr_fecs_falcon_ecc_address_row_address_s() (20U) +#define gr_fecs_falcon_ecc_address_row_address_f(v) (((v)&0xfffffU) << 0U) +#define gr_fecs_falcon_ecc_address_row_address_m() (U32(0xfffffU) << 0U) +#define gr_fecs_falcon_ecc_address_row_address_v(r) (((r) >> 0U) & 0xfffffU) +#define gr_fecs_falcon_ecc_corrected_err_count_r() (0x0040967cU) +#define gr_fecs_falcon_ecc_corrected_err_count_total_s() (16U) +#define gr_fecs_falcon_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_falcon_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define gr_fecs_falcon_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_fecs_falcon_ecc_corrected_err_count_unique_total_s() (16U) +#define gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define gr_fecs_falcon_ecc_corrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define gr_fecs_falcon_ecc_uncorrected_err_count_r() (0x00409680U) +#define gr_fecs_falcon_ecc_uncorrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define gr_fecs_falcon_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define gr_fecs_falcon_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s() (16U) +#define gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define gr_debug_0_r() (0x00400080U) +#define gr_debug_0_scg_force_slow_drain_tpc_m() (U32(0x1U) << 11U) +#define gr_debug_0_scg_force_slow_drain_tpc_enabled_f() (0x800U) +#define gr_debug_0_scg_force_slow_drain_tpc_disabled_f() (0x0U) +#define gr_debug_2_r() (0x00400088U) +#define gr_debug_2_gfxp_wfi_timeout_unit_m() (U32(0x1U) << 27U) +#define gr_debug_2_gfxp_wfi_timeout_unit_usec_f() (0x0U) +#define gr_debug_2_gfxp_wfi_timeout_unit_sysclk_f() (0x8000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 1dd755e8a..ae6ea548e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,736 +59,251 @@ #include #include -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) -{ - return 0x0017e204U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) -{ - return 8U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltcs_ltss_intr3_r(void) -{ - return 0x0017e388U; -} -static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 ltc_ltc0_lts0_intr3_r(void) -{ - return 0x00140588U; -} -static inline u32 ltc_ltc0_lts0_l1_cache_ecc_control_r(void) -{ - return 0x001404ecU; -} -static inline u32 ltc_ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ltc_ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) -{ - return 0x001404f0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 19U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) -{ - return 0x001404fcU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) -{ - return 0x001404f4U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) -{ - return 0x001404f8U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_address_r(void) -{ - return 0x00140520U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_address_info_ram_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_address_info_ram_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} +#define ltc_pltcg_base_v() (0x00140000U) +#define ltc_pltcg_extent_v() (0x0017ffffU) +#define ltc_ltc0_ltss_v() (0x00140200U) +#define ltc_ltc0_lts0_v() (0x00140400U) +#define ltc_ltcs_ltss_v() (0x0017e200U) +#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U) +#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U) +#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U) +#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U) +#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U) +#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU) +#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) +#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) +#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU) +#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) +#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) +#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs__v(r) (((r) >> 0U) & 0x1fU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(v)\ + (((v)&0x1U) << 24U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(r)\ + (((r) >> 24U) & 0x1U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(v) (((v)&0x1U) << 25U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(r) (((r) >> 25U) & 0x1U) +#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U) +#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U) +#define ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_cbc_param_cache_line_size_v(r) (((r) >> 24U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param2_r() (0x0017e3f4U) +#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) +#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ + (((v)&0x1fU) << 16U) +#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ + (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ + (U32(0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffffffffU) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r() (0x0017e204U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s() (8U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(v)\ + (((v)&0xffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m() (U32(0xffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U) +#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U) +#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U) +#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltcs_ltss_intr_r() (0x0017e20cU) +#define ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() (0x100U) +#define ltc_ltcs_ltss_intr_ecc_ded_error_pending_f() (0x200U) +#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f() (0x200000U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f() (0x0U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U) +#define ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() (0x1000000U) +#define ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f() (0x2000000U) +#define ltc_ltc0_lts0_intr_r() (0x0014040cU) +#define ltc_ltcs_ltss_intr3_r() (0x0017e388U) +#define ltc_ltcs_ltss_intr3_ecc_corrected_m() (U32(0x1U) << 7U) +#define ltc_ltcs_ltss_intr3_ecc_uncorrected_m() (U32(0x1U) << 8U) +#define ltc_ltc0_lts0_intr3_r() (0x00140588U) +#define ltc_ltc0_lts0_l1_cache_ecc_control_r() (0x001404ecU) +#define ltc_ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f(v)\ + (((v)&0x1U) << 4U) +#define ltc_ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 5U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_r() (0x001404f0U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(v)\ + (((v)&0x1U) << 1U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()\ + (U32(0x1U) << 1U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(v)\ + (((v)&0x1U) << 3U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()\ + (U32(0x1U) << 3U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(v)\ + (((v)&0x1U) << 5U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()\ + (U32(0x1U) << 5U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(v)\ + (((v)&0x1U) << 0U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()\ + (U32(0x1U) << 0U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(v)\ + (((v)&0x1U) << 2U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()\ + (U32(0x1U) << 2U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(v)\ + (((v)&0x1U) << 4U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()\ + (U32(0x1U) << 4U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 18U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 16U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 19U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 19U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(v)\ + (((v)&0x1U) << 17U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m()\ + (U32(0x1U) << 17U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f() (0x40000000U) +#define ltc_ltc0_lts0_l2_cache_ecc_address_r() (0x001404fcU) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() (0x001404f4U) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s() (16U) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m()\ + (U32(0xffffU) << 0U) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s() (16U) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() (0x001404f8U) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s() (16U) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m()\ + (U32(0xffffU) << 0U) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s() (16U) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU) +#define ltc_ltc0_lts0_dstg_ecc_address_r() (0x00140520U) +#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_m() (U32(0x1U) << 22U) +#define ltc_ltc0_lts0_dstg_ecc_address_info_ram_v(r) (((r) >> 22U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\ + (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\ + (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\ + (0x40000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\ + (((r) >> 16U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U) +#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltc0_lts0_tstg_info_1_r() (0x0014058cU) +#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 74f8bbb49..5e3e11187 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,176 +59,52 @@ #include #include -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4U; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204U; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} +#define mc_boot_0_r() (0x00000000U) +#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU) +#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU) +#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU) +#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU) +#define mc_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_pfifo_pending_f() (0x100U) +#define mc_intr_hub_pending_f() (0x200U) +#define mc_intr_pgraph_pending_f() (0x1000U) +#define mc_intr_pmu_pending_f() (0x1000000U) +#define mc_intr_ltc_pending_f() (0x2000000U) +#define mc_intr_priv_ring_pending_f() (0x40000000U) +#define mc_intr_pbus_pending_f() (0x10000000U) +#define mc_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_clear_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_enable_r() (0x00000200U) +#define mc_enable_xbar_enabled_f() (0x4U) +#define mc_enable_l2_enabled_f() (0x8U) +#define mc_enable_pmedia_s() (1U) +#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) +#define mc_enable_pmedia_m() (U32(0x1U) << 4U) +#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) +#define mc_enable_ce0_m() (U32(0x1U) << 6U) +#define mc_enable_pfifo_enabled_f() (0x100U) +#define mc_enable_pgraph_enabled_f() (0x1000U) +#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U) +#define mc_enable_pwr_disabled_v() (0x00000000U) +#define mc_enable_pwr_enabled_f() (0x2000U) +#define mc_enable_pfb_enabled_f() (0x100000U) +#define mc_enable_ce2_m() (U32(0x1U) << 21U) +#define mc_enable_ce2_enabled_f() (0x200000U) +#define mc_enable_blg_enabled_f() (0x8000000U) +#define mc_enable_perfmon_enabled_f() (0x10000000U) +#define mc_enable_hub_enabled_f() (0x20000000U) +#define mc_intr_ltc_r() (0x000001c0U) +#define mc_enable_pb_r() (0x00000204U) +#define mc_enable_pb_0_s() (1U) +#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) +#define mc_enable_pb_0_m() (U32(0x1U) << 0U) +#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) +#define mc_enable_pb_0_enabled_v() (0x00000001U) +#define mc_enable_pb_sel_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 38ddd8b05..84cdb2f29 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,596 +59,193 @@ #include #include -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000003U; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method3_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_data0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_config_l2_evict_first_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_l2_evict_normal_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_config_ce_split_enable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_ce_split_disable_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_config_auth_level_non_privileged_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_config_userd_writeback_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_userd_writeback_enable_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_eng_reset_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_1_ctxnotvalid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000U; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_target_eng_ctx_valid_true_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_target_eng_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_ce_ctx_valid_true_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_target_ce_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) -{ - return 0x3000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_true_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_set_channel_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_set_channel_info_veid_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout_period_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_timeout_period_init_f(void) -{ - return 0x10000U; -} +#define pbdma_gp_entry1_r() (0x10000004U) +#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) +#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) +#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) +#define pbdma_gp_base_r(i)\ + (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base__size_1_v() (0x00000003U) +#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) +#define pbdma_gp_base_rsvd_s() (3U) +#define pbdma_gp_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) +#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) +#define pbdma_gp_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_get_r(i)\ + (nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_put_r(i)\ + (nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_r(i)\ + (nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_r(i)\ + (nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_r(i)\ + (nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_priv_user_f() (0x0U) +#define pbdma_pb_header_method_zero_f() (0x0U) +#define pbdma_pb_header_subchannel_zero_f() (0x0U) +#define pbdma_pb_header_level_main_f() (0x0U) +#define pbdma_pb_header_first_true_f() (0x400000U) +#define pbdma_pb_header_type_inc_f() (0x20000000U) +#define pbdma_pb_header_type_non_inc_f() (0x60000000U) +#define pbdma_hdr_shadow_r(i)\ + (nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_0_r(i)\ + (nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_1_r(i)\ + (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_r(i)\ + (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) +#define pbdma_subdevice_status_active_f() (0x10000000U) +#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) +#define pbdma_method0_r(i)\ + (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method0_fifo_size_v() (0x00000004U) +#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) +#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) +#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) +#define pbdma_method0_first_true_f() (0x400000U) +#define pbdma_method0_valid_true_f() (0x80000000U) +#define pbdma_method1_r(i)\ + (nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method2_r(i)\ + (nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method3_r(i)\ + (nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_data0_r(i)\ + (nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_r(i)\ + (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_retry_man_2_f() (0x2U) +#define pbdma_acquire_retry_exp_2_f() (0x100U) +#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) +#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) +#define pbdma_acquire_timeout_exp_max_f() (0x7800U) +#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) +#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) +#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) +#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) +#define pbdma_acquire_timeout_en_disable_f() (0x0U) +#define pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_channel_r(i)\ + (nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_r(i)\ + (nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_hw_valid_f() (0xfaceU) +#define pbdma_signature_sw_zero_f() (0x0U) +#define pbdma_userd_r(i)\ + (nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_target_vid_mem_f() (0x0U) +#define pbdma_userd_target_sys_mem_coh_f() (0x2U) +#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) +#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) +#define pbdma_config_r(i)\ + (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_config_l2_evict_first_f() (0x0U) +#define pbdma_config_l2_evict_normal_f() (0x1U) +#define pbdma_config_ce_split_enable_f() (0x0U) +#define pbdma_config_ce_split_disable_f() (0x10U) +#define pbdma_config_auth_level_non_privileged_f() (0x0U) +#define pbdma_config_auth_level_privileged_f() (0x100U) +#define pbdma_config_userd_writeback_disable_f() (0x0U) +#define pbdma_config_userd_writeback_enable_f() (0x1000U) +#define pbdma_userd_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) +#define pbdma_hce_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) +#define pbdma_intr_0_r(i)\ + (nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_intr_0_memreq_pending_f() (0x1U) +#define pbdma_intr_0_memack_timeout_pending_f() (0x2U) +#define pbdma_intr_0_memack_extra_pending_f() (0x4U) +#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U) +#define pbdma_intr_0_memdat_extra_pending_f() (0x10U) +#define pbdma_intr_0_memflush_pending_f() (0x20U) +#define pbdma_intr_0_memop_pending_f() (0x40U) +#define pbdma_intr_0_lbconnect_pending_f() (0x80U) +#define pbdma_intr_0_lbreq_pending_f() (0x100U) +#define pbdma_intr_0_lback_timeout_pending_f() (0x200U) +#define pbdma_intr_0_lback_extra_pending_f() (0x400U) +#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U) +#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U) +#define pbdma_intr_0_gpfifo_pending_f() (0x2000U) +#define pbdma_intr_0_gpptr_pending_f() (0x4000U) +#define pbdma_intr_0_gpentry_pending_f() (0x8000U) +#define pbdma_intr_0_gpcrc_pending_f() (0x10000U) +#define pbdma_intr_0_pbptr_pending_f() (0x20000U) +#define pbdma_intr_0_pbentry_pending_f() (0x40000U) +#define pbdma_intr_0_pbcrc_pending_f() (0x80000U) +#define pbdma_intr_0_clear_faulted_error_pending_f() (0x100000U) +#define pbdma_intr_0_method_pending_f() (0x200000U) +#define pbdma_intr_0_methodcrc_pending_f() (0x400000U) +#define pbdma_intr_0_device_pending_f() (0x800000U) +#define pbdma_intr_0_eng_reset_pending_f() (0x1000000U) +#define pbdma_intr_0_semaphore_pending_f() (0x2000000U) +#define pbdma_intr_0_acquire_pending_f() (0x4000000U) +#define pbdma_intr_0_pri_pending_f() (0x8000000U) +#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U) +#define pbdma_intr_0_pbseg_pending_f() (0x40000000U) +#define pbdma_intr_0_signature_pending_f() (0x80000000U) +#define pbdma_intr_1_r(i)\ + (nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_1_ctxnotvalid_m() (U32(0x1U) << 31U) +#define pbdma_intr_1_ctxnotvalid_pending_f() (0x80000000U) +#define pbdma_intr_en_0_r(i)\ + (nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_0_lbreq_enabled_f() (0x100U) +#define pbdma_intr_en_1_r(i)\ + (nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_r(i)\ + (nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_lbreq_enabled_f() (0x100U) +#define pbdma_intr_stall_1_r(i)\ + (nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U) +#define pbdma_udma_nop_r() (0x00000008U) +#define pbdma_runlist_timeslice_r(i)\ + (nvgpu_safe_add_u32(0x000400f8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_runlist_timeslice_timeout_128_f() (0x80U) +#define pbdma_runlist_timeslice_timescale_3_f() (0x3000U) +#define pbdma_runlist_timeslice_enable_true_f() (0x10000000U) +#define pbdma_target_r(i)\ + (nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_engine_sw_f() (0x1fU) +#define pbdma_target_eng_ctx_valid_true_f() (0x10000U) +#define pbdma_target_eng_ctx_valid_false_f() (0x0U) +#define pbdma_target_ce_ctx_valid_true_f() (0x20000U) +#define pbdma_target_ce_ctx_valid_false_f() (0x0U) +#define pbdma_target_host_tsg_event_reason_pbdma_idle_f() (0x0U) +#define pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f()\ + (0x1000000U) +#define pbdma_target_host_tsg_event_reason_tsg_yield_f() (0x2000000U) +#define pbdma_target_host_tsg_event_reason_host_subchannel_switch_f()\ + (0x3000000U) +#define pbdma_target_should_send_tsg_event_true_f() (0x20000000U) +#define pbdma_target_should_send_tsg_event_false_f() (0x0U) +#define pbdma_target_needs_host_tsg_event_true_f() (0x80000000U) +#define pbdma_target_needs_host_tsg_event_false_f() (0x0U) +#define pbdma_set_channel_info_r(i)\ + (nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_set_channel_info_veid_f(v) (((v)&0x3fU) << 8U) +#define pbdma_timeout_r(i)\ + (nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U) +#define pbdma_timeout_period_max_f() (0xffffffffU) +#define pbdma_timeout_period_init_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h index 97d9bd4e6..657303ccf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,208 +59,58 @@ #include #include -static inline u32 perf_pmmgpc_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmsys_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmgpc_base_v(void) -{ - return 0x00180000U; -} -static inline u32 perf_pmmgpc_extent_v(void) -{ - return 0x00183fffU; -} -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x00240000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x00243fffU; -} -static inline u32 perf_pmmfbp_base_v(void) -{ - return 0x00200000U; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x0024a000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x0024a070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x0024a074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x0024a078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x0024a07cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x0024a084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x0024a088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x0024a0a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmmsys_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0024006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmsys_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmfbp_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmfbp_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmgpc_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmgpc_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} +#define perf_pmmgpc_perdomain_offset_v() (0x00000200U) +#define perf_pmmsys_perdomain_offset_v() (0x00000200U) +#define perf_pmmgpc_base_v() (0x00180000U) +#define perf_pmmgpc_extent_v() (0x00183fffU) +#define perf_pmmsys_base_v() (0x00240000U) +#define perf_pmmsys_extent_v() (0x00243fffU) +#define perf_pmmfbp_base_v() (0x00200000U) +#define perf_pmasys_control_r() (0x0024a000U) +#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) +#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) +#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) +#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) +#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) +#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) +#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_mem_block_r() (0x0024a070U) +#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) +#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) +#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) +#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) +#define perf_pmasys_mem_block_target_lfb_f() (0x0U) +#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U) +#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) +#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) +#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) +#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) +#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) +#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) +#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) +#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) +#define perf_pmasys_mem_block_valid_false_f() (0x0U) +#define perf_pmasys_outbase_r() (0x0024a074U) +#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_outbaseupper_r() (0x0024a078U) +#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) +#define perf_pmasys_outsize_r() (0x0024a07cU) +#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_mem_bytes_r() (0x0024a084U) +#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_mem_bump_r() (0x0024a088U) +#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_enginestatus_r() (0x0024a0a4U) +#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) +#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) +#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) +#define perf_pmmsys_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0024006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmsys_engine_sel__size_1_v() (0x00000020U) +#define perf_pmmfbp_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmfbp_engine_sel__size_1_v() (0x00000020U) +#define perf_pmmgpc_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmgpc_engine_sel__size_1_v() (0x00000020U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h index 89e099a99..c80ac4dee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pram_data032_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U)); -} +#define pram_data032_r(i)\ + (nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index 49be492db..2cfeb42b5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,112 +59,33 @@ #include #include -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} +#define pri_ringmaster_command_r() (0x0012004cU) +#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U) +#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU) +#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U) +#define pri_ringmaster_command_cmd_start_ring_f() (0x1U) +#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U) +#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U) +#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U) +#define pri_ringmaster_command_data_r() (0x00120048U) +#define pri_ringmaster_start_results_r() (0x00120050U) +#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U) +#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U) +#define pri_ringmaster_intr_status0_r() (0x00120058U) +#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\ + (((r) >> 0U) & 0x1U) +#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U) +#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U) +#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\ + (((r) >> 8U) & 0x1U) +#define pri_ringmaster_intr_status1_r() (0x0012005cU) +#define pri_ringmaster_global_ctl_r() (0x00120060U) +#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U) +#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U) +#define pri_ringmaster_enum_fbp_r() (0x00120074U) +#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_gpc_r() (0x00120078U) +#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_ltc_r() (0x0012006cU) +#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h index f8c898cb2..1b72cce9e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,24 +59,10 @@ #include #include -static inline u32 pri_ringstation_gpc_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} +#define pri_ringstation_gpc_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00128300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U) +#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) +#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) +#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index edb07d772..09cd91da4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,36 +59,14 @@ #include #include -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} +#define pri_ringstation_sys_master_config_r(i)\ + (nvgpu_safe_add_u32(0x00122300U, nvgpu_safe_mult_u32((i), 4U))) +#define pri_ringstation_sys_decode_config_r() (0x00122204U) +#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U) +#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\ + (0x1U) +#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U) +#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) +#define pri_ringstation_sys_priv_error_info_r() (0x00122128U) +#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 52db61818..69bf719df 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,136 +59,37 @@ #include #include -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_smpc_base_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_smpc_shared_base_v(void) -{ - return 0x00000300U; -} -static inline u32 proj_smpc_unique_base_v(void) -{ - return 0x00000600U; -} -static inline u32 proj_smpc_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_sm_stride_v(void) -{ - return 0x00000080U; -} +#define proj_gpc_base_v() (0x00500000U) +#define proj_gpc_shared_base_v() (0x00418000U) +#define proj_gpc_stride_v() (0x00008000U) +#define proj_gpc_priv_stride_v() (0x00000800U) +#define proj_ltc_stride_v() (0x00002000U) +#define proj_lts_stride_v() (0x00000200U) +#define proj_fbpa_stride_v() (0x00004000U) +#define proj_ppc_in_gpc_base_v() (0x00003000U) +#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U) +#define proj_ppc_in_gpc_stride_v() (0x00000200U) +#define proj_rop_base_v() (0x00410000U) +#define proj_rop_shared_base_v() (0x00408800U) +#define proj_rop_stride_v() (0x00000400U) +#define proj_tpc_in_gpc_base_v() (0x00004000U) +#define proj_tpc_in_gpc_stride_v() (0x00000800U) +#define proj_tpc_in_gpc_shared_base_v() (0x00001800U) +#define proj_smpc_base_v() (0x00000200U) +#define proj_smpc_shared_base_v() (0x00000300U) +#define proj_smpc_unique_base_v() (0x00000600U) +#define proj_smpc_stride_v() (0x00000100U) +#define proj_host_num_engines_v() (0x00000004U) +#define proj_host_num_pbdma_v() (0x00000003U) +#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000004U) +#define proj_scal_litter_num_fbps_v() (0x00000001U) +#define proj_scal_litter_num_fbpas_v() (0x00000001U) +#define proj_scal_litter_num_gpcs_v() (0x00000001U) +#define proj_scal_litter_num_pes_per_gpc_v() (0x00000002U) +#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U) +#define proj_scal_litter_num_zcull_banks_v() (0x00000004U) +#define proj_scal_litter_num_sm_per_tpc_v() (0x00000002U) +#define proj_scal_max_gpcs_v() (0x00000020U) +#define proj_scal_max_tpc_per_gpc_v() (0x00000008U) +#define proj_sm_stride_v() (0x00000080U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 894881521..f83cfff0b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,1192 +59,337 @@ #include #include -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) -{ - return 0x800U; -} -static inline u32 pwr_falcon_irqstat_ext_ecc_parity_true_f(void) -{ - return 0x400U; -} -static inline u32 pwr_pmu_ecc_intr_status_r(void) -{ - return 0x0010abfcU; -} -static inline u32 pwr_pmu_ecc_intr_status_corrected_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_ecc_intr_status_corrected_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_ecc_intr_status_uncorrected_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_ecc_intr_status_uncorrected_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmset_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pwr_falcon_irqmset_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pwr_falcon_irqmclr_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ecc_parity_f(u32 v) -{ - return (v & 0x1U) << 26U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_host_error_r(void) -{ - return 0x0010a990U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_falcon_ecc_control_r(void) -{ - return 0x0010a484U; -} -static inline u32 pwr_pmu_falcon_ecc_control_inject_corrected_err_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_control_inject_uncorrected_err_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_falcon_ecc_status_r(void) -{ - return 0x0010a6b0U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_imem_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_dmem_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 pwr_pmu_falcon_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_falcon_ecc_status_reset_task_f(void) -{ - return 0x80000000U; -} -static inline u32 pwr_pmu_falcon_ecc_address_r(void) -{ - return 0x0010a6b4U; -} -static inline u32 pwr_pmu_falcon_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_type_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 pwr_pmu_falcon_ecc_address_type_imem_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_type_dmem_f(void) -{ - return 0x100000U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_address_row_address_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_r(void) -{ - return 0x0010a6b8U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_corrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_r(void) -{ - return 0x0010a6bcU; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_s(void) -{ - return 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} +#define pwr_falcon_irqsset_r() (0x0010a000U) +#define pwr_falcon_irqsset_swgen0_set_f() (0x40U) +#define pwr_falcon_irqsclr_r() (0x0010a004U) +#define pwr_falcon_irqstat_r() (0x0010a008U) +#define pwr_falcon_irqstat_halt_true_f() (0x10U) +#define pwr_falcon_irqstat_exterr_true_f() (0x20U) +#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) +#define pwr_falcon_irqstat_ext_second_true_f() (0x800U) +#define pwr_falcon_irqstat_ext_ecc_parity_true_f() (0x400U) +#define pwr_pmu_ecc_intr_status_r() (0x0010abfcU) +#define pwr_pmu_ecc_intr_status_corrected_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_ecc_intr_status_corrected_m() (U32(0x1U) << 0U) +#define pwr_pmu_ecc_intr_status_uncorrected_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_ecc_intr_status_uncorrected_m() (U32(0x1U) << 1U) +#define pwr_falcon_irqmode_r() (0x0010a00cU) +#define pwr_falcon_irqmset_r() (0x0010a010U) +#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmset_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmset_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqmset_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqmset_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqmset_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqmset_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqmset_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqmset_ext_rsvd8_f(v) (((v)&0x1U) << 15U) +#define pwr_falcon_irqmset_ext_ecc_parity_f(v) (((v)&0x1U) << 10U) +#define pwr_falcon_irqmclr_r() (0x0010a014U) +#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmclr_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqmclr_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqmclr_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqmclr_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqmclr_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqmclr_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqmclr_ext_rsvd8_f(v) (((v)&0x1U) << 15U) +#define pwr_falcon_irqmclr_ext_ecc_parity_f(v) (((v)&0x1U) << 10U) +#define pwr_falcon_irqmask_r() (0x0010a018U) +#define pwr_falcon_irqdest_r() (0x0010a01cU) +#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqdest_host_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqdest_host_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqdest_host_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqdest_host_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqdest_host_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqdest_host_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqdest_host_ext_rsvd8_f(v) (((v)&0x1U) << 15U) +#define pwr_falcon_irqdest_host_ext_ecc_parity_f(v) (((v)&0x1U) << 10U) +#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pwr_falcon_irqdest_target_ext_ctxe_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_irqdest_target_ext_limitv_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_irqdest_target_ext_second_f(v) (((v)&0x1U) << 27U) +#define pwr_falcon_irqdest_target_ext_therm_f(v) (((v)&0x1U) << 28U) +#define pwr_falcon_irqdest_target_ext_miscio_f(v) (((v)&0x1U) << 29U) +#define pwr_falcon_irqdest_target_ext_rttimer_f(v) (((v)&0x1U) << 30U) +#define pwr_falcon_irqdest_target_ext_rsvd8_f(v) (((v)&0x1U) << 31U) +#define pwr_falcon_irqdest_target_ext_ecc_parity_f(v) (((v)&0x1U) << 26U) +#define pwr_falcon_curctx_r() (0x0010a050U) +#define pwr_falcon_nxtctx_r() (0x0010a054U) +#define pwr_falcon_mailbox0_r() (0x0010a040U) +#define pwr_falcon_mailbox1_r() (0x0010a044U) +#define pwr_falcon_itfen_r() (0x0010a048U) +#define pwr_falcon_itfen_ctxen_enable_f() (0x1U) +#define pwr_falcon_idlestate_r() (0x0010a04cU) +#define pwr_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pwr_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pwr_falcon_os_r() (0x0010a080U) +#define pwr_falcon_engctl_r() (0x0010a0a4U) +#define pwr_falcon_cpuctl_r() (0x0010a100U) +#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) +#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) +#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) +#define pwr_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_sctl_r() (0x0010a240U) +#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pwr_falcon_bootvec_r() (0x0010a104U) +#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_falcon_dmactl_r() (0x0010a10cU) +#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pwr_falcon_hwcfg_r() (0x0010a108U) +#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pwr_falcon_dmatrfbase_r() (0x0010a110U) +#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) +#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) +#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) +#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) +#define pwr_falcon_exterraddr_r() (0x0010a168U) +#define pwr_falcon_exterrstat_r() (0x0010a16cU) +#define pwr_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pwr_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) +#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) +#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) +#define pwr_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_new_instblk_r() (0x0010a480U) +#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define pwr_pmu_new_instblk_target_fb_f() (0x0U) +#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) +#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) +#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) +#define pwr_pmu_mutex_id_r() (0x0010a488U) +#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) +#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) +#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) +#define pwr_pmu_mutex_r(i)\ + (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mutex__size_1_v() (0x00000010U) +#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) +#define pwr_pmu_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_head__size_1_v() (0x00000008U) +#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_tail__size_1_v() (0x00000008U) +#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_head_r() (0x0010a4c8U) +#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) +#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_idle_mask_r(i)\ + (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U) +#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) +#define pwr_pmu_idle_count_r(i)\ + (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) +#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_idle_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) +#define pwr_pmu_idle_ctrl_value_busy_f() (0x2U) +#define pwr_pmu_idle_ctrl_value_always_f() (0x3U) +#define pwr_pmu_idle_ctrl_filter_m() (U32(0x1U) << 2U) +#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) +#define pwr_pmu_idle_threshold_r(i)\ + (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_intr_r() (0x0010a9e8U) +#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) +#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) +#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) +#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_intr_clear_v() (0x00000001U) +#define pwr_pmu_idle_mask_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_mask_1_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_ctrl_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_debug_r(i)\ + (nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_debug__size_1_v() (0x00000004U) +#define pwr_pmu_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mailbox__size_1_v() (0x0000000cU) +#define pwr_pmu_bar0_addr_r() (0x0010a7a0U) +#define pwr_pmu_bar0_data_r() (0x0010a7a4U) +#define pwr_pmu_bar0_ctl_r() (0x0010a7acU) +#define pwr_pmu_bar0_timeout_r() (0x0010a7a8U) +#define pwr_pmu_bar0_fecs_error_r() (0x0010a988U) +#define pwr_pmu_bar0_host_error_r() (0x0010a990U) +#define pwr_pmu_bar0_error_status_r() (0x0010a7b0U) +#define pwr_pmu_bar0_error_status_timeout_host_m() (U32(0x1U) << 0U) +#define pwr_pmu_bar0_error_status_timeout_fecs_m() (U32(0x1U) << 1U) +#define pwr_pmu_bar0_error_status_cmd_hwerr_m() (U32(0x1U) << 2U) +#define pwr_pmu_bar0_error_status_err_cmd_m() (U32(0x1U) << 3U) +#define pwr_pmu_bar0_error_status_hosterr_m() (U32(0x1U) << 30U) +#define pwr_pmu_bar0_error_status_fecserr_m() (U32(0x1U) << 31U) +#define pwr_pmu_pg_idlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_ppuidlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_idle_cnt_r(i)\ + (nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_intren_r(i)\ + (nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_falcon_ecc_control_r() (0x0010a484U) +#define pwr_pmu_falcon_ecc_control_inject_corrected_err_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_falcon_ecc_control_inject_uncorrected_err_f(v)\ + (((v)&0x1U) << 1U) +#define pwr_pmu_falcon_ecc_status_r() (0x0010a6b0U) +#define pwr_pmu_falcon_ecc_status_corrected_err_imem_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_falcon_ecc_status_corrected_err_imem_m() (U32(0x1U) << 0U) +#define pwr_pmu_falcon_ecc_status_corrected_err_dmem_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_falcon_ecc_status_corrected_err_dmem_m() (U32(0x1U) << 1U) +#define pwr_pmu_falcon_ecc_status_uncorrected_err_imem_f(v) (((v)&0x1U) << 8U) +#define pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m() (U32(0x1U) << 8U) +#define pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_f(v) (((v)&0x1U) << 9U) +#define pwr_pmu_falcon_ecc_status_uncorrected_err_dmem_m() (U32(0x1U) << 9U) +#define pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 16U) +#define pwr_pmu_falcon_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(v)\ + (((v)&0x1U) << 18U) +#define pwr_pmu_falcon_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define pwr_pmu_falcon_ecc_status_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_falcon_ecc_status_reset_task_f() (0x80000000U) +#define pwr_pmu_falcon_ecc_address_r() (0x0010a6b4U) +#define pwr_pmu_falcon_ecc_address_index_f(v) (((v)&0xffffffU) << 0U) +#define pwr_pmu_falcon_ecc_address_type_f(v) (((v)&0xfU) << 20U) +#define pwr_pmu_falcon_ecc_address_type_imem_f() (0x0U) +#define pwr_pmu_falcon_ecc_address_type_dmem_f() (0x100000U) +#define pwr_pmu_falcon_ecc_address_row_address_s() (16U) +#define pwr_pmu_falcon_ecc_address_row_address_f(v) (((v)&0xffffU) << 0U) +#define pwr_pmu_falcon_ecc_address_row_address_m() (U32(0xffffU) << 0U) +#define pwr_pmu_falcon_ecc_address_row_address_v(r) (((r) >> 0U) & 0xffffU) +#define pwr_pmu_falcon_ecc_corrected_err_count_r() (0x0010a6b8U) +#define pwr_pmu_falcon_ecc_corrected_err_count_total_s() (16U) +#define pwr_pmu_falcon_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define pwr_pmu_falcon_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define pwr_pmu_falcon_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define pwr_pmu_falcon_ecc_corrected_err_count_unique_total_s() (16U) +#define pwr_pmu_falcon_ecc_corrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define pwr_pmu_falcon_ecc_corrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define pwr_pmu_falcon_ecc_corrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_r() (0x0010a6bcU) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_total_s() (16U) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_s() (16U) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_f(v)\ + (((v)&0xffffU) << 16U) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_m()\ + (U32(0xffffU) << 16U) +#define pwr_pmu_falcon_ecc_uncorrected_err_count_unique_total_v(r)\ + (((r) >> 16U) & 0xffffU) +#define pwr_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_target_local_fb_f() (0x0U) +#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pwr_fbif_transcfg_mem_type_s() (1U) +#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pwr_fbif_transcfg_mem_type_physical_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index 71ae0c479..4a2886fca 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,760 +59,205 @@ #include #include -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_engine_wfi_mode_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_engine_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_wfi_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_engine_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_engine_wfi_target_local_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_engine_wfi_veid_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ram_in_engine_wfi_veid_w(void) -{ - return 134U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) -{ - return 136U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) -{ - return 137U; -} -static inline u32 ram_in_sc_pdb_valid_w(u32 i) -{ - return 166U + ((i*1U)/32U); -} -static inline u32 ram_in_sc_pdb_valid__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) -{ - return (v & 0x3U) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) -{ - return (v & 0x1U) << (2U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_vol_w(u32 i) -{ - return 168U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) -{ - return (v & 0x1U) << (4U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) -{ - return (v & 0x1U) << (5U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) -{ - return (v & 0x1U) << (10U + i*0U); -} -static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) -{ - return (v & 0x1U) << (11U + i*0U); -} -static inline u32 ram_in_sc_big_page_size__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_big_page_size_64kb_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) -{ - return (v & 0xfffffU) << (12U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_lo_w(u32 i) -{ - return 168U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) -{ - return (v & 0xffffffffU) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_hi_w(u32 i) -{ - return 169U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_big_page_size_0_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_sc_big_page_size_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) -{ - return 169U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_sem_addr_hi_w(void) -{ - return 14U; -} -static inline u32 ram_fc_sem_addr_lo_w(void) -{ - return 15U; -} -static inline u32 ram_fc_sem_payload_lo_w(void) -{ - return 16U; -} -static inline u32 ram_fc_sem_payload_hi_w(void) -{ - return 39U; -} -static inline u32 ram_fc_sem_execute_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58U; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62U; -} -static inline u32 ram_fc_set_channel_info_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000010U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ram_rl_entry_type_channel_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_type_tsg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) -{ - return (v & 0x3U) << 6U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_length_init_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_tsg_length_min_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_tsg_length_max_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} +#define ram_in_ramfc_s() (4096U) +#define ram_in_ramfc_w() (0U) +#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_page_dir_base_target_w() (128U) +#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) +#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) +#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) +#define ram_in_page_dir_base_vol_w() (128U) +#define ram_in_page_dir_base_vol_true_f() (0x4U) +#define ram_in_page_dir_base_vol_false_f() (0x0U) +#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_w() (128U) +#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) +#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) +#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) +#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) +#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) +#define ram_in_use_ver2_pt_format_w() (128U) +#define ram_in_use_ver2_pt_format_true_f() (0x400U) +#define ram_in_use_ver2_pt_format_false_f() (0x0U) +#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) +#define ram_in_big_page_size_m() (U32(0x1U) << 11U) +#define ram_in_big_page_size_w() (128U) +#define ram_in_big_page_size_128kb_f() (0x0U) +#define ram_in_big_page_size_64kb_f() (0x800U) +#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_page_dir_base_lo_w() (128U) +#define ram_in_page_dir_base_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_page_dir_base_hi_w() (129U) +#define ram_in_engine_cs_w() (132U) +#define ram_in_engine_cs_wfi_v() (0x00000000U) +#define ram_in_engine_cs_wfi_f() (0x0U) +#define ram_in_engine_cs_fg_v() (0x00000001U) +#define ram_in_engine_cs_fg_f() (0x8U) +#define ram_in_engine_wfi_mode_f(v) (((v)&0x1U) << 2U) +#define ram_in_engine_wfi_mode_w() (132U) +#define ram_in_engine_wfi_mode_physical_v() (0x00000000U) +#define ram_in_engine_wfi_mode_virtual_v() (0x00000001U) +#define ram_in_engine_wfi_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_engine_wfi_target_w() (132U) +#define ram_in_engine_wfi_target_sys_mem_coh_v() (0x00000002U) +#define ram_in_engine_wfi_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_in_engine_wfi_target_local_mem_v() (0x00000000U) +#define ram_in_engine_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_engine_wfi_ptr_lo_w() (132U) +#define ram_in_engine_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_engine_wfi_ptr_hi_w() (133U) +#define ram_in_engine_wfi_veid_f(v) (((v)&0x3fU) << 0U) +#define ram_in_engine_wfi_veid_w() (134U) +#define ram_in_eng_method_buffer_addr_lo_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_eng_method_buffer_addr_lo_w() (136U) +#define ram_in_eng_method_buffer_addr_hi_f(v) (((v)&0x1ffffU) << 0U) +#define ram_in_eng_method_buffer_addr_hi_w() (137U) +#define ram_in_sc_pdb_valid_w(i)\ + (166U + ((i*1U)/32U)) +#define ram_in_sc_pdb_valid__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_f(v, i)\ + (((v) & 0x3) << (0U + i*0U)) +#define ram_in_sc_page_dir_base_target__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_vid_mem_v() (0x00000000U) +#define ram_in_sc_page_dir_base_target_invalid_v() (0x00000001U) +#define ram_in_sc_page_dir_base_target_sys_mem_coh_v() (0x00000002U) +#define ram_in_sc_page_dir_base_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_in_sc_page_dir_base_vol_f(v, i)\ + (((v) & 0x1) << (2U + i*0U)) +#define ram_in_sc_page_dir_base_vol_w(i)\ + (168U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_vol__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_vol_true_v() (0x00000001U) +#define ram_in_sc_page_dir_base_vol_false_v() (0x00000000U) +#define ram_in_sc_page_dir_base_fault_replay_tex_f(v, i)\ + (((v) & 0x1) << (4U + i*0U)) +#define ram_in_sc_page_dir_base_fault_replay_tex__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_fault_replay_tex_enabled_v() (0x00000001U) +#define ram_in_sc_page_dir_base_fault_replay_tex_disabled_v() (0x00000000U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_f(v, i)\ + (((v) & 0x1) << (5U + i*0U)) +#define ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v() (0x00000001U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v() (0x00000000U) +#define ram_in_sc_use_ver2_pt_format_f(v, i)\ + (((v) & 0x1) << (10U + i*0U)) +#define ram_in_sc_use_ver2_pt_format__size_1_v() (0x00000040U) +#define ram_in_sc_use_ver2_pt_format_false_v() (0x00000000U) +#define ram_in_sc_use_ver2_pt_format_true_v() (0x00000001U) +#define ram_in_sc_big_page_size_f(v, i)\ + (((v) & 0x1) << (11U + i*0U)) +#define ram_in_sc_big_page_size__size_1_v() (0x00000040U) +#define ram_in_sc_big_page_size_64kb_v() (0x00000001U) +#define ram_in_sc_page_dir_base_lo_f(v, i)\ + (((v) & 0xfffff) << (12U + i*0U)) +#define ram_in_sc_page_dir_base_lo_w(i)\ + (168U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_lo__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_hi_f(v, i)\ + (((v) & 0xffffffff) << (0U + i*0U)) +#define ram_in_sc_page_dir_base_hi_w(i)\ + (169U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_hi__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_0_f(v) (((v)&0x3U) << 0U) +#define ram_in_sc_page_dir_base_target_0_w() (168U) +#define ram_in_sc_page_dir_base_vol_0_f(v) (((v)&0x1U) << 2U) +#define ram_in_sc_page_dir_base_vol_0_w() (168U) +#define ram_in_sc_page_dir_base_fault_replay_tex_0_f(v) (((v)&0x1U) << 4U) +#define ram_in_sc_page_dir_base_fault_replay_tex_0_w() (168U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_0_f(v) (((v)&0x1U) << 5U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_0_w() (168U) +#define ram_in_sc_use_ver2_pt_format_0_f(v) (((v)&0x1U) << 10U) +#define ram_in_sc_use_ver2_pt_format_0_w() (168U) +#define ram_in_sc_big_page_size_0_f(v) (((v)&0x1U) << 11U) +#define ram_in_sc_big_page_size_0_w() (168U) +#define ram_in_sc_page_dir_base_lo_0_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_sc_page_dir_base_lo_0_w() (168U) +#define ram_in_sc_page_dir_base_hi_0_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_sc_page_dir_base_hi_0_w() (169U) +#define ram_in_base_shift_v() (0x0000000cU) +#define ram_in_alloc_size_v() (0x00001000U) +#define ram_fc_size_val_v() (0x00000200U) +#define ram_fc_gp_put_w() (0U) +#define ram_fc_userd_w() (2U) +#define ram_fc_userd_hi_w() (3U) +#define ram_fc_signature_w() (4U) +#define ram_fc_gp_get_w() (5U) +#define ram_fc_pb_get_w() (6U) +#define ram_fc_pb_get_hi_w() (7U) +#define ram_fc_pb_top_level_get_w() (8U) +#define ram_fc_pb_top_level_get_hi_w() (9U) +#define ram_fc_acquire_w() (12U) +#define ram_fc_sem_addr_hi_w() (14U) +#define ram_fc_sem_addr_lo_w() (15U) +#define ram_fc_sem_payload_lo_w() (16U) +#define ram_fc_sem_payload_hi_w() (39U) +#define ram_fc_sem_execute_w() (17U) +#define ram_fc_gp_base_w() (18U) +#define ram_fc_gp_base_hi_w() (19U) +#define ram_fc_gp_fetch_w() (20U) +#define ram_fc_pb_fetch_w() (21U) +#define ram_fc_pb_fetch_hi_w() (22U) +#define ram_fc_pb_put_w() (23U) +#define ram_fc_pb_put_hi_w() (24U) +#define ram_fc_pb_header_w() (33U) +#define ram_fc_pb_count_w() (34U) +#define ram_fc_subdevice_w() (37U) +#define ram_fc_target_w() (43U) +#define ram_fc_hce_ctrl_w() (57U) +#define ram_fc_chid_w() (58U) +#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) +#define ram_fc_chid_id_w() (0U) +#define ram_fc_config_w() (61U) +#define ram_fc_runlist_timeslice_w() (62U) +#define ram_fc_set_channel_info_w() (63U) +#define ram_userd_base_shift_v() (0x00000009U) +#define ram_userd_chan_size_v() (0x00000200U) +#define ram_userd_put_w() (16U) +#define ram_userd_get_w() (17U) +#define ram_userd_ref_w() (18U) +#define ram_userd_put_hi_w() (19U) +#define ram_userd_top_level_get_w() (22U) +#define ram_userd_top_level_get_hi_w() (23U) +#define ram_userd_get_hi_w() (24U) +#define ram_userd_gp_get_w() (34U) +#define ram_userd_gp_put_w() (35U) +#define ram_userd_gp_top_level_get_w() (22U) +#define ram_userd_gp_top_level_get_hi_w() (23U) +#define ram_rl_entry_size_v() (0x00000010U) +#define ram_rl_entry_type_f(v) (((v)&0x1U) << 0U) +#define ram_rl_entry_type_channel_v() (0x00000000U) +#define ram_rl_entry_type_tsg_v() (0x00000001U) +#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_runqueue_selector_f(v) (((v)&0x1U) << 1U) +#define ram_rl_entry_chan_inst_target_f(v) (((v)&0x3U) << 4U) +#define ram_rl_entry_chan_inst_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_rl_entry_chan_inst_target_sys_mem_coh_v() (0x00000002U) +#define ram_rl_entry_chan_inst_target_vid_mem_v() (0x00000000U) +#define ram_rl_entry_chan_userd_target_f(v) (((v)&0x3U) << 6U) +#define ram_rl_entry_chan_userd_target_vid_mem_v() (0x00000000U) +#define ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v() (0x00000001U) +#define ram_rl_entry_chan_userd_target_sys_mem_coh_v() (0x00000002U) +#define ram_rl_entry_chan_userd_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_rl_entry_chan_userd_ptr_lo_f(v) (((v)&0xffffffU) << 8U) +#define ram_rl_entry_chan_userd_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_inst_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_rl_entry_chan_inst_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_rl_entry_tsg_timeslice_scale_f(v) (((v)&0xfU) << 16U) +#define ram_rl_entry_tsg_timeslice_scale_v(r) (((r) >> 16U) & 0xfU) +#define ram_rl_entry_tsg_timeslice_scale_3_v() (0x00000003U) +#define ram_rl_entry_tsg_timeslice_timeout_f(v) (((v)&0xffU) << 24U) +#define ram_rl_entry_tsg_timeslice_timeout_v(r) (((r) >> 24U) & 0xffU) +#define ram_rl_entry_tsg_timeslice_timeout_128_v() (0x00000080U) +#define ram_rl_entry_tsg_length_f(v) (((v)&0xffU) << 0U) +#define ram_rl_entry_tsg_length_init_v() (0x00000000U) +#define ram_rl_entry_tsg_length_min_v() (0x00000001U) +#define ram_rl_entry_tsg_length_max_v() (0x00000080U) +#define ram_rl_entry_tsg_tsgid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_userd_ptr_align_shift_v() (0x00000008U) +#define ram_rl_entry_chan_userd_align_shift_v() (0x00000008U) +#define ram_rl_entry_chan_inst_ptr_align_shift_v() (0x0000000cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index 9d5d9bef0..4c7ab80a7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,432 +59,116 @@ #include #include -static inline u32 therm_use_a_r(void) -{ - return 0x00020798U; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2U; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4U; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) -{ - return (v & 0x3U) << 30U; -} -static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) -{ - return 0x00000001U; -} -static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) -{ - return 0x00000002U; -} -static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) -{ - return 0x00000003U; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_grad_step_duration_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 therm_config2_grad_step_duration_m(void) -{ - return U32(0xfU) << 8U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return U32(0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) -{ - return 0x200U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return U32(0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) -{ - return 0x2000U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) -{ - return 0x40000U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return U32(0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) -{ - return 0x0U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_fecs_idle_filter_value__prod_f(void) -{ - return 0x0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) -{ - return 0x0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_clk_slowdown_2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000201a0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_select_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_type_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_type_v(u32 r) -{ - return (r >> 4U) & 0x7U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_a_type_never_f(void) -{ - return 0x40U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_b_type_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_b_type_v(u32 r) -{ - return (r >> 12U) & 0x7U; -} -static inline u32 therm_clk_slowdown_2_idle_condition_b_type_never_f(void) -{ - return 0x4000U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by16_f(void) -{ - return 0x1eU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f(void) -{ - return 0x3eU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return U32(0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return U32(0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return U32(0x3fU) << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} +#define therm_use_a_r() (0x00020798U) +#define therm_use_a_ext_therm_0_enable_f() (0x1U) +#define therm_use_a_ext_therm_1_enable_f() (0x2U) +#define therm_use_a_ext_therm_2_enable_f() (0x4U) +#define therm_evt_ext_therm_0_r() (0x00020700U) +#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 24U) +#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000001U) +#define therm_evt_ext_therm_0_mode_f(v) (((v)&0x3U) << 30U) +#define therm_evt_ext_therm_0_mode_normal_v() (0x00000000U) +#define therm_evt_ext_therm_0_mode_inverted_v() (0x00000001U) +#define therm_evt_ext_therm_0_mode_forced_v() (0x00000002U) +#define therm_evt_ext_therm_0_mode_cleared_v() (0x00000003U) +#define therm_evt_ext_therm_1_r() (0x00020704U) +#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 24U) +#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000002U) +#define therm_evt_ext_therm_1_mode_f(v) (((v)&0x3U) << 30U) +#define therm_evt_ext_therm_1_mode_normal_v() (0x00000000U) +#define therm_evt_ext_therm_1_mode_inverted_v() (0x00000001U) +#define therm_evt_ext_therm_1_mode_forced_v() (0x00000002U) +#define therm_evt_ext_therm_1_mode_cleared_v() (0x00000003U) +#define therm_evt_ext_therm_2_r() (0x00020708U) +#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 24U) +#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000003U) +#define therm_evt_ext_therm_2_mode_f(v) (((v)&0x3U) << 30U) +#define therm_evt_ext_therm_2_mode_normal_v() (0x00000000U) +#define therm_evt_ext_therm_2_mode_inverted_v() (0x00000001U) +#define therm_evt_ext_therm_2_mode_forced_v() (0x00000002U) +#define therm_evt_ext_therm_2_mode_cleared_v() (0x00000003U) +#define therm_weight_1_r() (0x00020024U) +#define therm_config1_r() (0x00020050U) +#define therm_config2_r() (0x00020130U) +#define therm_config2_grad_step_duration_f(v) (((v)&0xfU) << 8U) +#define therm_config2_grad_step_duration_m() (U32(0xfU) << 8U) +#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) +#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) +#define therm_gate_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) +#define therm_gate_ctrl_eng_clk_run_f() (0x0U) +#define therm_gate_ctrl_eng_clk_auto_f() (0x1U) +#define therm_gate_ctrl_eng_clk_stop_f() (0x2U) +#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) +#define therm_gate_ctrl_blk_clk_run_f() (0x0U) +#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) +#define therm_gate_ctrl_idle_holdoff_m() (U32(0x1U) << 4U) +#define therm_gate_ctrl_idle_holdoff_off_f() (0x0U) +#define therm_gate_ctrl_idle_holdoff_on_f() (0x10U) +#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp__prod_f() (0x200U) +#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant__prod_f() (0x2000U) +#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before__prod_f() (0x40000U) +#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after__prod_f() (0x0U) +#define therm_fecs_idle_filter_r() (0x00020288U) +#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_fecs_idle_filter_value__prod_f() (0x0U) +#define therm_hubmmu_idle_filter_r() (0x0002028cU) +#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_hubmmu_idle_filter_value__prod_f() (0x0U) +#define therm_clk_slowdown_r(i)\ + (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) +#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) +#define therm_clk_slowdown_2_r(i)\ + (nvgpu_safe_add_u32(0x000201a0U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_slowdown_2_idle_condition_a_select_f(v) (((v)&0xfU) << 0U) +#define therm_clk_slowdown_2_idle_condition_a_type_f(v) (((v)&0x7U) << 4U) +#define therm_clk_slowdown_2_idle_condition_a_type_v(r) (((r) >> 4U) & 0x7U) +#define therm_clk_slowdown_2_idle_condition_a_type_never_f() (0x40U) +#define therm_clk_slowdown_2_idle_condition_b_type_f(v) (((v)&0x7U) << 12U) +#define therm_clk_slowdown_2_idle_condition_b_type_v(r) (((r) >> 12U) & 0x7U) +#define therm_clk_slowdown_2_idle_condition_b_type_never_f() (0x4000U) +#define therm_grad_stepping_table_r(i)\ + (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1_f() (0x0U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by16_f() (0x1eU) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by32_f() (0x3eU) +#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) +#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) +#define therm_grad_stepping0_r() (0x000202c0U) +#define therm_grad_stepping0_feature_s() (1U) +#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) +#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) +#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) +#define therm_grad_stepping0_feature_enable_f() (0x1U) +#define therm_grad_stepping1_r() (0x000202c4U) +#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) +#define therm_clk_timing_r(i)\ + (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h index 0f659405d..74784cece 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,72 +59,21 @@ #include #include -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) -{ - return (r >> 2U) & 0x3fffffU; -} -static inline u32 timer_pri_timeout_save_0_write_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} +#define timer_pri_timeout_r() (0x00009080U) +#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) +#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) +#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) +#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) +#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) +#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) +#define timer_pri_timeout_en_en_disabled_f() (0x0U) +#define timer_pri_timeout_save_0_r() (0x00009084U) +#define timer_pri_timeout_save_0_fecs_tgt_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_save_0_addr_v(r) (((r) >> 2U) & 0x3fffffU) +#define timer_pri_timeout_save_0_write_v(r) (((r) >> 1U) & 0x1U) +#define timer_pri_timeout_save_1_r() (0x00009088U) +#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU) +#define timer_time_0_r() (0x00009400U) +#define timer_time_1_r() (0x00009410U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index 31bec9502..279db5d2f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,200 +59,54 @@ #include #include -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_num_ces_r(void) -{ - return 0x00022444U; -} -static inline u32 top_num_ces_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_chain_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_engine_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_runlist_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_intr_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_reset_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x7fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} +#define top_num_gpcs_r() (0x00022430U) +#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_tpc_per_gpc_r() (0x00022434U) +#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbps_r() (0x00022438U) +#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_ltc_per_fbp_r() (0x00022450U) +#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_slices_per_ltc_r() (0x0002245cU) +#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_ltcs_r() (0x00022454U) +#define top_num_ces_r() (0x00022444U) +#define top_num_ces_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_device_info_r(i)\ + (nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U))) +#define top_device_info__size_1_v() (0x00000040U) +#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U) +#define top_device_info_chain_enable_v() (0x00000001U) +#define top_device_info_chain_disable_v() (0x00000000U) +#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU) +#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU) +#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU) +#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU) +#define top_device_info_type_enum_graphics_v() (0x00000000U) +#define top_device_info_type_enum_graphics_f() (0x0U) +#define top_device_info_type_enum_copy2_v() (0x00000003U) +#define top_device_info_type_enum_copy2_f() (0xcU) +#define top_device_info_type_enum_lce_v() (0x00000013U) +#define top_device_info_type_enum_lce_f() (0x4cU) +#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U) +#define top_device_info_engine_valid_v() (0x00000001U) +#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U) +#define top_device_info_runlist_valid_v() (0x00000001U) +#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U) +#define top_device_info_intr_valid_v() (0x00000001U) +#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_reset_valid_v() (0x00000001U) +#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) +#define top_device_info_entry_not_valid_v() (0x00000000U) +#define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_data_v() (0x00000001U) +#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U) +#define top_device_info_data_type_enum2_v() (0x00000000U) +#define top_device_info_data_inst_id_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0xfffU) +#define top_device_info_data_pri_base_align_v() (0x0000000cU) +#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x7fU) +#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_data_fault_id_valid_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_bus_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_bus_tu104.h index 8ce129481..6f1fe0444 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_bus_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_bus_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,188 +59,51 @@ #include #include -static inline u32 bus_sw_scratch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001400U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700U; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000U; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000U; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010U; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704U; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714U; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000U; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710U; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2U; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4U; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8U; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100U; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140U; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return U32(0x1U) << 3U; -} +#define bus_sw_scratch_r(i)\ + (nvgpu_safe_add_u32(0x00001400U, nvgpu_safe_mult_u32((i), 4U))) +#define bus_bar0_window_r() (0x00001700U) +#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) +#define bus_bar0_window_target_vid_mem_f() (0x0U) +#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) +#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) +#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) +#define bus_bar1_block_r() (0x00001704U) +#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar1_block_target_vid_mem_f() (0x0U) +#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar1_block_mode_virtual_f() (0x80000000U) +#define bus_bar2_block_r() (0x00001714U) +#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define bus_bar2_block_target_vid_mem_f() (0x0U) +#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) +#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) +#define bus_bar2_block_mode_virtual_f() (0x80000000U) +#define bus_bar1_block_ptr_shift_v() (0x0000000cU) +#define bus_bar2_block_ptr_shift_v() (0x0000000cU) +#define bus_bind_status_r() (0x00001710U) +#define bus_bind_status_bar1_pending_v(r) (((r) >> 0U) & 0x1U) +#define bus_bind_status_bar1_pending_empty_f() (0x0U) +#define bus_bind_status_bar1_pending_busy_f() (0x1U) +#define bus_bind_status_bar1_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define bus_bind_status_bar1_outstanding_false_f() (0x0U) +#define bus_bind_status_bar1_outstanding_true_f() (0x2U) +#define bus_bind_status_bar2_pending_v(r) (((r) >> 2U) & 0x1U) +#define bus_bind_status_bar2_pending_empty_v() (0x00000000U) +#define bus_bind_status_bar2_pending_empty_f() (0x0U) +#define bus_bind_status_bar2_pending_busy_v() (0x00000001U) +#define bus_bind_status_bar2_pending_busy_f() (0x4U) +#define bus_bind_status_bar2_outstanding_v(r) (((r) >> 3U) & 0x1U) +#define bus_bind_status_bar2_outstanding_false_v() (0x00000000U) +#define bus_bind_status_bar2_outstanding_false_f() (0x0U) +#define bus_bind_status_bar2_outstanding_true_v() (0x00000001U) +#define bus_bind_status_bar2_outstanding_true_f() (0x8U) +#define bus_intr_0_r() (0x00001100U) +#define bus_intr_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_0_pri_timeout_m() (U32(0x1U) << 3U) +#define bus_intr_en_0_r() (0x00001140U) +#define bus_intr_en_0_pri_squash_m() (U32(0x1U) << 1U) +#define bus_intr_en_0_pri_fecserr_m() (U32(0x1U) << 2U) +#define bus_intr_en_0_pri_timeout_m() (U32(0x1U) << 3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ccsr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ccsr_tu104.h index 23452bdaf..5007da17b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ccsr_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ccsr_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,172 +59,48 @@ #include #include -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0U; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00001000U; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ccsr_channel_enable_in_use_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400U; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800U; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ccsr_channel_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 ccsr_channel_status_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) -{ - return 0x00000002U; -} -static inline u32 ccsr_channel_status_pending_acquire_v(void) -{ - return 0x00000003U; -} -static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) -{ - return 0x00000004U; -} -static inline u32 ccsr_channel_status_on_pbdma_v(void) -{ - return 0x00000005U; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_v(void) -{ - return 0x00000006U; -} -static inline u32 ccsr_channel_status_on_eng_v(void) -{ - return 0x00000007U; -} -static inline u32 ccsr_channel_status_on_eng_pending_acquire_v(void) -{ - return 0x00000008U; -} -static inline u32 ccsr_channel_status_on_eng_pending_v(void) -{ - return 0x00000009U; -} -static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) -{ - return 0x0000000aU; -} -static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) -{ - return 0x0000000bU; -} -static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) -{ - return 0x0000000cU; -} -static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) -{ - return 0x0000000dU; -} -static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) -{ - return 0x0000000eU; -} -static inline u32 ccsr_channel_next_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ccsr_channel_next_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_force_ctx_reload_true_f(void) -{ - return 0x100U; -} -static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) -{ - return 0x400000U; -} -static inline u32 ccsr_channel_eng_faulted_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 ccsr_channel_eng_faulted_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 ccsr_channel_eng_faulted_reset_f(void) -{ - return 0x800000U; -} -static inline u32 ccsr_channel_eng_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ccsr_channel_busy_true_v(void) -{ - return 0x00000001U; -} +#define ccsr_channel_inst_r(i)\ + (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel_inst__size_1_v() (0x00001000U) +#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define ccsr_channel_inst_target_vid_mem_f() (0x0U) +#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) +#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) +#define ccsr_channel_inst_bind_false_f() (0x0U) +#define ccsr_channel_inst_bind_true_f() (0x80000000U) +#define ccsr_channel_r(i)\ + (nvgpu_safe_add_u32(0x00800004U, nvgpu_safe_mult_u32((i), 8U))) +#define ccsr_channel__size_1_v() (0x00001000U) +#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) +#define ccsr_channel_enable_in_use_v() (0x00000001U) +#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) +#define ccsr_channel_enable_set_true_f() (0x400U) +#define ccsr_channel_enable_clr_true_f() (0x800U) +#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) +#define ccsr_channel_status_idle_v() (0x00000000U) +#define ccsr_channel_status_pending_v() (0x00000001U) +#define ccsr_channel_status_pending_ctx_reload_v() (0x00000002U) +#define ccsr_channel_status_pending_acquire_v() (0x00000003U) +#define ccsr_channel_status_pending_acq_ctx_reload_v() (0x00000004U) +#define ccsr_channel_status_on_pbdma_v() (0x00000005U) +#define ccsr_channel_status_on_pbdma_and_eng_v() (0x00000006U) +#define ccsr_channel_status_on_eng_v() (0x00000007U) +#define ccsr_channel_status_on_eng_pending_acquire_v() (0x00000008U) +#define ccsr_channel_status_on_eng_pending_v() (0x00000009U) +#define ccsr_channel_status_on_pbdma_ctx_reload_v() (0x0000000aU) +#define ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v() (0x0000000bU) +#define ccsr_channel_status_on_eng_ctx_reload_v() (0x0000000cU) +#define ccsr_channel_status_on_eng_pending_ctx_reload_v() (0x0000000dU) +#define ccsr_channel_status_on_eng_pending_acq_ctx_reload_v() (0x0000000eU) +#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) +#define ccsr_channel_next_true_v() (0x00000001U) +#define ccsr_channel_force_ctx_reload_true_f() (0x100U) +#define ccsr_channel_pbdma_faulted_f(v) (((v)&0x1U) << 22U) +#define ccsr_channel_pbdma_faulted_reset_f() (0x400000U) +#define ccsr_channel_eng_faulted_f(v) (((v)&0x1U) << 23U) +#define ccsr_channel_eng_faulted_v(r) (((r) >> 23U) & 0x1U) +#define ccsr_channel_eng_faulted_reset_f() (0x800000U) +#define ccsr_channel_eng_faulted_true_v() (0x00000001U) +#define ccsr_channel_busy_v(r) (((r) >> 28U) & 0x1U) +#define ccsr_channel_busy_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h index 7d9cd608e..29ecab318 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,52 +59,17 @@ #include #include -static inline u32 ce_intr_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32(i, 128U)); -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1U; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2U; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4U; -} -static inline u32 ce_intr_status_invalid_config_pending_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_invalid_config_reset_f(void) -{ - return 0x8U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) -{ - return 0x10U; -} -static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) -{ - return 0x10U; -} -static inline u32 ce_pce_map_r(void) -{ - return 0x00104028U; -} +#define ce_intr_status_r(i)\ + (nvgpu_safe_add_u32(0x00104410U, nvgpu_safe_mult_u32((i), 128U))) +#define ce_intr_status_blockpipe_pending_f() (0x1U) +#define ce_intr_status_blockpipe_reset_f() (0x1U) +#define ce_intr_status_nonblockpipe_pending_f() (0x2U) +#define ce_intr_status_nonblockpipe_reset_f() (0x2U) +#define ce_intr_status_launcherr_pending_f() (0x4U) +#define ce_intr_status_launcherr_reset_f() (0x4U) +#define ce_intr_status_invalid_config_pending_f() (0x8U) +#define ce_intr_status_invalid_config_reset_f() (0x8U) +#define ce_intr_status_mthd_buffer_fault_pending_f() (0x10U) +#define ce_intr_status_mthd_buffer_fault_reset_f() (0x10U) +#define ce_pce_map_r() (0x00104028U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctrl_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctrl_tu104.h index 4dde676ff..5baa3d12f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctrl_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctrl_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,14 @@ #include #include -static inline u32 ctrl_doorbell_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00b64000U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 ctrl_doorbell_vector_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ctrl_doorbell_runlist_id_f(u32 v) -{ - return (v & 0x7fU) << 16U; -} -static inline u32 ctrl_virtual_channel_cfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00b65000U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ctrl_virtual_channel_cfg_pending_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 ctrl_legacy_engine_nonstall_intr_base_vectorid_r(void) -{ - return 0x00b66884U; -} -static inline u32 ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} +#define ctrl_doorbell_r(i)\ + (nvgpu_safe_add_u32(0x00b64000U, nvgpu_safe_mult_u32((i), 8U))) +#define ctrl_doorbell_vector_f(v) (((v)&0xfffU) << 0U) +#define ctrl_doorbell_runlist_id_f(v) (((v)&0x7fU) << 16U) +#define ctrl_virtual_channel_cfg_r(i)\ + (nvgpu_safe_add_u32(0x00b65000U, nvgpu_safe_mult_u32((i), 4U))) +#define ctrl_virtual_channel_cfg_pending_enable_true_f() (0x80000000U) +#define ctrl_legacy_engine_nonstall_intr_base_vectorid_r() (0x00b66884U) +#define ctrl_legacy_engine_nonstall_intr_base_vectorid_vector_v(r)\ + (((r) >> 0U) & 0xfffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctxsw_prog_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctxsw_prog_tu104.h index 8720824a7..227116e50 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctxsw_prog_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ctxsw_prog_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,396 +59,117 @@ #include #include -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_gpccs_header_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) -{ - return 0x00000008U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) -{ - return 0x00000011U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) -{ - return 0x00000012U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) -{ - return 0x00000021U; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010U; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014U; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018U; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001cU; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001U; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020U; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8U; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002cU; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0U; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4U; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8U; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dcU; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) -{ - return 0x00000060U; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) -{ - return 0x00000094U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) -{ - return 0x00000064U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) -{ - return 0x00000070U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) -{ - return 0x00000074U; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) -{ - return 0x00000078U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) -{ - return 0x0000007cU; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0deU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000cU; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) -{ - return 0x000000b8U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) -{ - return 0x000000bcU; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) -{ - return 0x000000c0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) -{ - return 0x000000c4U; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) -{ - return 0x000000c8U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) -{ - return 0x000000ccU; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4U; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8U; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fcU; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becabU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ecU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100U; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000U; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4U; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8U; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003cU; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1U; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2U; -} +#define ctxsw_prog_fecs_header_v() (0x00000100U) +#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) +#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) +#define ctxsw_prog_main_image_ctl_o() (0x0000000cU) +#define ctxsw_prog_main_image_ctl_type_f(v) (((v)&0x3fU) << 0U) +#define ctxsw_prog_main_image_ctl_type_undefined_v() (0x00000000U) +#define ctxsw_prog_main_image_ctl_type_opengl_v() (0x00000008U) +#define ctxsw_prog_main_image_ctl_type_dx9_v() (0x00000010U) +#define ctxsw_prog_main_image_ctl_type_dx10_v() (0x00000011U) +#define ctxsw_prog_main_image_ctl_type_dx11_v() (0x00000012U) +#define ctxsw_prog_main_image_ctl_type_compute_v() (0x00000020U) +#define ctxsw_prog_main_image_ctl_type_per_veid_header_v() (0x00000021U) +#define ctxsw_prog_main_image_patch_count_o() (0x00000010U) +#define ctxsw_prog_main_image_context_id_o() (0x000000f0U) +#define ctxsw_prog_main_image_patch_adr_lo_o() (0x00000014U) +#define ctxsw_prog_main_image_patch_adr_hi_o() (0x00000018U) +#define ctxsw_prog_main_image_zcull_o() (0x0000001cU) +#define ctxsw_prog_main_image_zcull_mode_no_ctxsw_v() (0x00000001U) +#define ctxsw_prog_main_image_zcull_mode_separate_buffer_v() (0x00000002U) +#define ctxsw_prog_main_image_zcull_ptr_o() (0x00000020U) +#define ctxsw_prog_main_image_pm_o() (0x00000028U) +#define ctxsw_prog_main_image_pm_mode_m() (U32(0x7U) << 0U) +#define ctxsw_prog_main_image_pm_mode_ctxsw_f() (0x1U) +#define ctxsw_prog_main_image_pm_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f() (0x2U) +#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) +#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) +#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) +#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) +#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) +#define ctxsw_prog_main_image_num_wfi_save_ops_o() (0x000000d0U) +#define ctxsw_prog_main_image_num_cta_save_ops_o() (0x000000d4U) +#define ctxsw_prog_main_image_num_gfxp_save_ops_o() (0x000000d8U) +#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU) +#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) +#define ctxsw_prog_main_image_zcull_ptr_hi_o() (0x00000060U) +#define ctxsw_prog_main_image_zcull_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_pm_ptr_hi_o() (0x00000094U) +#define ctxsw_prog_main_image_full_preemption_ptr_hi_o() (0x00000064U) +#define ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) +#define ctxsw_prog_main_image_full_preemption_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o() (0x00000070U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_o() (0x00000074U) +#define ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_context_buffer_ptr_hi_o() (0x00000078U) +#define ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_context_buffer_ptr_o() (0x0000007cU) +#define ctxsw_prog_main_image_context_buffer_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) +#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) +#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) +#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_image_global_cb_ptr_o() (0x000000b8U) +#define ctxsw_prog_main_image_global_cb_ptr_v_f(v) (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_global_cb_ptr_hi_o() (0x000000bcU) +#define ctxsw_prog_main_image_global_cb_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_o() (0x000000c0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_v_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_global_pagepool_ptr_hi_o() (0x000000c4U) +#define ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(v)\ + (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_main_image_control_block_ptr_o() (0x000000c8U) +#define ctxsw_prog_main_image_control_block_ptr_v_f(v) (((v)&0xffffffffU) << 0U) +#define ctxsw_prog_main_image_control_block_ptr_hi_o() (0x000000ccU) +#define ctxsw_prog_main_image_control_block_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) +#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) +#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) +#define ctxsw_prog_local_image_num_tpcs_o() (0x000000f8U) +#define ctxsw_prog_local_magic_value_o() (0x000000fcU) +#define ctxsw_prog_local_magic_value_v_value_v() (0xad0becabU) +#define ctxsw_prog_main_extended_buffer_ctl_o() (0x000000ecU) +#define ctxsw_prog_main_extended_buffer_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) +#define ctxsw_prog_main_extended_buffer_ctl_size_v(r) (((r) >> 16U) & 0xffU) +#define ctxsw_prog_extended_buffer_segments_size_in_bytes_v() (0x00000100U) +#define ctxsw_prog_extended_marker_size_in_bytes_v() (0x00000004U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v()\ + (0x00000000U) +#define ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v()\ + (0x00000002U) +#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ + (((r) >> 0U) & 0x3U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f() (0x0U) +#define ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f() (0x2U) +#define ctxsw_prog_main_image_priv_access_map_addr_lo_o() (0x000000a4U) +#define ctxsw_prog_main_image_priv_access_map_addr_hi_o() (0x000000a8U) +#define ctxsw_prog_main_image_misc_options_o() (0x0000003cU) +#define ctxsw_prog_main_image_misc_options_verif_features_m() (U32(0x1U) << 3U) +#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) +#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ + (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) +#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ + (((v)&0x3U) << 0U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) +#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_falcon_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_falcon_tu104.h index b63bb6f30..c9947211f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_falcon_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_falcon_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,548 +59,145 @@ #include #include -static inline u32 falcon_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 falcon_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 falcon_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 falcon_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 falcon_falcon_irqmode_r(void) -{ - return 0x0000000cU; -} -static inline u32 falcon_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_r(void) -{ - return 0x00000014U; -} -static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 falcon_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 falcon_falcon_curctx_r(void) -{ - return 0x00000050U; -} -static inline u32 falcon_falcon_nxtctx_r(void) -{ - return 0x00000054U; -} -static inline u32 falcon_falcon_mailbox0_r(void) -{ - return 0x00000040U; -} -static inline u32 falcon_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 falcon_falcon_itfen_r(void) -{ - return 0x00000048U; -} -static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 falcon_falcon_idlestate_r(void) -{ - return 0x0000004cU; -} -static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 falcon_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 falcon_falcon_engctl_r(void) -{ - return 0x000000a4U; -} -static inline u32 falcon_falcon_cpuctl_r(void) -{ - return 0x00000100U; -} -static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_stopped_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 falcon_falcon_cpuctl_alias_r(void) -{ - return 0x00000130U; -} -static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 falcon_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_imemc_secure_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 falcon_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 falcon_falcon_sctl_r(void) -{ - return 0x00000240U; -} -static inline u32 falcon_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 falcon_falcon_bootvec_r(void) -{ - return 0x00000104U; -} -static inline u32 falcon_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 falcon_falcon_dmactl_r(void) -{ - return 0x0000010cU; -} -static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 falcon_falcon_hwcfg_r(void) -{ - return 0x00000108U; -} -static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 falcon_falcon_dmatrfbase_r(void) -{ - return 0x00000110U; -} -static inline u32 falcon_falcon_dmatrfbase1_r(void) -{ - return 0x00000128U; -} -static inline u32 falcon_falcon_dmatrfmoffs_r(void) -{ - return 0x00000114U; -} -static inline u32 falcon_falcon_dmatrfcmd_r(void) -{ - return 0x00000118U; -} -static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 falcon_falcon_dmatrffboffs_r(void) -{ - return 0x0000011cU; -} -static inline u32 falcon_falcon_imctl_debug_r(void) -{ - return 0x0000015cU; -} -static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 falcon_falcon_imstat_r(void) -{ - return 0x00000144U; -} -static inline u32 falcon_falcon_traceidx_r(void) -{ - return 0x00000148U; -} -static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 falcon_falcon_traceidx_idx_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 falcon_falcon_tracepc_r(void) -{ - return 0x0000014cU; -} -static inline u32 falcon_falcon_tracepc_pc_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 falcon_falcon_exterraddr_r(void) -{ - return 0x00000168U; -} -static inline u32 falcon_falcon_exterrstat_r(void) -{ - return 0x0000016cU; -} -static inline u32 falcon_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 falcon_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 falcon_falcon_icd_cmd_r(void) -{ - return 0x00000200U; -} -static inline u32 falcon_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 falcon_falcon_icd_rdata_r(void) -{ - return 0x0000020cU; -} -static inline u32 falcon_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 falcon_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 falcon_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 falcon_falcon_debug1_r(void) -{ - return 0x00000090U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 falcon_falcon_debuginfo_r(void) -{ - return 0x00000094U; -} +#define falcon_falcon_irqsset_r() (0x00000000U) +#define falcon_falcon_irqsset_swgen0_set_f() (0x40U) +#define falcon_falcon_irqsclr_r() (0x00000004U) +#define falcon_falcon_irqstat_r() (0x00000008U) +#define falcon_falcon_irqstat_halt_true_f() (0x10U) +#define falcon_falcon_irqstat_exterr_true_f() (0x20U) +#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) +#define falcon_falcon_irqmode_r() (0x0000000cU) +#define falcon_falcon_irqmset_r() (0x00000010U) +#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_r() (0x00000014U) +#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqmask_r() (0x00000018U) +#define falcon_falcon_irqdest_r() (0x0000001cU) +#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define falcon_falcon_curctx_r() (0x00000050U) +#define falcon_falcon_nxtctx_r() (0x00000054U) +#define falcon_falcon_mailbox0_r() (0x00000040U) +#define falcon_falcon_mailbox1_r() (0x00000044U) +#define falcon_falcon_itfen_r() (0x00000048U) +#define falcon_falcon_itfen_ctxen_enable_f() (0x1U) +#define falcon_falcon_idlestate_r() (0x0000004cU) +#define falcon_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define falcon_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define falcon_falcon_os_r() (0x00000080U) +#define falcon_falcon_engctl_r() (0x000000a4U) +#define falcon_falcon_cpuctl_r() (0x00000100U) +#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) +#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) +#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define falcon_falcon_cpuctl_alias_r() (0x00000130U) +#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define falcon_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) +#define falcon_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) +#define falcon_falcon_sctl_r() (0x00000240U) +#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define falcon_falcon_bootvec_r() (0x00000104U) +#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define falcon_falcon_dmactl_r() (0x0000010cU) +#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define falcon_falcon_hwcfg_r() (0x00000108U) +#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define falcon_falcon_dmatrfbase_r() (0x00000110U) +#define falcon_falcon_dmatrfbase1_r() (0x00000128U) +#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) +#define falcon_falcon_dmatrfcmd_r() (0x00000118U) +#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) +#define falcon_falcon_imctl_debug_r() (0x0000015cU) +#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) +#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) +#define falcon_falcon_imstat_r() (0x00000144U) +#define falcon_falcon_traceidx_r() (0x00000148U) +#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) +#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) +#define falcon_falcon_tracepc_r() (0x0000014cU) +#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) +#define falcon_falcon_exterraddr_r() (0x0010a168U) +#define falcon_falcon_exterrstat_r() (0x0010a16cU) +#define falcon_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define falcon_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) +#define falcon_falcon_icd_cmd_r() (0x00000200U) +#define falcon_falcon_icd_cmd_opc_s() (4U) +#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define falcon_falcon_icd_rdata_r() (0x0000020cU) +#define falcon_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define falcon_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) +#define falcon_falcon_debug1_r() (0x00000090U) +#define falcon_falcon_debug1_ctxsw_mode_s() (1U) +#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define falcon_falcon_debuginfo_r() (0x00000094U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h index af5ff2714..1cd24802d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,2260 +59,632 @@ #include #include -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return U32(0x1U) << (16U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void) -{ - return U32(0x1U) << 26U; -} -static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_bind_imb_r(void) -{ - return 0x00100cacU; -} -static inline u32 fb_mmu_bind_imb_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_bind_imb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_bind_imb_aperture_sys_mem_c_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_bind_imb_aperture_sys_mem_nc_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_bind_imb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_bind_imb_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_bind_r(void) -{ - return 0x00100cb0U; -} -static inline u32 fb_mmu_bind_engine_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_mmu_bind_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_r(void) -{ - return 0x001fac80U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v) -{ - return (v & 0x3U) << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r) -{ - return (r >> 24U) & 0x3U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f(void) -{ - return 0x0U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_hshub_num_active_ltcs_r(void) -{ - return 0x001fbc20U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i) -{ - return (v & 0x1U) << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i) -{ - return U32(0x1U) << (16U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i) -{ - return (r >> (16U + i*1U)) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i) -{ - return 0x1U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i) -{ - return 0x0U << (32U + i*1U); -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) -{ - return 0x0U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4U; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbcU; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return U32(0x7U) << 3U; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return U32(0x3U) << 7U; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7U) & 0x3U; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return U32(0x3fU) << 9U; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9U) & 0x3fU; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return U32(0x1fU) << 15U; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return U32(0x7U) << 24U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24U) & 0x7U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000U; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000U; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1U; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_invalidate_trigger_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8U; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2U; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100cccU; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000cU; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4U; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_r(void) -{ - return 0x00100e70U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e74U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e78U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_r(void) -{ - return 0x00100e7cU; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_status_r(void) -{ - return 0x00100e84U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) -{ - return 0x00100e88U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) -{ - return 0x00100e8cU; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_hubtlb_ecc_address_r(void) -{ - return 0x00100e90U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fillunit_ecc_status_r(void) -{ - return 0x00100e98U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) -{ - return 0x00100e9cU; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) -{ - return 0x00100ea0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_fillunit_ecc_address_r(void) -{ - return 0x00100ea4U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) -{ - return 32U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_niso_cfg1_r(void) -{ - return 0x00100c14U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_f(void) -{ - return 0x20000U; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10U; -} -static inline u32 fb_niso_intr_r(void) -{ - return 0x00100a20U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en_set__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100a34U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_niso_intr_en_clr__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 1U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) -{ - return (r >> 1U) & 0x3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x6U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_buffer_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) -{ - return U32(0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_buffer_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) -{ - return (r >> 0U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_addr_lo_r(void) -{ - return 0x00100e4cU; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x3U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_addr_hi_r(void) -{ - return 0x00100e50U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_inst_lo_r(void) -{ - return 0x00100e54U; -} -static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) -{ - return (r >> 12U) & 0xfffffU; -} -static inline u32 fb_mmu_fault_inst_hi_r(void) -{ - return 0x00100e58U; -} -static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 fb_mmu_fault_info_r(void) -{ - return 0x00100e5cU; -} -static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8U) & 0x7fU; -} -static inline u32 fb_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_mmu_fault_info_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fb_mmu_fault_status_r(void) -{ - return 0x00100e60U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) -{ - return 0x1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) -{ - return 0x2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) -{ - return 0x4U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) -{ - return 0x8U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) -{ - return 0x10U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) -{ - return 0x20U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) -{ - return 0x40U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) -{ - return 0x80U; -} -static inline u32 fb_mmu_fault_status_replayable_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fb_mmu_fault_status_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_set_f(void) -{ - return 0x100U; -} -static inline u32 fb_mmu_fault_status_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) -{ - return 0x200U; -} -static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_error_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) -{ - return 0x400U; -} -static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) -{ - return 0x800U; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) -{ - return 0x1000U; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) -{ - return 0x2000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) -{ - return 0x0U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) -{ - return U32(0x1U) << 14U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) -{ - return 0x4000U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) -{ - return 0x8000U; -} -static inline u32 fb_mmu_fault_status_busy_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 fb_mmu_fault_status_busy_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_busy_true_f(void) -{ - return 0x40000000U; -} -static inline u32 fb_mmu_fault_status_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 fb_mmu_fault_status_valid_set_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_set_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_fault_status_valid_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_fault_status_valid_clear_f(void) -{ - return 0x80000000U; -} -static inline u32 fb_mmu_local_memory_range_r(void) -{ - return 0x00100ce0U; -} -static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) -{ - return (r >> 4U) & 0x3fU; -} -static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fb_niso_scrub_status_r(void) -{ - return 0x00100b20U; -} -static inline u32 fb_niso_scrub_status_flag_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 fb_mmu_priv_level_mask_r(void) -{ - return 0x00100cdcU; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r) -{ - return (r >> 9U) & 0x1U; -} -static inline u32 fb_hshub_config0_r(void) -{ - return 0x001fbc00U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 fb_hshub_config0_peer_pcie_mask_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 fb_hshub_config1_r(void) -{ - return 0x001fbc04U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config1_peer_0_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config1_peer_1_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config1_peer_2_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config1_peer_3_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config2_r(void) -{ - return 0x001fbc08U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fb_hshub_config2_peer_4_nvlink_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 fb_hshub_config2_peer_5_nvlink_mask_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 fb_hshub_config2_peer_6_nvlink_mask_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 fb_hshub_config2_peer_7_nvlink_mask_v(u32 r) -{ - return (r >> 24U) & 0xffU; -} -static inline u32 fb_hshub_config6_r(void) -{ - return 0x001fbc18U; -} -static inline u32 fb_hshub_config7_r(void) -{ - return 0x001fbc1cU; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_r(void) -{ - return 0x001fbc50U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 fb_mmu_int_vector_info_fault_r(void) -{ - return 0x00100ee0U; -} -static inline u32 fb_mmu_int_vector_info_fault_vector_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_int_vector_ecc_error_r(void) -{ - return 0x00100edcU; -} -static inline u32 fb_mmu_int_vector_ecc_error_vector_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_int_vector_fault_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00100ee4U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fb_mmu_int_vector_fault_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fb_mmu_int_vector_fault_notify_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 fb_mmu_num_active_ltcs_r(void) -{ - return 0x00100ec0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 fb_mmu_cbc_base_r(void) -{ - return 0x00100ec4U; -} -static inline u32 fb_mmu_cbc_base_address_f(u32 v) -{ - return (v & 0x3ffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_top_r(void) -{ - return 0x00100ec8U; -} -static inline u32 fb_mmu_cbc_top_size_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 fb_mmu_cbc_top_size_v(u32 r) -{ - return (r >> 0U) & 0x7fffU; -} -static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 fb_mmu_cbc_max_r(void) -{ - return 0x00100eccU; -} -static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_max_comptagline_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} +#define fb_fbhub_num_active_ltcs_r() (0x00100800U) +#define fb_fbhub_num_active_ltcs_use_nvlink_f(v) (((v)&0xffU) << 16U) +#define fb_fbhub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U) +#define fb_fbhub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_f(v, i)\ + (((v) & 0x1) << (16U + i*1U)) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_m(i)\ + (U32(0x1U) << (16U + (i)*1U)) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_v(r, i)\ + (((r) >> (16U + i*1U)) & 0x1U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ + ((0x1U << (32U +((i)*1U)))) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) +#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(v) (((v)&0x1U) << 25U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f() (0x0U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v() (0x00000001U) +#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f() (0x2000000U) +#define fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m() (U32(0x1U) << 26U) +#define fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f() (0x0U) +#define fb_mmu_ctrl_r() (0x00100c80U) +#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) +#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) +#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) +#define fb_mmu_ctrl_atomic_capability_mode_f(v) (((v)&0x3U) << 24U) +#define fb_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define fb_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U) +#define fb_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U) +#define fb_mmu_ctrl_atomic_capability_mode_l2_f() (0x0U) +#define fb_mmu_ctrl_atomic_capability_mode_atomic_v() (0x00000001U) +#define fb_mmu_ctrl_atomic_capability_mode_atomic_f() (0x1000000U) +#define fb_mmu_ctrl_atomic_capability_mode_rmw_v() (0x00000002U) +#define fb_mmu_ctrl_atomic_capability_mode_rmw_f() (0x2000000U) +#define fb_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U) +#define fb_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U) +#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m() (U32(0x1U) << 27U) +#define fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f() (0x0U) +#define fb_mmu_bind_imb_r() (0x00100cacU) +#define fb_mmu_bind_imb_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_bind_imb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_bind_imb_aperture_sys_mem_c_f() (0x2U) +#define fb_mmu_bind_imb_aperture_sys_mem_nc_f() (0x3U) +#define fb_mmu_bind_imb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_bind_imb_addr_alignment_v() (0x0000000cU) +#define fb_mmu_bind_r() (0x00100cb0U) +#define fb_mmu_bind_engine_id_f(v) (((v)&0xffU) << 0U) +#define fb_mmu_bind_trigger_true_f() (0x80000000U) +#define fb_hsmmu_pri_mmu_ctrl_r() (0x001fac80U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(v) (((v)&0x3U) << 24U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f() (0x0U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v() (0x00000001U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f() (0x1000000U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v() (0x00000002U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f() (0x2000000U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U) +#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U) +#define fb_hshub_num_active_ltcs_r() (0x001fbc20U) +#define fb_hshub_num_active_ltcs_use_nvlink_f(v) (((v)&0xffU) << 16U) +#define fb_hshub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U) +#define fb_hshub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_f(v, i)\ + (((v) & 0x1) << (16U + i*1U)) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_m(i)\ + (U32(0x1U) << (16U + (i)*1U)) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_v(r, i)\ + (((r) >> (16U + i*1U)) & 0x1U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ + ((0x1U << (32U +((i)*1U)))) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) +#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ + ((0x0U << (32U +((i)*1U)))) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(v) (((v)&0x1U) << 25U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f() (0x0U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v() (0x00000001U) +#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f() (0x2000000U) +#define fb_priv_mmu_phy_secure_r() (0x00100ce4U) +#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) +#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) +#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) +#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_invalidate_r() (0x00100cbcU) +#define fb_mmu_invalidate_all_va_true_f() (0x1U) +#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) +#define fb_mmu_invalidate_hubtlb_only_s() (1U) +#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) +#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) +#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) +#define fb_mmu_invalidate_replay_s() (3U) +#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) +#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) +#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) +#define fb_mmu_invalidate_replay_none_f() (0x0U) +#define fb_mmu_invalidate_replay_start_f() (0x8U) +#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U) +#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) +#define fb_mmu_invalidate_sys_membar_s() (1U) +#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) +#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) +#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) +#define fb_mmu_invalidate_ack_s() (2U) +#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) +#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) +#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) +#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) +#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) +#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) +#define fb_mmu_invalidate_cancel_client_id_s() (6U) +#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) +#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) +#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) +#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) +#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) +#define fb_mmu_invalidate_cancel_client_type_s() (1U) +#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) +#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) +#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) +#define fb_mmu_invalidate_cancel_cache_level_s() (3U) +#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) +#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) +#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) +#define fb_mmu_invalidate_cancel_cache_level_pte_only_f() (0x1000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f() (0x2000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f() (0x3000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f() (0x4000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f() (0x5000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) +#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) +#define fb_mmu_invalidate_trigger_s() (1U) +#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) +#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_invalidate_trigger_true_v() (0x00000001U) +#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) +#define fb_mmu_debug_wr_r() (0x00100cc8U) +#define fb_mmu_debug_wr_aperture_s() (2U) +#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) +#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_wr_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_wr_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_wr_vol_false_f() (0x0U) +#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) +#define fb_mmu_debug_wr_vol_true_f() (0x4U) +#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_rd_r() (0x00100cccU) +#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) +#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) +#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) +#define fb_mmu_debug_rd_vol_false_f() (0x0U) +#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) +#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) +#define fb_mmu_debug_ctrl_r() (0x00100cc4U) +#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define fb_mmu_debug_ctrl_debug_m() (U32(0x1U) << 16U) +#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) +#define fb_mmu_l2tlb_ecc_status_r() (0x00100e70U) +#define fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()\ + (U32(0x1U) << 0U) +#define fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m()\ + (U32(0x1U) << 1U) +#define fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define fb_mmu_l2tlb_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_l2tlb_ecc_status_reset_clear_f() (0x40000000U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_r() (0x00100e74U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_s() (16U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_corrected_err_count_total_v(r) (((r) >> 0U) & 0xffffU) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_r() (0x00100e78U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s() (16U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_l2tlb_ecc_address_r() (0x00100e7cU) +#define fb_mmu_l2tlb_ecc_address_index_s() (32U) +#define fb_mmu_l2tlb_ecc_address_index_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_l2tlb_ecc_address_index_m() (U32(0xffffffffU) << 0U) +#define fb_mmu_l2tlb_ecc_address_index_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_hubtlb_ecc_status_r() (0x00100e84U) +#define fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m() (U32(0x1U) << 0U) +#define fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m() (U32(0x1U) << 1U) +#define fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define fb_mmu_hubtlb_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_hubtlb_ecc_status_reset_clear_f() (0x40000000U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_r() (0x00100e88U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_s() (16U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_corrected_err_count_total_v(r) (((r) >> 0U) & 0xffffU) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_r() (0x00100e8cU) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s() (16U) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_hubtlb_ecc_address_r() (0x00100e90U) +#define fb_mmu_hubtlb_ecc_address_index_s() (32U) +#define fb_mmu_hubtlb_ecc_address_index_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_hubtlb_ecc_address_index_m() (U32(0xffffffffU) << 0U) +#define fb_mmu_hubtlb_ecc_address_index_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fillunit_ecc_status_r() (0x00100e98U) +#define fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m() (U32(0x1U) << 0U) +#define fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m()\ + (U32(0x1U) << 1U) +#define fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m() (U32(0x1U) << 2U) +#define fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m()\ + (U32(0x1U) << 3U) +#define fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 16U) +#define fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m()\ + (U32(0x1U) << 18U) +#define fb_mmu_fillunit_ecc_status_reset_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fillunit_ecc_status_reset_clear_f() (0x40000000U) +#define fb_mmu_fillunit_ecc_corrected_err_count_r() (0x00100e9cU) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_s() (16U) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_f(v) (((v)&0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_r() (0x00100ea0U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_s() (16U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(v)\ + (((v)&0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_m() (U32(0xffffU) << 0U) +#define fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define fb_mmu_fillunit_ecc_address_r() (0x00100ea4U) +#define fb_mmu_fillunit_ecc_address_index_s() (32U) +#define fb_mmu_fillunit_ecc_address_index_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fillunit_ecc_address_index_m() (U32(0xffffffffU) << 0U) +#define fb_mmu_fillunit_ecc_address_index_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_niso_cfg1_r() (0x00100c14U) +#define fb_niso_cfg1_sysmem_nvlink_f(v) (((v)&0x1U) << 17U) +#define fb_niso_cfg1_sysmem_nvlink_m() (U32(0x1U) << 17U) +#define fb_niso_cfg1_sysmem_nvlink_v(r) (((r) >> 17U) & 0x1U) +#define fb_niso_cfg1_sysmem_nvlink_enabled_v() (0x00000001U) +#define fb_niso_cfg1_sysmem_nvlink_enabled_f() (0x20000U) +#define fb_niso_flush_sysmem_addr_r() (0x00100c10U) +#define fb_niso_intr_r() (0x00100a20U) +#define fb_niso_intr_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_hub_access_counter_notify_pending_f() (0x1U) +#define fb_niso_intr_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_hub_access_counter_error_pending_f() (0x2U) +#define fb_niso_intr_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_mmu_replayable_fault_notify_pending_f() (0x8000000U) +#define fb_niso_intr_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_mmu_replayable_fault_overflow_pending_f() (0x10000000U) +#define fb_niso_intr_mmu_nonreplayable_fault_notify_m() (U32(0x1U) << 29U) +#define fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() (0x20000000U) +#define fb_niso_intr_mmu_nonreplayable_fault_overflow_m() (U32(0x1U) << 30U) +#define fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f() (0x40000000U) +#define fb_niso_intr_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_mmu_other_fault_notify_pending_f() (0x80000000U) +#define fb_niso_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en__size_1_v() (0x00000002U) +#define fb_niso_intr_en_hub_access_counter_notify_f(v) (((v)&0x1U) << 0U) +#define fb_niso_intr_en_hub_access_counter_notify_enabled_f() (0x1U) +#define fb_niso_intr_en_hub_access_counter_error_f(v) (((v)&0x1U) << 1U) +#define fb_niso_intr_en_hub_access_counter_error_enabled_f() (0x2U) +#define fb_niso_intr_en_mmu_replayable_fault_notify_f(v) (((v)&0x1U) << 27U) +#define fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f() (0x8000000U) +#define fb_niso_intr_en_mmu_replayable_fault_overflow_f(v) (((v)&0x1U) << 28U) +#define fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f() (0x10000000U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(v) (((v)&0x1U) << 29U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f() (0x20000000U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(v)\ + (((v)&0x1U) << 30U) +#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f()\ + (0x40000000U) +#define fb_niso_intr_en_mmu_other_fault_notify_f(v) (((v)&0x1U) << 31U) +#define fb_niso_intr_en_mmu_other_fault_notify_enabled_f() (0x80000000U) +#define fb_niso_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en_set__size_1_v() (0x00000002U) +#define fb_niso_intr_en_set_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_en_set_hub_access_counter_notify_set_f() (0x1U) +#define fb_niso_intr_en_set_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_en_set_hub_access_counter_error_set_f() (0x2U) +#define fb_niso_intr_en_set_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f() (0x8000000U) +#define fb_niso_intr_en_set_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f() (0x10000000U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m()\ + (U32(0x1U) << 29U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f() (0x20000000U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m()\ + (U32(0x1U) << 30U) +#define fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f()\ + (0x40000000U) +#define fb_niso_intr_en_set_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_en_set_mmu_other_fault_notify_set_f() (0x80000000U) +#define fb_niso_intr_en_clr_r(i)\ + (nvgpu_safe_add_u32(0x00100a34U, nvgpu_safe_mult_u32((i), 4U))) +#define fb_niso_intr_en_clr__size_1_v() (0x00000002U) +#define fb_niso_intr_en_clr_hub_access_counter_notify_m() (U32(0x1U) << 0U) +#define fb_niso_intr_en_clr_hub_access_counter_notify_set_f() (0x1U) +#define fb_niso_intr_en_clr_hub_access_counter_error_m() (U32(0x1U) << 1U) +#define fb_niso_intr_en_clr_hub_access_counter_error_set_f() (0x2U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_notify_m() (U32(0x1U) << 27U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f() (0x8000000U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m() (U32(0x1U) << 28U) +#define fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f() (0x10000000U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m()\ + (U32(0x1U) << 29U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f() (0x20000000U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m()\ + (U32(0x1U) << 30U) +#define fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f()\ + (0x40000000U) +#define fb_niso_intr_en_clr_mmu_other_fault_notify_m() (U32(0x1U) << 31U) +#define fb_niso_intr_en_clr_mmu_other_fault_notify_set_f() (0x80000000U) +#define fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v() (0x00000000U) +#define fb_niso_intr_en_clr_mmu_replay_fault_buffer_v() (0x00000001U) +#define fb_mmu_fault_buffer_lo_r(i)\ + (nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_lo__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_lo_addr_mode_f(v) (((v)&0x1U) << 0U) +#define fb_mmu_fault_buffer_lo_addr_mode_v(r) (((r) >> 0U) & 0x1U) +#define fb_mmu_fault_buffer_lo_addr_mode_virtual_v() (0x00000000U) +#define fb_mmu_fault_buffer_lo_addr_mode_virtual_f() (0x0U) +#define fb_mmu_fault_buffer_lo_addr_mode_physical_v() (0x00000001U) +#define fb_mmu_fault_buffer_lo_addr_mode_physical_f() (0x1U) +#define fb_mmu_fault_buffer_lo_phys_aperture_f(v) (((v)&0x3U) << 1U) +#define fb_mmu_fault_buffer_lo_phys_aperture_v(r) (((r) >> 1U) & 0x3U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f() (0x4U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f() (0x6U) +#define fb_mmu_fault_buffer_lo_phys_vol_f(v) (((v)&0x1U) << 3U) +#define fb_mmu_fault_buffer_lo_phys_vol_v(r) (((r) >> 3U) & 0x1U) +#define fb_mmu_fault_buffer_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_buffer_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_buffer_hi_r(i)\ + (nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_hi__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_hi_addr_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fault_buffer_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_buffer_get_r(i)\ + (nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_get__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_get_ptr_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_get_ptr_m() (U32(0xfffffU) << 0U) +#define fb_mmu_fault_buffer_get_ptr_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_get_getptr_corrupted_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_m() (U32(0x1U) << 30U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_v() (0x00000001U) +#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_f() (0x40000000U) +#define fb_mmu_fault_buffer_get_overflow_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_get_overflow_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_buffer_get_overflow_clear_v() (0x00000001U) +#define fb_mmu_fault_buffer_get_overflow_clear_f() (0x80000000U) +#define fb_mmu_fault_buffer_put_r(i)\ + (nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_put__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_put_ptr_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_put_ptr_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_put_getptr_corrupted_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_f() (0x40000000U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_no_v() (0x00000000U) +#define fb_mmu_fault_buffer_put_getptr_corrupted_no_f() (0x0U) +#define fb_mmu_fault_buffer_put_overflow_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_put_overflow_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_buffer_put_overflow_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_put_overflow_yes_f() (0x80000000U) +#define fb_mmu_fault_buffer_size_r(i)\ + (nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32((i), 20U))) +#define fb_mmu_fault_buffer_size__size_1_v() (0x00000002U) +#define fb_mmu_fault_buffer_size_val_f(v) (((v)&0xfffffU) << 0U) +#define fb_mmu_fault_buffer_size_val_v(r) (((r) >> 0U) & 0xfffffU) +#define fb_mmu_fault_buffer_size_overflow_intr_f(v) (((v)&0x1U) << 29U) +#define fb_mmu_fault_buffer_size_overflow_intr_v(r) (((r) >> 29U) & 0x1U) +#define fb_mmu_fault_buffer_size_overflow_intr_enable_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_overflow_intr_enable_f() (0x20000000U) +#define fb_mmu_fault_buffer_size_set_default_f(v) (((v)&0x1U) << 30U) +#define fb_mmu_fault_buffer_size_set_default_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_buffer_size_set_default_yes_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_set_default_yes_f() (0x40000000U) +#define fb_mmu_fault_buffer_size_enable_f(v) (((v)&0x1U) << 31U) +#define fb_mmu_fault_buffer_size_enable_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_buffer_size_enable_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_buffer_size_enable_true_v() (0x00000001U) +#define fb_mmu_fault_buffer_size_enable_true_f() (0x80000000U) +#define fb_mmu_fault_addr_lo_r() (0x00100e4cU) +#define fb_mmu_fault_addr_lo_phys_aperture_f(v) (((v)&0x3U) << 0U) +#define fb_mmu_fault_addr_lo_phys_aperture_v(r) (((r) >> 0U) & 0x3U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f() (0x2U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f() (0x3U) +#define fb_mmu_fault_addr_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_addr_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_addr_hi_r() (0x00100e50U) +#define fb_mmu_fault_addr_hi_addr_f(v) (((v)&0xffffffffU) << 0U) +#define fb_mmu_fault_addr_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_inst_lo_r() (0x00100e54U) +#define fb_mmu_fault_inst_lo_engine_id_v(r) (((r) >> 0U) & 0x1ffU) +#define fb_mmu_fault_inst_lo_aperture_v(r) (((r) >> 10U) & 0x3U) +#define fb_mmu_fault_inst_lo_aperture_sys_coh_v() (0x00000002U) +#define fb_mmu_fault_inst_lo_aperture_sys_nocoh_v() (0x00000003U) +#define fb_mmu_fault_inst_lo_addr_f(v) (((v)&0xfffffU) << 12U) +#define fb_mmu_fault_inst_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) +#define fb_mmu_fault_inst_hi_r() (0x00100e58U) +#define fb_mmu_fault_inst_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) +#define fb_mmu_fault_info_r() (0x00100e5cU) +#define fb_mmu_fault_info_fault_type_v(r) (((r) >> 0U) & 0x1fU) +#define fb_mmu_fault_info_replayable_fault_v(r) (((r) >> 7U) & 0x1U) +#define fb_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU) +#define fb_mmu_fault_info_access_type_v(r) (((r) >> 16U) & 0xfU) +#define fb_mmu_fault_info_client_type_v(r) (((r) >> 20U) & 0x1U) +#define fb_mmu_fault_info_gpc_id_v(r) (((r) >> 24U) & 0x1fU) +#define fb_mmu_fault_info_protected_mode_v(r) (((r) >> 29U) & 0x1U) +#define fb_mmu_fault_info_replayable_fault_en_v(r) (((r) >> 30U) & 0x1U) +#define fb_mmu_fault_info_valid_v(r) (((r) >> 31U) & 0x1U) +#define fb_mmu_fault_status_r() (0x00100e60U) +#define fb_mmu_fault_status_dropped_bar1_phys_m() (U32(0x1U) << 0U) +#define fb_mmu_fault_status_dropped_bar1_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_phys_set_f() (0x1U) +#define fb_mmu_fault_status_dropped_bar1_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_phys_clear_f() (0x1U) +#define fb_mmu_fault_status_dropped_bar1_virt_m() (U32(0x1U) << 1U) +#define fb_mmu_fault_status_dropped_bar1_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_virt_set_f() (0x2U) +#define fb_mmu_fault_status_dropped_bar1_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar1_virt_clear_f() (0x2U) +#define fb_mmu_fault_status_dropped_bar2_phys_m() (U32(0x1U) << 2U) +#define fb_mmu_fault_status_dropped_bar2_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_phys_set_f() (0x4U) +#define fb_mmu_fault_status_dropped_bar2_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_phys_clear_f() (0x4U) +#define fb_mmu_fault_status_dropped_bar2_virt_m() (U32(0x1U) << 3U) +#define fb_mmu_fault_status_dropped_bar2_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_virt_set_f() (0x8U) +#define fb_mmu_fault_status_dropped_bar2_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_bar2_virt_clear_f() (0x8U) +#define fb_mmu_fault_status_dropped_ifb_phys_m() (U32(0x1U) << 4U) +#define fb_mmu_fault_status_dropped_ifb_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_phys_set_f() (0x10U) +#define fb_mmu_fault_status_dropped_ifb_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_phys_clear_f() (0x10U) +#define fb_mmu_fault_status_dropped_ifb_virt_m() (U32(0x1U) << 5U) +#define fb_mmu_fault_status_dropped_ifb_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_virt_set_f() (0x20U) +#define fb_mmu_fault_status_dropped_ifb_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_ifb_virt_clear_f() (0x20U) +#define fb_mmu_fault_status_dropped_other_phys_m() (U32(0x1U) << 6U) +#define fb_mmu_fault_status_dropped_other_phys_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_phys_set_f() (0x40U) +#define fb_mmu_fault_status_dropped_other_phys_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_phys_clear_f() (0x40U) +#define fb_mmu_fault_status_dropped_other_virt_m() (U32(0x1U) << 7U) +#define fb_mmu_fault_status_dropped_other_virt_set_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_virt_set_f() (0x80U) +#define fb_mmu_fault_status_dropped_other_virt_clear_v() (0x00000001U) +#define fb_mmu_fault_status_dropped_other_virt_clear_f() (0x80U) +#define fb_mmu_fault_status_replayable_m() (U32(0x1U) << 8U) +#define fb_mmu_fault_status_replayable_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_set_f() (0x100U) +#define fb_mmu_fault_status_replayable_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_m() (U32(0x1U) << 9U) +#define fb_mmu_fault_status_non_replayable_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_set_f() (0x200U) +#define fb_mmu_fault_status_non_replayable_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_error_m() (U32(0x1U) << 10U) +#define fb_mmu_fault_status_replayable_error_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_error_set_f() (0x400U) +#define fb_mmu_fault_status_replayable_error_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_error_m() (U32(0x1U) << 11U) +#define fb_mmu_fault_status_non_replayable_error_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_error_set_f() (0x800U) +#define fb_mmu_fault_status_non_replayable_error_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_overflow_m() (U32(0x1U) << 12U) +#define fb_mmu_fault_status_replayable_overflow_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_overflow_set_f() (0x1000U) +#define fb_mmu_fault_status_replayable_overflow_reset_f() (0x0U) +#define fb_mmu_fault_status_non_replayable_overflow_m() (U32(0x1U) << 13U) +#define fb_mmu_fault_status_non_replayable_overflow_set_v() (0x00000001U) +#define fb_mmu_fault_status_non_replayable_overflow_set_f() (0x2000U) +#define fb_mmu_fault_status_non_replayable_overflow_reset_f() (0x0U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_m() (U32(0x1U) << 14U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_set_v() (0x00000001U) +#define fb_mmu_fault_status_replayable_getptr_corrupted_set_f() (0x4000U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_m()\ + (U32(0x1U) << 15U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v()\ + (0x00000001U) +#define fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f() (0x8000U) +#define fb_mmu_fault_status_busy_m() (U32(0x1U) << 30U) +#define fb_mmu_fault_status_busy_true_v() (0x00000001U) +#define fb_mmu_fault_status_busy_true_f() (0x40000000U) +#define fb_mmu_fault_status_valid_m() (U32(0x1U) << 31U) +#define fb_mmu_fault_status_valid_set_v() (0x00000001U) +#define fb_mmu_fault_status_valid_set_f() (0x80000000U) +#define fb_mmu_fault_status_valid_clear_v() (0x00000001U) +#define fb_mmu_fault_status_valid_clear_f() (0x80000000U) +#define fb_mmu_local_memory_range_r() (0x00100ce0U) +#define fb_mmu_local_memory_range_lower_scale_v(r) (((r) >> 0U) & 0xfU) +#define fb_mmu_local_memory_range_lower_mag_v(r) (((r) >> 4U) & 0x3fU) +#define fb_mmu_local_memory_range_ecc_mode_v(r) (((r) >> 30U) & 0x1U) +#define fb_niso_scrub_status_r() (0x00100b20U) +#define fb_niso_scrub_status_flag_v(r) (((r) >> 0U) & 0x1U) +#define fb_mmu_priv_level_mask_r() (0x00100cdcU) +#define fb_mmu_priv_level_mask_write_violation_f(v) (((v)&0x1U) << 9U) +#define fb_mmu_priv_level_mask_write_violation_m() (U32(0x1U) << 9U) +#define fb_mmu_priv_level_mask_write_violation_v(r) (((r) >> 9U) & 0x1U) +#define fb_hshub_config0_r() (0x001fbc00U) +#define fb_hshub_config0_sysmem_nvlink_mask_f(v) (((v)&0xffffU) << 0U) +#define fb_hshub_config0_sysmem_nvlink_mask_m() (U32(0xffffU) << 0U) +#define fb_hshub_config0_sysmem_nvlink_mask_v(r) (((r) >> 0U) & 0xffffU) +#define fb_hshub_config0_peer_pcie_mask_f(v) (((v)&0xffffU) << 16U) +#define fb_hshub_config0_peer_pcie_mask_v(r) (((r) >> 16U) & 0xffffU) +#define fb_hshub_config1_r() (0x001fbc04U) +#define fb_hshub_config1_peer_0_nvlink_mask_f(v) (((v)&0xffU) << 0U) +#define fb_hshub_config1_peer_0_nvlink_mask_v(r) (((r) >> 0U) & 0xffU) +#define fb_hshub_config1_peer_1_nvlink_mask_f(v) (((v)&0xffU) << 8U) +#define fb_hshub_config1_peer_1_nvlink_mask_v(r) (((r) >> 8U) & 0xffU) +#define fb_hshub_config1_peer_2_nvlink_mask_f(v) (((v)&0xffU) << 16U) +#define fb_hshub_config1_peer_2_nvlink_mask_v(r) (((r) >> 16U) & 0xffU) +#define fb_hshub_config1_peer_3_nvlink_mask_f(v) (((v)&0xffU) << 24U) +#define fb_hshub_config1_peer_3_nvlink_mask_v(r) (((r) >> 24U) & 0xffU) +#define fb_hshub_config2_r() (0x001fbc08U) +#define fb_hshub_config2_peer_4_nvlink_mask_f(v) (((v)&0xffU) << 0U) +#define fb_hshub_config2_peer_4_nvlink_mask_v(r) (((r) >> 0U) & 0xffU) +#define fb_hshub_config2_peer_5_nvlink_mask_f(v) (((v)&0xffU) << 8U) +#define fb_hshub_config2_peer_5_nvlink_mask_v(r) (((r) >> 8U) & 0xffU) +#define fb_hshub_config2_peer_6_nvlink_mask_f(v) (((v)&0xffU) << 16U) +#define fb_hshub_config2_peer_6_nvlink_mask_v(r) (((r) >> 16U) & 0xffU) +#define fb_hshub_config2_peer_7_nvlink_mask_f(v) (((v)&0xffU) << 24U) +#define fb_hshub_config2_peer_7_nvlink_mask_v(r) (((r) >> 24U) & 0xffU) +#define fb_hshub_config6_r() (0x001fbc18U) +#define fb_hshub_config7_r() (0x001fbc1cU) +#define fb_hshub_config7_nvlink_logical_0_physical_portmap_f(v)\ + (((v)&0xfU) << 0U) +#define fb_hshub_config7_nvlink_logical_0_physical_portmap_v(r)\ + (((r) >> 0U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_1_physical_portmap_f(v)\ + (((v)&0xfU) << 4U) +#define fb_hshub_config7_nvlink_logical_1_physical_portmap_v(r)\ + (((r) >> 4U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_2_physical_portmap_f(v)\ + (((v)&0xfU) << 8U) +#define fb_hshub_config7_nvlink_logical_2_physical_portmap_v(r)\ + (((r) >> 8U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_3_physical_portmap_f(v)\ + (((v)&0xfU) << 12U) +#define fb_hshub_config7_nvlink_logical_3_physical_portmap_v(r)\ + (((r) >> 12U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_4_physical_portmap_f(v)\ + (((v)&0xfU) << 16U) +#define fb_hshub_config7_nvlink_logical_4_physical_portmap_v(r)\ + (((r) >> 16U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_5_physical_portmap_f(v)\ + (((v)&0xfU) << 20U) +#define fb_hshub_config7_nvlink_logical_5_physical_portmap_v(r)\ + (((r) >> 20U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_6_physical_portmap_f(v)\ + (((v)&0xfU) << 24U) +#define fb_hshub_config7_nvlink_logical_6_physical_portmap_v(r)\ + (((r) >> 24U) & 0xfU) +#define fb_hshub_config7_nvlink_logical_7_physical_portmap_f(v)\ + (((v)&0xfU) << 28U) +#define fb_hshub_config7_nvlink_logical_7_physical_portmap_v(r)\ + (((r) >> 28U) & 0xfU) +#define fb_hshub_nvl_cfg_priv_level_mask_r() (0x001fbc50U) +#define fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(v)\ + (((v)&0xfU) << 4U) +#define fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(r)\ + (((r) >> 4U) & 0xfU) +#define fb_mmu_int_vector_info_fault_r() (0x00100ee0U) +#define fb_mmu_int_vector_info_fault_vector_v(r) (((r) >> 0U) & 0xffffU) +#define fb_mmu_int_vector_ecc_error_r() (0x00100edcU) +#define fb_mmu_int_vector_ecc_error_vector_v(r) (((r) >> 0U) & 0xffffU) +#define fb_mmu_int_vector_fault_r(i)\ + (nvgpu_safe_add_u32(0x00100ee4U, nvgpu_safe_mult_u32((i), 4U))) +#define fb_mmu_int_vector_fault_error_v(r) (((r) >> 0U) & 0xffffU) +#define fb_mmu_int_vector_fault_notify_v(r) (((r) >> 16U) & 0xffffU) +#define fb_mmu_num_active_ltcs_r() (0x00100ec0U) +#define fb_mmu_num_active_ltcs_count_f(v) (((v)&0x1fU) << 0U) +#define fb_mmu_num_active_ltcs_count_v(r) (((r) >> 0U) & 0x1fU) +#define fb_mmu_cbc_base_r() (0x00100ec4U) +#define fb_mmu_cbc_base_address_f(v) (((v)&0x3ffffffU) << 0U) +#define fb_mmu_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define fb_mmu_cbc_base_address_alignment_shift_v() (0x0000000bU) +#define fb_mmu_cbc_top_r() (0x00100ec8U) +#define fb_mmu_cbc_top_size_f(v) (((v)&0x7fffU) << 0U) +#define fb_mmu_cbc_top_size_v(r) (((r) >> 0U) & 0x7fffU) +#define fb_mmu_cbc_top_size_alignment_shift_v() (0x0000000bU) +#define fb_mmu_cbc_max_r() (0x00100eccU) +#define fb_mmu_cbc_max_comptagline_f(v) (((v)&0xffffffU) << 0U) +#define fb_mmu_cbc_max_comptagline_m() (U32(0xffffffU) << 0U) +#define fb_mmu_cbc_max_comptagline_v(r) (((r) >> 0U) & 0xffffffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fbpa_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fbpa_tu104.h index 0575b4c27..696baac37 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fbpa_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fbpa_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,72 +59,24 @@ #include #include -static inline u32 fbpa_0_intr_status_r(void) -{ - return 0x00900398U; -} -static inline u32 fbpa_0_intr_status_sec_subp0_pending_f(void) -{ - return 0x1U; -} -static inline u32 fbpa_0_intr_status_ded_subp0_pending_f(void) -{ - return 0x2U; -} -static inline u32 fbpa_0_intr_status_sec_subp1_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fbpa_0_intr_status_ded_subp1_pending_f(void) -{ - return 0x20000U; -} -static inline u32 fbpa_ecc_intr_ctrl_r(void) -{ - return 0x009a0474U; -} -static inline u32 fbpa_ecc_intr_ctrl_sec_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f(void) -{ - return 0x1U; -} -static inline u32 fbpa_ecc_intr_ctrl_ded_intr_en_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f(void) -{ - return 0x2U; -} -static inline u32 fbpa_0_ecc_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00900478U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fbpa_0_ecc_status_sec_intr_pending_f(void) -{ - return 0x2U; -} -static inline u32 fbpa_0_ecc_status_ded_intr_pending_f(void) -{ - return 0x4U; -} -static inline u32 fbpa_0_ecc_status_sec_counter_overflow_pending_f(void) -{ - return 0x20000U; -} -static inline u32 fbpa_0_ecc_status_ded_counter_overflow_pending_f(void) -{ - return 0x40000U; -} -static inline u32 fbpa_0_ecc_sec_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00900480U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fbpa_0_ecc_ded_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00900488U, nvgpu_safe_mult_u32(i, 4U)); -} +#define fbpa_0_intr_status_r() (0x00900398U) +#define fbpa_0_intr_status_sec_subp0_pending_f() (0x1U) +#define fbpa_0_intr_status_ded_subp0_pending_f() (0x2U) +#define fbpa_0_intr_status_sec_subp1_pending_f() (0x10000U) +#define fbpa_0_intr_status_ded_subp1_pending_f() (0x20000U) +#define fbpa_ecc_intr_ctrl_r() (0x009a0474U) +#define fbpa_ecc_intr_ctrl_sec_intr_en_f(v) (((v)&0x1U) << 0U) +#define fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f() (0x1U) +#define fbpa_ecc_intr_ctrl_ded_intr_en_f(v) (((v)&0x1U) << 1U) +#define fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f() (0x2U) +#define fbpa_0_ecc_status_r(i)\ + (nvgpu_safe_add_u32(0x00900478U, nvgpu_safe_mult_u32((i), 4U))) +#define fbpa_0_ecc_status_sec_intr_pending_f() (0x2U) +#define fbpa_0_ecc_status_ded_intr_pending_f() (0x4U) +#define fbpa_0_ecc_status_sec_counter_overflow_pending_f() (0x20000U) +#define fbpa_0_ecc_status_ded_counter_overflow_pending_f() (0x40000U) +#define fbpa_0_ecc_sec_count_r(i)\ + (nvgpu_safe_add_u32(0x00900480U, nvgpu_safe_mult_u32((i), 4U))) +#define fbpa_0_ecc_ded_count_r(i)\ + (nvgpu_safe_add_u32(0x00900488U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h index e806c6474..6c7a41033 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,448 +59,128 @@ #include #include -static inline u32 fifo_userd_writeback_r(void) -{ - return 0x0000225cU; -} -static inline u32 fifo_userd_writeback_timer_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_userd_writeback_timer_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_userd_writeback_timer_shorter_v(void) -{ - return 0x00000003U; -} -static inline u32 fifo_userd_writeback_timer_100us_v(void) -{ - return 0x00000064U; -} -static inline u32 fifo_userd_writeback_timescale_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 fifo_userd_writeback_timescale_0_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_runlist_base_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002b00U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_runlist_base_lo__size_1_v(void) -{ - return 0x0000000bU; -} -static inline u32 fifo_runlist_base_lo_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_runlist_base_lo_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 fifo_runlist_base_lo_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 fifo_runlist_base_lo_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 fifo_runlist_base_lo_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 fifo_runlist_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002b04U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_runlist_base_hi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_runlist_submit_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002b08U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_runlist_submit_length_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fifo_runlist_submit_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002b0cU, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 fifo_runlist_submit_info_pending_true_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100U; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1U; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100U; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000U; -} -static inline u32 fifo_intr_0_memop_timeout_pending_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_memop_timeout_reset_f(void) -{ - return 0x800000U; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140U; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528U; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252cU; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254cU; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256cU; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0U; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00U; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04U; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return U32(0x3fffffffU) << 0U; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffffU; -} -static inline u32 fifo_fb_timeout_period_init_f(void) -{ - return 0x3c00U; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630U; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_runlist_preempt_r(void) -{ - return 0x00002638U; -} -static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) -{ - return (v & 0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_m(u32 i) -{ - return U32(0x1U) << (0U + i*1U); -} -static inline u32 fifo_runlist_preempt_runlist_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634U; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000U; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0U; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000U; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x0000000dU; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_eng_reload_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000U; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13U) & 0x7U; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006U; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007U; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16U) & 0xfffU; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000U; -} -static inline u32 fifo_pbdma_status_next_id_type_tsgid_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001U; -} -static inline u32 fifo_cfg0_r(void) -{ - return 0x00002004U; -} -static inline u32 fifo_cfg0_num_pbdma_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} +#define fifo_userd_writeback_r() (0x0000225cU) +#define fifo_userd_writeback_timer_f(v) (((v)&0xffU) << 0U) +#define fifo_userd_writeback_timer_disabled_v() (0x00000000U) +#define fifo_userd_writeback_timer_shorter_v() (0x00000003U) +#define fifo_userd_writeback_timer_100us_v() (0x00000064U) +#define fifo_userd_writeback_timescale_f(v) (((v)&0xfU) << 12U) +#define fifo_userd_writeback_timescale_0_v() (0x00000000U) +#define fifo_runlist_base_lo_r(i)\ + (nvgpu_safe_add_u32(0x00002b00U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_runlist_base_lo__size_1_v() (0x0000000bU) +#define fifo_runlist_base_lo_ptr_align_shift_v() (0x0000000cU) +#define fifo_runlist_base_lo_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define fifo_runlist_base_lo_target_vid_mem_f() (0x0U) +#define fifo_runlist_base_lo_target_sys_mem_coh_f() (0x2U) +#define fifo_runlist_base_lo_target_sys_mem_ncoh_f() (0x3U) +#define fifo_runlist_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x00002b04U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_runlist_base_hi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define fifo_runlist_submit_r(i)\ + (nvgpu_safe_add_u32(0x00002b08U, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_runlist_submit_length_f(v) (((v)&0xffffU) << 0U) +#define fifo_runlist_submit_info_r(i)\ + (nvgpu_safe_add_u32(0x00002b0cU, nvgpu_safe_mult_u32((i), 16U))) +#define fifo_runlist_submit_info_pending_true_f() (0x8000U) +#define fifo_pbdma_map_r(i)\ + (nvgpu_safe_add_u32(0x00002390U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_intr_0_r() (0x00002100U) +#define fifo_intr_0_bind_error_pending_f() (0x1U) +#define fifo_intr_0_bind_error_reset_f() (0x1U) +#define fifo_intr_0_sched_error_pending_f() (0x100U) +#define fifo_intr_0_sched_error_reset_f() (0x100U) +#define fifo_intr_0_chsw_error_pending_f() (0x10000U) +#define fifo_intr_0_chsw_error_reset_f() (0x10000U) +#define fifo_intr_0_memop_timeout_pending_f() (0x800000U) +#define fifo_intr_0_memop_timeout_reset_f() (0x800000U) +#define fifo_intr_0_lb_error_pending_f() (0x1000000U) +#define fifo_intr_0_lb_error_reset_f() (0x1000000U) +#define fifo_intr_0_pbdma_intr_pending_f() (0x20000000U) +#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) +#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) +#define fifo_intr_0_ctxsw_timeout_pending_f() (0x2U) +#define fifo_intr_en_0_r() (0x00002140U) +#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) +#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) +#define fifo_intr_en_1_r() (0x00002528U) +#define fifo_intr_bind_error_r() (0x0000252cU) +#define fifo_intr_sched_error_r() (0x0000254cU) +#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) +#define fifo_intr_chsw_error_r() (0x0000256cU) +#define fifo_intr_pbdma_id_r() (0x000025a0U) +#define fifo_intr_pbdma_id_status_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_intr_pbdma_id_status_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fifo_intr_pbdma_id_status__size_1_v() (0x0000000cU) +#define fifo_intr_runlist_r() (0x00002a00U) +#define fifo_fb_timeout_r() (0x00002a04U) +#define fifo_fb_timeout_period_m() (U32(0x3fffffffU) << 0U) +#define fifo_fb_timeout_period_max_f() (0x3fffffffU) +#define fifo_fb_timeout_period_init_f() (0x3c00U) +#define fifo_sched_disable_r() (0x00002630U) +#define fifo_sched_disable_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_sched_disable_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_sched_disable_true_v() (0x00000001U) +#define fifo_runlist_preempt_r() (0x00002638U) +#define fifo_runlist_preempt_runlist_f(v, i)\ + (((v) & 0x1) << (0U + i*1U)) +#define fifo_runlist_preempt_runlist_m(i)\ + (U32(0x1U) << (0U + (i)*1U)) +#define fifo_runlist_preempt_runlist_pending_v() (0x00000001U) +#define fifo_preempt_r() (0x00002634U) +#define fifo_preempt_pending_true_f() (0x100000U) +#define fifo_preempt_type_channel_f() (0x0U) +#define fifo_preempt_type_tsg_f() (0x1000000U) +#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) +#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) +#define fifo_engine_status_r(i)\ + (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) +#define fifo_engine_status__size_1_v() (0x0000000dU) +#define fifo_engine_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_engine_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_engine_status_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_engine_status_ctx_status_valid_v() (0x00000001U) +#define fifo_engine_status_ctx_status_ctxsw_load_v() (0x00000005U) +#define fifo_engine_status_ctx_status_ctxsw_save_v() (0x00000006U) +#define fifo_engine_status_ctx_status_ctxsw_switch_v() (0x00000007U) +#define fifo_engine_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_engine_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_engine_status_next_id_type_chid_v() (0x00000000U) +#define fifo_engine_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_engine_status_eng_reload_v(r) (((r) >> 29U) & 0x1U) +#define fifo_engine_status_faulted_v(r) (((r) >> 30U) & 0x1U) +#define fifo_engine_status_faulted_true_v() (0x00000001U) +#define fifo_engine_status_engine_v(r) (((r) >> 31U) & 0x1U) +#define fifo_engine_status_engine_idle_v() (0x00000000U) +#define fifo_engine_status_engine_busy_v() (0x00000001U) +#define fifo_engine_status_ctxsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_engine_status_ctxsw_in_progress_v() (0x00000001U) +#define fifo_engine_status_ctxsw_in_progress_f() (0x8000U) +#define fifo_pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00003080U, nvgpu_safe_mult_u32((i), 4U))) +#define fifo_pbdma_status__size_1_v() (0x0000000cU) +#define fifo_pbdma_status_id_v(r) (((r) >> 0U) & 0xfffU) +#define fifo_pbdma_status_id_type_v(r) (((r) >> 12U) & 0x1U) +#define fifo_pbdma_status_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_v(r) (((r) >> 13U) & 0x7U) +#define fifo_pbdma_status_chan_status_valid_v() (0x00000001U) +#define fifo_pbdma_status_chan_status_chsw_load_v() (0x00000005U) +#define fifo_pbdma_status_chan_status_chsw_save_v() (0x00000006U) +#define fifo_pbdma_status_chan_status_chsw_switch_v() (0x00000007U) +#define fifo_pbdma_status_next_id_v(r) (((r) >> 16U) & 0xfffU) +#define fifo_pbdma_status_next_id_type_v(r) (((r) >> 28U) & 0x1U) +#define fifo_pbdma_status_next_id_type_chid_v() (0x00000000U) +#define fifo_pbdma_status_next_id_type_tsgid_v() (0x00000001U) +#define fifo_pbdma_status_chsw_v(r) (((r) >> 15U) & 0x1U) +#define fifo_pbdma_status_chsw_in_progress_v() (0x00000001U) +#define fifo_cfg0_r() (0x00002004U) +#define fifo_cfg0_num_pbdma_v(r) (((r) >> 0U) & 0xffU) +#define fifo_cfg0_pbdma_fault_id_v(r) (((r) >> 16U) & 0xffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_flush_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_flush_tu104.h index 652a5b1a2..1c8e8e3da 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_flush_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_flush_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,132 +59,36 @@ #include #include -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004U; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010U; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000cU; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000U; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0U; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000U; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1U; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001U; -} +#define flush_l2_system_invalidate_r() (0x00070004U) +#define flush_l2_system_invalidate_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_system_invalidate_pending_busy_v() (0x00000001U) +#define flush_l2_system_invalidate_pending_busy_f() (0x1U) +#define flush_l2_system_invalidate_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_system_invalidate_outstanding_true_v() (0x00000001U) +#define flush_l2_flush_dirty_r() (0x00070010U) +#define flush_l2_flush_dirty_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_flush_dirty_pending_empty_v() (0x00000000U) +#define flush_l2_flush_dirty_pending_empty_f() (0x0U) +#define flush_l2_flush_dirty_pending_busy_v() (0x00000001U) +#define flush_l2_flush_dirty_pending_busy_f() (0x1U) +#define flush_l2_flush_dirty_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_flush_dirty_outstanding_false_v() (0x00000000U) +#define flush_l2_flush_dirty_outstanding_false_f() (0x0U) +#define flush_l2_flush_dirty_outstanding_true_v() (0x00000001U) +#define flush_l2_clean_comptags_r() (0x0007000cU) +#define flush_l2_clean_comptags_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_l2_clean_comptags_pending_empty_v() (0x00000000U) +#define flush_l2_clean_comptags_pending_empty_f() (0x0U) +#define flush_l2_clean_comptags_pending_busy_v() (0x00000001U) +#define flush_l2_clean_comptags_pending_busy_f() (0x1U) +#define flush_l2_clean_comptags_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_l2_clean_comptags_outstanding_false_v() (0x00000000U) +#define flush_l2_clean_comptags_outstanding_false_f() (0x0U) +#define flush_l2_clean_comptags_outstanding_true_v() (0x00000001U) +#define flush_fb_flush_r() (0x00070000U) +#define flush_fb_flush_pending_v(r) (((r) >> 0U) & 0x1U) +#define flush_fb_flush_pending_busy_v() (0x00000001U) +#define flush_fb_flush_pending_busy_f() (0x1U) +#define flush_fb_flush_outstanding_v(r) (((r) >> 1U) & 0x1U) +#define flush_fb_flush_outstanding_true_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_func_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_func_tu104.h index 36c2aadcc..7355d20c4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_func_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_func_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,108 +59,41 @@ #include #include -static inline u32 func_full_phys_offset_v(void) -{ - return 0x00b80000U; -} -static inline u32 func_doorbell_r(void) -{ - return 0x00030090U; -} -static inline u32 func_cfg0_r(void) -{ - return 0x00030000U; -} -static inline u32 func_priv_cpu_intr_top_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001608U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 func_priv_cpu_intr_top_en_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001610U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 func_priv_cpu_intr_top_en_clear__size_1_v(void) -{ - return 0x00000001U; -} -static inline u32 func_priv_cpu_intr_leaf_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 func_priv_cpu_intr_leaf_en_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001400U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 func_priv_cpu_intr_leaf_en_clear__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 func_priv_cpu_intr_top_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001600U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 func_priv_cpu_intr_leaf_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00001000U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 func_priv_mmu_fault_buffer_lo_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003000U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 func_priv_mmu_fault_buffer_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003004U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 func_priv_mmu_fault_buffer_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003008U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 func_priv_mmu_fault_buffer_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0000300cU, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 func_priv_mmu_fault_buffer_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00003010U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 func_priv_mmu_fault_addr_lo_r(void) -{ - return 0x00003080U; -} -static inline u32 func_priv_mmu_fault_addr_hi_r(void) -{ - return 0x00003084U; -} -static inline u32 func_priv_mmu_fault_inst_lo_r(void) -{ - return 0x00003088U; -} -static inline u32 func_priv_mmu_fault_inst_hi_r(void) -{ - return 0x0000308cU; -} -static inline u32 func_priv_mmu_fault_info_r(void) -{ - return 0x00003090U; -} -static inline u32 func_priv_mmu_fault_status_r(void) -{ - return 0x00003094U; -} -static inline u32 func_priv_bar2_block_r(void) -{ - return 0x00000f48U; -} -static inline u32 func_priv_bind_status_r(void) -{ - return 0x00000f50U; -} -static inline u32 func_priv_mmu_invalidate_pdb_r(void) -{ - return 0x000030a0U; -} -static inline u32 func_priv_mmu_invalidate_r(void) -{ - return 0x000030b0U; -} +#define func_full_phys_offset_v() (0x00b80000U) +#define func_doorbell_r() (0x00030090U) +#define func_cfg0_r() (0x00030000U) +#define func_priv_cpu_intr_top_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00001608U, nvgpu_safe_mult_u32((i), 4U))) +#define func_priv_cpu_intr_top_en_clear_r(i)\ + (nvgpu_safe_add_u32(0x00001610U, nvgpu_safe_mult_u32((i), 4U))) +#define func_priv_cpu_intr_top_en_clear__size_1_v() (0x00000001U) +#define func_priv_cpu_intr_leaf_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00001200U, nvgpu_safe_mult_u32((i), 4U))) +#define func_priv_cpu_intr_leaf_en_clear_r(i)\ + (nvgpu_safe_add_u32(0x00001400U, nvgpu_safe_mult_u32((i), 4U))) +#define func_priv_cpu_intr_leaf_en_clear__size_1_v() (0x00000008U) +#define func_priv_cpu_intr_top_r(i)\ + (nvgpu_safe_add_u32(0x00001600U, nvgpu_safe_mult_u32((i), 4U))) +#define func_priv_cpu_intr_leaf_r(i)\ + (nvgpu_safe_add_u32(0x00001000U, nvgpu_safe_mult_u32((i), 4U))) +#define func_priv_mmu_fault_buffer_lo_r(i)\ + (nvgpu_safe_add_u32(0x00003000U, nvgpu_safe_mult_u32((i), 32U))) +#define func_priv_mmu_fault_buffer_hi_r(i)\ + (nvgpu_safe_add_u32(0x00003004U, nvgpu_safe_mult_u32((i), 32U))) +#define func_priv_mmu_fault_buffer_get_r(i)\ + (nvgpu_safe_add_u32(0x00003008U, nvgpu_safe_mult_u32((i), 32U))) +#define func_priv_mmu_fault_buffer_put_r(i)\ + (nvgpu_safe_add_u32(0x0000300cU, nvgpu_safe_mult_u32((i), 32U))) +#define func_priv_mmu_fault_buffer_size_r(i)\ + (nvgpu_safe_add_u32(0x00003010U, nvgpu_safe_mult_u32((i), 32U))) +#define func_priv_mmu_fault_addr_lo_r() (0x00003080U) +#define func_priv_mmu_fault_addr_hi_r() (0x00003084U) +#define func_priv_mmu_fault_inst_lo_r() (0x00003088U) +#define func_priv_mmu_fault_inst_hi_r() (0x0000308cU) +#define func_priv_mmu_fault_info_r() (0x00003090U) +#define func_priv_mmu_fault_status_r() (0x00003094U) +#define func_priv_bar2_block_r() (0x00000f48U) +#define func_priv_bind_status_r() (0x00000f50U) +#define func_priv_mmu_invalidate_pdb_r() (0x000030a0U) +#define func_priv_mmu_invalidate_r() (0x000030b0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fuse_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fuse_tu104.h index 4b0790689..1acedc740 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fuse_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fuse_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,52 +59,20 @@ #include #include -static inline u32 fuse_status_opt_gpc_r(void) -{ - return 0x00021c1cU; -} -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14U; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38U; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0U + i*1U)) & 0x1U; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228U; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0U; -} +#define fuse_status_opt_gpc_r() (0x00021c1cU) +#define fuse_status_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021c38U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_ctrl_opt_tpc_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_status_opt_fbio_r() (0x00021c14U) +#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) +#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) +#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) +#define fuse_status_opt_rop_l2_fbp_r(i)\ + (nvgpu_safe_add_u32(0x00021d70U, nvgpu_safe_mult_u32((i), 4U))) +#define fuse_status_opt_fbp_r() (0x00021d38U) +#define fuse_status_opt_fbp_idx_v(r, i)\ + (((r) >> (0U + i*1U)) & 0x1U) +#define fuse_opt_ecc_en_r() (0x00021228U) +#define fuse_opt_feature_fuses_override_disable_r() (0x000213f0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gc6_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gc6_tu104.h index 0b20513cb..8f7eaa46a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gc6_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gc6_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 gc6_aon_secure_scratch_group_05_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00118234U, nvgpu_safe_mult_u32(i, 4U)); -} +#define gc6_aon_secure_scratch_group_05_r(i)\ + (nvgpu_safe_add_u32(0x00118234U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gmmu_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gmmu_tu104.h index cb6da2d90..7afc169e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gmmu_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gmmu_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,300 +59,78 @@ #include #include -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2U; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010U; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008U; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1U; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20U; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8U; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4U; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6U; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0U; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40U; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0xfffffU) << 4U; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xffU) << 4U; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1U; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x00000007U; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_gpc_v(void) -{ - return 0x00000000U; -} -static inline u32 gmmu_fault_client_type_hub_v(void) -{ - return 0x00000001U; -} -static inline u32 gmmu_fault_type_unbound_inst_block_v(void) -{ - return 0x00000004U; -} -static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) -{ - return 0x000000c0U; -} -static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) -{ - return 0x0000001fU; -} -static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) -{ - return 0x0000000fU; -} +#define gmmu_new_pde_is_pte_w() (0U) +#define gmmu_new_pde_is_pte_false_f() (0x0U) +#define gmmu_new_pde_aperture_w() (0U) +#define gmmu_new_pde_aperture_invalid_f() (0x0U) +#define gmmu_new_pde_aperture_video_memory_f() (0x2U) +#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pde_address_sys_w() (0U) +#define gmmu_new_pde_vol_w() (0U) +#define gmmu_new_pde_vol_true_f() (0x8U) +#define gmmu_new_pde_vol_false_f() (0x0U) +#define gmmu_new_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_pde__size_v() (0x00000008U) +#define gmmu_new_dual_pde_is_pte_w() (0U) +#define gmmu_new_dual_pde_is_pte_false_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_w() (0U) +#define gmmu_new_dual_pde_aperture_big_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) +#define gmmu_new_dual_pde_address_big_sys_w() (0U) +#define gmmu_new_dual_pde_aperture_small_w() (2U) +#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) +#define gmmu_new_dual_pde_aperture_small_video_memory_f() (0x2U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_coh_f() (0x4U) +#define gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_dual_pde_vol_small_w() (2U) +#define gmmu_new_dual_pde_vol_small_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_small_false_f() (0x0U) +#define gmmu_new_dual_pde_vol_big_w() (0U) +#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) +#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) +#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_dual_pde_address_small_sys_w() (2U) +#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) +#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) +#define gmmu_new_dual_pde__size_v() (0x00000010U) +#define gmmu_new_pte__size_v() (0x00000008U) +#define gmmu_new_pte_valid_w() (0U) +#define gmmu_new_pte_valid_true_f() (0x1U) +#define gmmu_new_pte_valid_false_f() (0x0U) +#define gmmu_new_pte_privilege_w() (0U) +#define gmmu_new_pte_privilege_true_f() (0x20U) +#define gmmu_new_pte_privilege_false_f() (0x0U) +#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_sys_w() (0U) +#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) +#define gmmu_new_pte_address_vid_w() (0U) +#define gmmu_new_pte_vol_w() (0U) +#define gmmu_new_pte_vol_true_f() (0x8U) +#define gmmu_new_pte_vol_false_f() (0x0U) +#define gmmu_new_pte_aperture_w() (0U) +#define gmmu_new_pte_aperture_video_memory_f() (0x0U) +#define gmmu_new_pte_aperture_sys_mem_coh_f() (0x4U) +#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) +#define gmmu_new_pte_read_only_w() (0U) +#define gmmu_new_pte_read_only_true_f() (0x40U) +#define gmmu_new_pte_comptagline_f(v) (((v)&0xfffffU) << 4U) +#define gmmu_new_pte_comptagline_w() (1U) +#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) +#define gmmu_new_pte_kind_w() (1U) +#define gmmu_new_pte_address_shift_v() (0x0000000cU) +#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) +#define gmmu_pte_kind_w() (1U) +#define gmmu_pte_kind_invalid_v() (0x00000007U) +#define gmmu_pte_kind_pitch_v() (0x00000000U) +#define gmmu_fault_client_type_gpc_v() (0x00000000U) +#define gmmu_fault_client_type_hub_v() (0x00000001U) +#define gmmu_fault_type_unbound_inst_block_v() (0x00000004U) +#define gmmu_fault_mmu_eng_id_bar2_v() (0x000000c0U) +#define gmmu_fault_mmu_eng_id_physical_v() (0x0000001fU) +#define gmmu_fault_mmu_eng_id_ce0_v() (0x0000000fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h index 85bae9203..0dbe835a4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,4040 +59,1116 @@ #include #include -static inline u32 gr_intr_r(void) -{ - return 0x00400100U; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1U; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2U; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10U; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40U; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100U; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20U; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000U; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000U; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000U; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000U; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144U; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110U; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013cU; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108U; -} -static inline u32 gr_exception_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118U; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011cU; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138U; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_exception_en_fe_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_exception_en_gpc_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 gr_exception_en_gpc_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 gr_exception_en_memfmt_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_exception_en_memfmt_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_exception_en_ds_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_exception_en_ds_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_exception_en_pd_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_exception_en_pd_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_exception_en_scc_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_exception_en_scc_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_exception_en_ssync_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_exception_en_ssync_enabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_exception_en_mme_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_exception_en_mme_enabled_f(void) -{ - return 0x80U; -} -static inline u32 gr_exception_en_sked_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_exception_en_sked_enabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130U; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134U; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500U; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504U; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704U; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 gr_trapped_addr_mme_generated_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 gr_trapped_addr_datahigh_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_trapped_addr_priv_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_trapped_addr_status_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708U; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070cU; -} -static inline u32 gr_trapped_data_mme_r(void) -{ - return 0x00400710U; -} -static inline u32 gr_trapped_data_mme_pc_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700U; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610U; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604U; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608U; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060cU; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204U; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380U; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384U; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388U; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390U; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3U; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000U; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x0050433cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419b3cU; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88U; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8cU; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88U; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8cU; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00U; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200U; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00U; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858U; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194U; -} -static inline u32 gr_pri_fe_chip_def_info_r(void) -{ - return 0x00404030U; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x00504358U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) -{ - return U32(0x1U) << 9U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) -{ - return U32(0x1U) << 14U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 26U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) -{ - return 0x0050435cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) -{ - return 0x00504360U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) -{ - return 0x0050436cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) -{ - return 0x00504370U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) -{ - return 0x00504374U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) -{ - return 0x00504638U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) -{ - return 0x0050463cU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) -{ - return 0x00504640U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) -{ - return 16U; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1U; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) -{ - return 0x00504430U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) -{ - return 0x00504434U; -} -static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134U; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934U; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048U; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004cU; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848U; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884cU; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200U; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_pipe_bundle_address_veid_f(u32 v) -{ - return (v & 0x3fU) << 20U; -} -static inline u32 gr_pipe_bundle_address_veid_w(void) -{ - return 0U; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204U; -} -static inline u32 gr_pipe_bundle_data_hi_r(void) -{ - return 0x0040020cU; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000U; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fe_hww_esr_info_r(void) -{ - return 0x004041b0U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) -{ - return 0x00419eacU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x0050472cU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) -{ - return 0x00419eb4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) -{ - return 0x100U; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154U; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800U; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_fe_tpc_fs_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488U; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448cU; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490U; -} -static inline u32 gr_mme_hww_esr_missing_macro_data_pending_f(void) -{ - return 0x1U; -} -static inline u32 gr_mme_hww_esr_illegal_opcode_pending_f(void) -{ - return 0x4U; -} -static inline u32 gr_mme_hww_esr_branch_in_delay_pending_f(void) -{ - return 0x8U; -} -static inline u32 gr_mme_hww_esr_inst_ram_acess_pending_f(void) -{ - return 0x20U; -} -static inline u32 gr_mme_hww_esr_data_ram_access_pending_f(void) -{ - return 0x40U; -} -static inline u32 gr_mme_hww_esr_illegal_mme_method_pending_f(void) -{ - return 0x80U; -} -static inline u32 gr_mme_hww_esr_dma_dram_access_pending_f(void) -{ - return 0x10000U; -} -static inline u32 gr_mme_hww_esr_dma_read_pb_pending_f(void) -{ - return 0x20000U; -} -static inline u32 gr_mme_hww_esr_dma_illegal_fifo_pending_f(void) -{ - return 0x40000U; -} -static inline u32 gr_mme_hww_esr_dma_read_overflow_pending_f(void) -{ - return 0x80000U; -} -static inline u32 gr_mme_hww_esr_dma_fifo_resized_pending_f(void) -{ - return 0x100000U; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_mme_hww_esr_info_r(void) -{ - return 0x00404494U; -} -static inline u32 gr_mme_hww_esr_info_pc_valid_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 gr_mme_hww_esr_info2_r(void) -{ - return 0x0040449cU; -} -static inline u32 gr_mme_hww_esr_info3_r(void) -{ - return 0x004044a8U; -} -static inline u32 gr_mme_hww_esr_info4_r(void) -{ - return 0x004044acU; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600U; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100U; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130U; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910cU; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080U; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904cU; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040U; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044U; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008U; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900cU; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018U; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901cU; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050U; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054U; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4U; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090U; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094U; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200U; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920cU; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110U; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114U; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911cU; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118U; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104U; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_irqsset_r(void) -{ - return 0x00409000U; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108U; -} -static inline u32 gr_gpcs_gpccs_irqsset_r(void) -{ - return 0x0041a000U; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108U; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084U; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00U; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500U; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504U; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003U; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3U; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009U; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015U; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016U; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025U; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031U; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032U; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038U; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039U; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21U; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001aU; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003aU; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18U; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24U; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2U; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000U; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000U; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10U) & 0x1U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400U; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960cU; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002U; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return U32(0x1fU) << 16U; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620U; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24U; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04U; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1U; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0cU; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return U32(0xfffffffU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0U) & 0xfffffffU; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return U32(0x1fU) << 0U; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400U; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420U; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420U; -} -static inline u32 gr_rstr2d_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bcU; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018U; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xfU) << 24U; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xfU) << 28U; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0U; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffffU; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080U; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fffU) << 0U; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000a80U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fffU) << 16U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000a80U; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800U; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830U; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585cU; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840U; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848U; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1U; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844U; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8U; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80U; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400U; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000U; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000U; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000U; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000U; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000U; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584cU; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1U; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800cU; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010U; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200U; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return U32(0x3ffU) << 10U; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10U) & 0x3ffU; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_scc_rm_rtv_cb_base_r(void) -{ - return 0x00408070U; -} -static inline u32 gr_scc_rm_rtv_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f(void) -{ - return 0x8U; -} -static inline u32 gr_scc_rm_rtv_cb_size_r(void) -{ - return 0x00408074U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7fffU) << 0U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_default_f(void) -{ - return 0x800U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_db_adder_f(void) -{ - return 0x0U; -} -static inline u32 gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpcs_gcc_rm_rtv_cb_base_r(void) -{ - return 0x00419034U; -} -static inline u32 gr_gpcs_gcc_rm_rtv_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_scc_rm_gfxp_reserve_r(void) -{ - return 0x00408078U; -} -static inline u32 gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030U; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_ssync_hww_esr_r(void) -{ - return 0x00405a14U; -} -static inline u32 gr_ssync_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_ssync_hww_esr_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020U; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00U; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608U; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620U; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910U; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24U; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910U; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914U; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xfU) << 8U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920U; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32(i, 32U)); -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040U; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088U; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504608U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x00504330U; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8U) & 0xfffU; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000700U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00000fa8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return U32(0xffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000700U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419e00U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419e04U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return U32(0x1fffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0U) & 0x1fffffU; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0acU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6U) & 0x3fU; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12U; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return U32(0xfffU) << 0U; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0U) & 0xfffU; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100U; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10cU; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dcU; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x000004b0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100U; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befcU; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return U32(0x3fffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00418100U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0041814cU; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) -{ - return 0x00418198U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000cU; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_crstr_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) -{ - return (v & 0x1fU) << 0U; -} -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) -{ - return (v & 0x1fU) << 5U; -} -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) -{ - return (v & 0x1fU) << 10U; -} -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) -{ - return (v & 0x1fU) << 15U; -} -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) -{ - return (v & 0x1fU) << 20U; -} -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) -{ - return (v & 0x1fU) << 25U; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8U; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) -{ - return (v & 0x7U) << 4U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) -{ - return (v & 0x7U) << 24U; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) -{ - return (v & 0x7U) << 28U; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6cU; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004U; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008U; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980cU; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2cU; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) -{ - return 0x00504728U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void) -{ - return 0x4000000U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0cU; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450cU; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) -{ - return 0x00504704U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) -{ - return 0x00504708U; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) -{ - return 0x0050470cU; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00504710U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00504714U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) -{ - return 0x00504718U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) -{ - return 0x0050471cU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) -{ - return 0x00419e90U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) -{ - return 0x00419e94U; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) -{ - return 0x00419e80U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) -{ - return 0x00504700U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) -{ - return 0x00504730U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void) -{ - return 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void) -{ - return 0x2U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void) -{ - return 0x4U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void) -{ - return 0x5U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void) -{ - return 0x6U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void) -{ - return 0x8U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void) -{ - return 0x9U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void) -{ - return 0xbU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void) -{ - return 0xdU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void) -{ - return 0xeU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) -{ - return 0xfU; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void) -{ - return 0x10U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void) -{ - return 0x12U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void) -{ - return 0x16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void) -{ - return 0x17U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void) -{ - return 0x18U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void) -{ - return 0x19U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) -{ - return 0x20U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) -{ - return U32(0xfU) << 24U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) -{ - return 0x0050460cU; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) -{ - return 0x00504738U; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void) -{ - return 0x0050473cU; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x005043a0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419ba0U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x005043b0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419bb0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08U; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4U; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7U) << 21U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4U; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) -{ - return 0x00000005U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850U; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108U; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908U; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) -{ - return 0x2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) -{ - return 0x4U; -} -static inline u32 gr_bes_crop_debug4_r(void) -{ - return 0x0040894cU; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void) -{ - return U32(0x1U) << 18U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void) -{ - return 0x0U; -} -static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void) -{ - return 0x40000U; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958U; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020U; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0U; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) -{ - return 0x00419a00U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) -{ - return U32(0x1U) << 19U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) -{ - return 0x00419bf0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170U; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0U; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2U; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10U; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return U32(0x3U) << 3U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return U32(0x3U) << 5U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return U32(0x3U) << 28U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) -{ - return U32(0x3U) << 24U; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) -{ - return U32(0x1U) << 27U; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890U; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4U; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8U; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188acU; -} -static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) -{ - return 0x00419e84U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419bd8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return U32(0x7U) << 8U; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419ba4U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return U32(0x3U) << 11U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f(void) -{ - return 0x200000U; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f(void) -{ - return 0x0U; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return U32(0x1ffU) << 0U; -} +#define gr_intr_r() (0x00400100U) +#define gr_intr_notify_pending_f() (0x1U) +#define gr_intr_notify_reset_f() (0x1U) +#define gr_intr_semaphore_pending_f() (0x2U) +#define gr_intr_semaphore_reset_f() (0x2U) +#define gr_intr_illegal_method_pending_f() (0x10U) +#define gr_intr_illegal_method_reset_f() (0x10U) +#define gr_intr_illegal_notify_pending_f() (0x40U) +#define gr_intr_illegal_notify_reset_f() (0x40U) +#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) +#define gr_intr_firmware_method_pending_f() (0x100U) +#define gr_intr_firmware_method_reset_f() (0x100U) +#define gr_intr_illegal_class_pending_f() (0x20U) +#define gr_intr_illegal_class_reset_f() (0x20U) +#define gr_intr_fecs_error_pending_f() (0x80000U) +#define gr_intr_fecs_error_reset_f() (0x80000U) +#define gr_intr_class_error_pending_f() (0x100000U) +#define gr_intr_class_error_reset_f() (0x100000U) +#define gr_intr_exception_pending_f() (0x200000U) +#define gr_intr_exception_reset_f() (0x200000U) +#define gr_fecs_intr_r() (0x00400144U) +#define gr_class_error_r() (0x00400110U) +#define gr_class_error_code_v(r) (((r) >> 0U) & 0xffffU) +#define gr_intr_en_r() (0x0040013cU) +#define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception1_r() (0x00400118U) +#define gr_exception1_gpc_0_pending_f() (0x1U) +#define gr_exception2_r() (0x0040011cU) +#define gr_exception_en_r() (0x00400138U) +#define gr_exception_en_fe_m() (U32(0x1U) << 0U) +#define gr_exception_en_fe_enabled_f() (0x1U) +#define gr_exception_en_gpc_m() (U32(0x1U) << 24U) +#define gr_exception_en_gpc_enabled_f() (0x1000000U) +#define gr_exception_en_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_en_memfmt_enabled_f() (0x2U) +#define gr_exception_en_ds_m() (U32(0x1U) << 4U) +#define gr_exception_en_ds_enabled_f() (0x10U) +#define gr_exception_en_pd_m() (U32(0x1U) << 2U) +#define gr_exception_en_pd_enabled_f() (0x4U) +#define gr_exception_en_scc_m() (U32(0x1U) << 3U) +#define gr_exception_en_scc_enabled_f() (0x8U) +#define gr_exception_en_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_en_ssync_enabled_f() (0x20U) +#define gr_exception_en_mme_m() (U32(0x1U) << 7U) +#define gr_exception_en_mme_enabled_f() (0x80U) +#define gr_exception_en_sked_m() (U32(0x1U) << 8U) +#define gr_exception_en_sked_enabled_f() (0x100U) +#define gr_exception1_en_r() (0x00400130U) +#define gr_exception2_en_r() (0x00400134U) +#define gr_gpfifo_ctl_r() (0x00400500U) +#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) +#define gr_gpfifo_ctl_access_disabled_f() (0x0U) +#define gr_gpfifo_ctl_access_enabled_f() (0x1U) +#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) +#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) +#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) +#define gr_gpfifo_status_r() (0x00400504U) +#define gr_trapped_addr_r() (0x00400704U) +#define gr_trapped_addr_mthd_v(r) (((r) >> 2U) & 0xfffU) +#define gr_trapped_addr_subch_v(r) (((r) >> 16U) & 0x7U) +#define gr_trapped_addr_mme_generated_v(r) (((r) >> 20U) & 0x1U) +#define gr_trapped_addr_datahigh_v(r) (((r) >> 24U) & 0x1U) +#define gr_trapped_addr_priv_v(r) (((r) >> 28U) & 0x1U) +#define gr_trapped_addr_status_v(r) (((r) >> 31U) & 0x1U) +#define gr_trapped_data_lo_r() (0x00400708U) +#define gr_trapped_data_hi_r() (0x0040070cU) +#define gr_trapped_data_mme_r() (0x00400710U) +#define gr_trapped_data_mme_pc_v(r) (((r) >> 0U) & 0xfffU) +#define gr_status_r() (0x00400700U) +#define gr_status_fe_method_upper_v(r) (((r) >> 1U) & 0x1U) +#define gr_status_fe_method_lower_v(r) (((r) >> 2U) & 0x1U) +#define gr_status_fe_method_lower_idle_v() (0x00000000U) +#define gr_status_fe_gi_v(r) (((r) >> 21U) & 0x1U) +#define gr_status_mask_r() (0x00400610U) +#define gr_status_1_r() (0x00400604U) +#define gr_status_2_r() (0x00400608U) +#define gr_engine_status_r() (0x0040060cU) +#define gr_engine_status_value_busy_f() (0x1U) +#define gr_pri_be0_becs_be_exception_r() (0x00410204U) +#define gr_pri_be0_becs_be_exception_en_r() (0x00410208U) +#define gr_pri_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_pri_gpc0_gpccs_gpc_exception_en_r() (0x00502c94U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_activity_0_r() (0x00400380U) +#define gr_activity_1_r() (0x00400384U) +#define gr_activity_2_r() (0x00400388U) +#define gr_activity_4_r() (0x00400390U) +#define gr_activity_4_gpc0_s() (3U) +#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) +#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) +#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) +#define gr_activity_4_gpc0_empty_v() (0x00000000U) +#define gr_activity_4_gpc0_preempted_v() (0x00000004U) +#define gr_pri_gpc0_gcc_dbg_r() (0x00501000U) +#define gr_pri_gpcs_gcc_dbg_r() (0x00419000U) +#define gr_pri_gpcs_gcc_dbg_invalidate_m() (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cache_control_r() (0x0050433cU) +#define gr_pri_gpcs_tpcs_sm_cache_control_r() (0x00419b3cU) +#define gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m() (U32(0x1U) << 0U) +#define gr_pri_sked_activity_r() (0x00407054U) +#define gr_pri_gpc0_gpccs_gpc_activity0_r() (0x00502c80U) +#define gr_pri_gpc0_gpccs_gpc_activity1_r() (0x00502c84U) +#define gr_pri_gpc0_gpccs_gpc_activity2_r() (0x00502c88U) +#define gr_pri_gpc0_gpccs_gpc_activity3_r() (0x00502c8cU) +#define gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() (0x00504500U) +#define gr_pri_gpcs_gpccs_gpc_activity_0_r() (0x0041ac80U) +#define gr_pri_gpcs_gpccs_gpc_activity_1_r() (0x0041ac84U) +#define gr_pri_gpcs_gpccs_gpc_activity_2_r() (0x0041ac88U) +#define gr_pri_gpcs_gpccs_gpc_activity_3_r() (0x0041ac8cU) +#define gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r() (0x00419d00U) +#define gr_pri_be0_becs_be_activity0_r() (0x00410200U) +#define gr_pri_bes_becs_be_activity0_r() (0x00408a00U) +#define gr_pri_ds_mpipe_status_r() (0x00405858U) +#define gr_pri_fe_go_idle_info_r() (0x00404194U) +#define gr_pri_fe_chip_def_info_r() (0x00404030U) +#define gr_pri_fe_chip_def_info_max_veid_count_v(r) (((r) >> 0U) & 0xfffU) +#define gr_pri_fe_chip_def_info_max_veid_count_init_v() (0x00000040U) +#define gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r() (0x00504238U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() (0x00504358U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m()\ + (U32(0x1U) << 8U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m()\ + (U32(0x1U) << 9U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m()\ + (U32(0x1U) << 10U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m()\ + (U32(0x1U) << 11U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m()\ + (U32(0x1U) << 12U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m()\ + (U32(0x1U) << 13U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m()\ + (U32(0x1U) << 14U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m()\ + (U32(0x1U) << 15U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 24U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 26U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() (0x0050435cU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() (0x00504360U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r() (0x0050436cU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 8U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 10U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() (0x00504370U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() (0x00504374U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r() (0x00504638U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m()\ + (U32(0x1U) << 0U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m()\ + (U32(0x1U) << 1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m()\ + (U32(0x1U) << 2U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m()\ + (U32(0x1U) << 3U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m()\ + (U32(0x1U) << 4U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m()\ + (U32(0x1U) << 5U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m()\ + (U32(0x1U) << 6U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m()\ + (U32(0x1U) << 7U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(r)\ + (((r) >> 16U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(r)\ + (((r) >> 18U) & 0x1U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f() (0x40000000U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() (0x0050463cU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() (0x00504640U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s() (16U) +#define gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(r)\ + (((r) >> 0U) & 0xffffU) +#define gr_pri_gpc0_tpc0_tex_m_routing_r() (0x005042c4U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f() (0x0U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f() (0x1U) +#define gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f() (0x2U) +#define gr_gpc0_tpc0_mpc_hww_esr_r() (0x00504430U) +#define gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f() (0x40000000U) +#define gr_gpc0_tpc0_mpc_hww_esr_info_r() (0x00504434U) +#define gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(r) (((r) >> 0U) & 0x3fU) +#define gr_pri_be0_crop_status1_r() (0x00410134U) +#define gr_pri_bes_crop_status1_r() (0x00408934U) +#define gr_pri_be0_zrop_status_r() (0x00410048U) +#define gr_pri_be0_zrop_status2_r() (0x0041004cU) +#define gr_pri_bes_zrop_status_r() (0x00408848U) +#define gr_pri_bes_zrop_status2_r() (0x0040884cU) +#define gr_pipe_bundle_address_r() (0x00400200U) +#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) +#define gr_pipe_bundle_address_veid_f(v) (((v)&0x3fU) << 20U) +#define gr_pipe_bundle_address_veid_w() (0U) +#define gr_pipe_bundle_data_r() (0x00400204U) +#define gr_pipe_bundle_data_hi_r() (0x0040020cU) +#define gr_pipe_bundle_config_r() (0x00400208U) +#define gr_pipe_bundle_config_override_pipe_mode_disabled_f() (0x0U) +#define gr_pipe_bundle_config_override_pipe_mode_enabled_f() (0x80000000U) +#define gr_fe_hww_esr_r() (0x00404000U) +#define gr_fe_hww_esr_reset_active_f() (0x40000000U) +#define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) +#define gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() (0x00419eacU) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() (0x0050472cU) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()\ + (0x4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f()\ + (0x40U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f()\ + (0x100U) +#define gr_gpcs_tpcs_sms_hww_global_esr_r() (0x00419eb4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_r() (0x00504734U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m() (U32(0x1U) << 5U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m()\ + (U32(0x1U) << 6U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f() (0x40U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m()\ + (U32(0x1U) << 2U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f() (0x4U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m() (U32(0x1U) << 8U) +#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f() (0x100U) +#define gr_fe_go_idle_timeout_r() (0x00404154U) +#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) +#define gr_fe_go_idle_timeout_count_prod_f() (0x1800U) +#define gr_fe_object_table_r(i)\ + (nvgpu_safe_add_u32(0x00404200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fe_object_table_nvclass_v(r) (((r) >> 0U) & 0xffffU) +#define gr_fe_tpc_fs_r(i)\ + (nvgpu_safe_add_u32(0x0040a200U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pri_mme_shadow_raw_index_r() (0x00404488U) +#define gr_pri_mme_shadow_raw_index_write_trigger_f() (0x80000000U) +#define gr_pri_mme_shadow_raw_data_r() (0x0040448cU) +#define gr_mme_hww_esr_r() (0x00404490U) +#define gr_mme_hww_esr_missing_macro_data_pending_f() (0x1U) +#define gr_mme_hww_esr_illegal_opcode_pending_f() (0x4U) +#define gr_mme_hww_esr_branch_in_delay_pending_f() (0x8U) +#define gr_mme_hww_esr_inst_ram_acess_pending_f() (0x20U) +#define gr_mme_hww_esr_data_ram_access_pending_f() (0x40U) +#define gr_mme_hww_esr_illegal_mme_method_pending_f() (0x80U) +#define gr_mme_hww_esr_dma_dram_access_pending_f() (0x10000U) +#define gr_mme_hww_esr_dma_read_pb_pending_f() (0x20000U) +#define gr_mme_hww_esr_dma_illegal_fifo_pending_f() (0x40000U) +#define gr_mme_hww_esr_dma_read_overflow_pending_f() (0x80000U) +#define gr_mme_hww_esr_dma_fifo_resized_pending_f() (0x100000U) +#define gr_mme_hww_esr_reset_active_f() (0x40000000U) +#define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) +#define gr_mme_hww_esr_info_pc_valid_v(r) (((r) >> 28U) & 0x1U) +#define gr_mme_hww_esr_info2_r() (0x0040449cU) +#define gr_mme_hww_esr_info3_r() (0x004044a8U) +#define gr_mme_hww_esr_info4_r() (0x004044acU) +#define gr_memfmt_hww_esr_r() (0x00404600U) +#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) +#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) +#define gr_fecs_cpuctl_r() (0x00409100U) +#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_cpuctl_alias_r() (0x00409130U) +#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_dmactl_r() (0x0040910cU) +#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_fecs_os_r() (0x00409080U) +#define gr_fecs_idlestate_r() (0x0040904cU) +#define gr_fecs_mailbox0_r() (0x00409040U) +#define gr_fecs_mailbox1_r() (0x00409044U) +#define gr_fecs_irqstat_r() (0x00409008U) +#define gr_fecs_irqmode_r() (0x0040900cU) +#define gr_fecs_irqmask_r() (0x00409018U) +#define gr_fecs_irqdest_r() (0x0040901cU) +#define gr_fecs_curctx_r() (0x00409050U) +#define gr_fecs_nxtctx_r() (0x00409054U) +#define gr_fecs_engctl_r() (0x004090a4U) +#define gr_fecs_debug1_r() (0x00409090U) +#define gr_fecs_debuginfo_r() (0x00409094U) +#define gr_fecs_icd_cmd_r() (0x00409200U) +#define gr_fecs_icd_cmd_opc_s() (4U) +#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) +#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) +#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define gr_fecs_icd_rdata_r() (0x0040920cU) +#define gr_fecs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmemc_offs_s() (6U) +#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) +#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_fecs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_fecs_dmatrfbase_r() (0x00409110U) +#define gr_fecs_dmatrfmoffs_r() (0x00409114U) +#define gr_fecs_dmatrffboffs_r() (0x0040911cU) +#define gr_fecs_dmatrfcmd_r() (0x00409118U) +#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define gr_fecs_bootvec_r() (0x00409104U) +#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_irqsset_r() (0x00409000U) +#define gr_fecs_falcon_hwcfg_r() (0x00409108U) +#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) +#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) +#define gr_fecs_falcon_rm_r() (0x00409084U) +#define gr_fecs_current_ctx_r() (0x00409b00U) +#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_current_ctx_target_s() (2U) +#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) +#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) +#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) +#define gr_fecs_current_ctx_valid_s() (1U) +#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_current_ctx_valid_false_f() (0x0U) +#define gr_fecs_method_data_r() (0x00409500U) +#define gr_fecs_method_push_r() (0x00409504U) +#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) +#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) +#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) +#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) +#define gr_fecs_method_push_adr_wfi_golden_save_v() (0x00000009U) +#define gr_fecs_method_push_adr_restore_golden_v() (0x00000015U) +#define gr_fecs_method_push_adr_discover_zcull_image_size_v() (0x00000016U) +#define gr_fecs_method_push_adr_discover_pm_image_size_v() (0x00000025U) +#define gr_fecs_method_push_adr_discover_reglist_image_size_v() (0x00000030U) +#define gr_fecs_method_push_adr_set_reglist_bind_instance_v() (0x00000031U) +#define gr_fecs_method_push_adr_set_reglist_virtual_address_v() (0x00000032U) +#define gr_fecs_method_push_adr_stop_ctxsw_v() (0x00000038U) +#define gr_fecs_method_push_adr_start_ctxsw_v() (0x00000039U) +#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) +#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU) +#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) +#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\ + (0x0000003aU) +#define gr_fecs_host_int_status_r() (0x00409c18U) +#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) +#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) +#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) +#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) +#define gr_fecs_host_int_clear_r() (0x00409c20U) +#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) +#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) +#define gr_fecs_host_int_enable_r() (0x00409c24U) +#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) +#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) +#define gr_fecs_host_int_enable_umimp_firmware_method_enable_f() (0x20000U) +#define gr_fecs_host_int_enable_umimp_illegal_method_enable_f() (0x40000U) +#define gr_fecs_host_int_enable_watchdog_enable_f() (0x80000U) +#define gr_fecs_ctxsw_reset_ctl_r() (0x00409614U) +#define gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f() (0x10U) +#define gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f() (0x20U) +#define gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f() (0x40U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() (0x100U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) +#define gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f() (0x400U) +#define gr_fecs_ctx_state_store_major_rev_id_r() (0x0040960cU) +#define gr_fecs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) +#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) +#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) +#define gr_fecs_ctxsw_mailbox_set_r(i)\ + (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_ctxsw_mailbox_clear_r(i)\ + (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fecs_fs_r() (0x00409604U) +#define gr_fecs_fs_num_available_gpcs_s() (5U) +#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) +#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_fs_num_available_fbps_s() (5U) +#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) +#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) +#define gr_fecs_cfg_r() (0x00409620U) +#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_fecs_rc_lanes_r() (0x00409880U) +#define gr_fecs_rc_lanes_num_chains_s() (6U) +#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_fecs_ctxsw_status_1_r() (0x00409400U) +#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) +#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) +#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) +#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) +#define gr_fecs_new_ctx_r() (0x00409b04U) +#define gr_fecs_new_ctx_ptr_s() (28U) +#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_new_ctx_target_s() (2U) +#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) +#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_new_ctx_valid_s() (1U) +#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) +#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) +#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) +#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) +#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) +#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) +#define gr_fecs_arb_ctx_ptr_target_s() (2U) +#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) +#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) +#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) +#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) +#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) +#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) +#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) +#define gr_gpc0_gpccs_ctxsw_status_gpc_0_r() (0x00502c04U) +#define gr_gpc0_gpccs_ctxsw_status_1_r() (0x00502400U) +#define gr_fecs_ctxsw_idlestate_r() (0x00409420U) +#define gr_fecs_feature_override_ecc_r() (0x00409658U) +#define gr_fecs_feature_override_ecc_sm_lrf_override_v(r) (((r) >> 3U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_override_v(r) (((r) >> 15U) & 0x1U) +#define gr_fecs_feature_override_ecc_sm_lrf_v(r) (((r) >> 0U) & 0x1U) +#define gr_fecs_feature_override_ecc_ltc_v(r) (((r) >> 12U) & 0x1U) +#define gr_gpc0_gpccs_ctxsw_idlestate_r() (0x00502420U) +#define gr_rstr2d_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) +#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_pd_hww_esr_r() (0x00406018U) +#define gr_pd_hww_esr_reset_active_f() (0x40000000U) +#define gr_pd_hww_esr_en_enable_f() (0x80000000U) +#define gr_pd_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) +#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) +#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) +#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) +#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) +#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) +#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) +#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) +#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) +#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) +#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) +#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) +#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) +#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) +#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) +#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) +#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) +#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000a80U) +#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) +#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) +#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000a80U) +#define gr_pd_dist_skip_table_r(i)\ + (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) +#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) +#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) +#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) +#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) +#define gr_ds_debug_r() (0x00405800U) +#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) +#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) +#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) +#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) +#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) +#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) +#define gr_ds_hww_esr_r() (0x00405840U) +#define gr_ds_hww_esr_reset_s() (1U) +#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) +#define gr_ds_hww_esr_2_r() (0x00405848U) +#define gr_ds_hww_esr_2_reset_s() (1U) +#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) +#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) +#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) +#define gr_ds_hww_esr_2_reset_task_f() (0x40000000U) +#define gr_ds_hww_esr_2_en_enabled_f() (0x80000000U) +#define gr_ds_hww_report_mask_r() (0x00405844U) +#define gr_ds_hww_report_mask_sph0_err_report_f() (0x1U) +#define gr_ds_hww_report_mask_sph1_err_report_f() (0x2U) +#define gr_ds_hww_report_mask_sph2_err_report_f() (0x4U) +#define gr_ds_hww_report_mask_sph3_err_report_f() (0x8U) +#define gr_ds_hww_report_mask_sph4_err_report_f() (0x10U) +#define gr_ds_hww_report_mask_sph5_err_report_f() (0x20U) +#define gr_ds_hww_report_mask_sph6_err_report_f() (0x40U) +#define gr_ds_hww_report_mask_sph7_err_report_f() (0x80U) +#define gr_ds_hww_report_mask_sph8_err_report_f() (0x100U) +#define gr_ds_hww_report_mask_sph9_err_report_f() (0x200U) +#define gr_ds_hww_report_mask_sph10_err_report_f() (0x400U) +#define gr_ds_hww_report_mask_sph11_err_report_f() (0x800U) +#define gr_ds_hww_report_mask_sph12_err_report_f() (0x1000U) +#define gr_ds_hww_report_mask_sph13_err_report_f() (0x2000U) +#define gr_ds_hww_report_mask_sph14_err_report_f() (0x4000U) +#define gr_ds_hww_report_mask_sph15_err_report_f() (0x8000U) +#define gr_ds_hww_report_mask_sph16_err_report_f() (0x10000U) +#define gr_ds_hww_report_mask_sph17_err_report_f() (0x20000U) +#define gr_ds_hww_report_mask_sph18_err_report_f() (0x40000U) +#define gr_ds_hww_report_mask_sph19_err_report_f() (0x80000U) +#define gr_ds_hww_report_mask_sph20_err_report_f() (0x100000U) +#define gr_ds_hww_report_mask_sph21_err_report_f() (0x200000U) +#define gr_ds_hww_report_mask_sph22_err_report_f() (0x400000U) +#define gr_ds_hww_report_mask_sph23_err_report_f() (0x800000U) +#define gr_ds_hww_report_mask_2_r() (0x0040584cU) +#define gr_ds_hww_report_mask_2_sph24_err_report_f() (0x1U) +#define gr_ds_num_tpc_per_gpc_r(i)\ + (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_scc_bundle_cb_base_r() (0x00408004U) +#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_bundle_cb_size_r() (0x00408008U) +#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U) +#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) +#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_scc_pagepool_base_r() (0x0040800cU) +#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) +#define gr_scc_pagepool_r() (0x00408010U) +#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) +#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) +#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) +#define gr_scc_pagepool_max_valid_pages_s() (10U) +#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) +#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) +#define gr_scc_pagepool_valid_true_f() (0x80000000U) +#define gr_scc_rm_rtv_cb_base_r() (0x00408070U) +#define gr_scc_rm_rtv_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f() (0x8U) +#define gr_scc_rm_rtv_cb_size_r() (0x00408074U) +#define gr_scc_rm_rtv_cb_size_div_256b_f(v) (((v)&0x7fffU) << 0U) +#define gr_scc_rm_rtv_cb_size_div_256b_byte_granularity_v() (0x00000100U) +#define gr_scc_rm_rtv_cb_size_div_256b_init_f() (0x0U) +#define gr_scc_rm_rtv_cb_size_div_256b_default_f() (0x800U) +#define gr_scc_rm_rtv_cb_size_div_256b_db_adder_f() (0x0U) +#define gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f() (0x20U) +#define gr_gpcs_gcc_rm_rtv_cb_base_r() (0x00419034U) +#define gr_gpcs_gcc_rm_rtv_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_scc_rm_gfxp_reserve_r() (0x00408078U) +#define gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(v) (((v)&0x1ffU) << 0U) +#define gr_scc_hww_esr_r() (0x00408030U) +#define gr_scc_hww_esr_reset_active_f() (0x40000000U) +#define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_ssync_hww_esr_r() (0x00405a14U) +#define gr_ssync_hww_esr_reset_active_f() (0x40000000U) +#define gr_ssync_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) +#define gr_sked_hww_esr_en_r() (0x00407024U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m()\ + (U32(0x1U) << 25U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() (0x0U) +#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()\ + (0x2000000U) +#define gr_cwd_fs_r() (0x00405b00U) +#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) +#define gr_cwd_gpc_tpc_id_r(i)\ + (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) +#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) +#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) +#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) +#define gr_cwd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_cwd_sm_id__size_1_v() (0x00000010U) +#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) +#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) +#define gr_gpc0_fs_gpc_r() (0x00502608U) +#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) +#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) +#define gr_gpc0_cfg_r() (0x00502620U) +#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpccs_rc_lanes_r() (0x00502880U) +#define gr_gpccs_rc_lanes_num_chains_s() (6U) +#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) +#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_rc_lane_size_r() (0x00502910U) +#define gr_gpccs_rc_lane_size_v_s() (24U) +#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) +#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) +#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) +#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) +#define gr_gpc0_zcull_fs_r() (0x00500910U) +#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) +#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) +#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ + (((v)&0xfU) << 0U) +#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) +#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) +#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) +#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) +#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_zcull_zcsize_r(i)\ + (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) +#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) +#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) +#define gr_gpc0_gpm_pd_sm_id_r(i)\ + (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ + (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) +#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_r() (0x00504608U) +#define gr_gpc0_tpc0_sm_cfg_tpc_id_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_tpc0_sm_cfg_tpc_id_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm_arch_r() (0x00504330U) +#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) +#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU) +#define gr_gpc0_tpc0_sm_arch_sm_version_v(r) (((r) >> 20U) & 0xfffU) +#define gr_gpc0_ppc0_pes_vsc_strem_r() (0x00503018U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) +#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000700U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00000fa8U) +#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) +#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) +#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ + (((v)&0x3fffffU) << 0U) +#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000700U) +#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U) +#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419e04U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) +#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) +#define gr_gpccs_falcon_addr_r() (0x0041a0acU) +#define gr_gpccs_falcon_addr_lsb_s() (6U) +#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) +#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) +#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_msb_s() (6U) +#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) +#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) +#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) +#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) +#define gr_gpccs_falcon_addr_ext_s() (12U) +#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) +#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) +#define gr_gpccs_cpuctl_r() (0x0041a100U) +#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define gr_gpccs_dmactl_r() (0x0041a10cU) +#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define gr_gpccs_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) +#define gr_gpccs_imemt__size_1_v() (0x00000004U) +#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) +#define gr_gpccs_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define gr_gpccs_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define gr_gpccs_ctxsw_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U) +#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U) +#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) +#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) +#define gr_gpcs_swdx_bundle_cb_size_valid_false_f() (0x0U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) +#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) +#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x000004b0U) +#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ + (0x00000100U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) +#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) +#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ + (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) +#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ + (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ + (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ + (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ + (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00418100U) +#define gr_gpcs_swdx_dss_zbc_z_r(i)\ + (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0041814cU) +#define gr_gpcs_swdx_dss_zbc_s_r(i)\ + (nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_swdx_dss_zbc_s_val_f(v) (((v)&0xffU) << 0U) +#define gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() (0x00418198U) +#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) +#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) +#define gr_crstr_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_crstr_gpc_map_tile0_f(v) (((v)&0x1fU) << 0U) +#define gr_crstr_gpc_map_tile1_f(v) (((v)&0x1fU) << 5U) +#define gr_crstr_gpc_map_tile2_f(v) (((v)&0x1fU) << 10U) +#define gr_crstr_gpc_map_tile3_f(v) (((v)&0x1fU) << 15U) +#define gr_crstr_gpc_map_tile4_f(v) (((v)&0x1fU) << 20U) +#define gr_crstr_gpc_map_tile5_f(v) (((v)&0x1fU) << 25U) +#define gr_crstr_map_table_cfg_r() (0x00418bb8U) +#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_r(i)\ + (nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(v) (((v)&0x7U) << 0U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(v) (((v)&0x7U) << 4U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(v) (((v)&0x7U) << 8U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(v) (((v)&0x7U) << 12U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(v) (((v)&0x7U) << 16U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(v) (((v)&0x7U) << 20U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(v) (((v)&0x7U) << 24U) +#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(v) (((v)&0x7U) << 28U) +#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) +#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) +#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) +#define gr_gpcs_gcc_pagepool_r() (0x00419008U) +#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) +#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) +#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) +#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) +#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) +#define gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() (0x00419ea8U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() (0x00504728U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f()\ + (0x4U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f()\ + (0x20U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() (0x40U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f()\ + (0x100U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f()\ + (0x200U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f()\ + (0x800U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f() (0x2000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f() (0x4000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f()\ + (0x8000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f()\ + (0x10000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f()\ + (0x40000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f()\ + (0x800000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f()\ + (0x400000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f()\ + (0x4000000U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_r() (0x00419d0cU) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_r() (0x0050450cU) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U) +#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) +#define gr_gpcs_gpccs_gpc_exception_en_gcc_f(v) (((v)&0x1U) << 2U) +#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) +#define gr_gpcs_gpccs_gpc_exception_en_gpccs_f(v) (((v)&0x1U) << 14U) +#define gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(v) (((v)&0x1U) << 15U) +#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) +#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) +#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) +#define gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_r() (0x00504508U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v() (0x00000001U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m() (U32(0x1U) << 4U) +#define gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f() (0x10U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_r() (0x00504704U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m() (U32(0x1U) << 0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v() (0x00000001U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f() (0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v() (0x00000000U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f() (0x80000000U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m() (U32(0x1U) << 3U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f() (0x8U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f() (0x0U) +#define gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f() (0x40000000U) +#define gr_gpc0_tpc0_sm0_warp_valid_mask_0_r() (0x00504708U) +#define gr_gpc0_tpc0_sm0_warp_valid_mask_1_r() (0x0050470cU) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r() (0x00504710U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r() (0x00504714U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r() (0x00504718U) +#define gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r() (0x0050471cU) +#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r() (0x00419e90U) +#define gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r() (0x00419e94U) +#define gr_gpcs_tpcs_sms_dbgr_status0_r() (0x00419e80U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_r() (0x00504700U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(r) (((r) >> 4U) & 0x1U) +#define gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v() (0x00000001U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_r() (0x00504730U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(r) (((r) >> 0U) & 0xffffU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v() (0x00000000U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f() (0x0U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f() (0x1U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f() (0x2U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f() (0x4U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f() (0x5U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f() (0x6U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f() (0x8U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f() (0x9U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f() (0xbU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f() (0xdU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f() (0xeU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f() (0xfU) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f() (0x10U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f() (0x12U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f() (0x16U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f() (0x17U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f() (0x18U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f() (0x19U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f() (0x20U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m() (U32(0xffU) << 16U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m() (U32(0xfU) << 24U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f() (0x0U) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r() (0x0050460cU) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(r) (((r) >> 0U) & 0x1U) +#define gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(r) (((r) >> 1U) & 0x1U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() (0x00504738U) +#define gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() (0x0050473cU) +#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x005043a0U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419ba0U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) +#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) +#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x005043b0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419bb0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) +#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) +#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) +#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) +#define gr_ppcs_wwdx_map_gpc_map_r(i)\ + (nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) +#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ + (((v)&0x1fU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ + (((v)&0x7U) << 21U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) +#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_r(i)\ + (nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32((i), 4U))) +#define gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v() (0x00000005U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(v) (((v)&0xffU) << 0U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(v) (((v)&0xffU) << 8U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(v) (((v)&0xffU) << 16U) +#define gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(v) (((v)&0xffU) << 24U) +#define gr_bes_zrop_settings_r() (0x00408850U) +#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_be0_crop_debug3_r() (0x00410108U) +#define gr_bes_crop_debug3_r() (0x00408908U) +#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) +#define gr_bes_crop_debug3_blendopt_read_suppress_m() (U32(0x1U) << 1U) +#define gr_bes_crop_debug3_blendopt_read_suppress_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_read_suppress_enabled_f() (0x2U) +#define gr_bes_crop_debug3_blendopt_fill_override_m() (U32(0x1U) << 2U) +#define gr_bes_crop_debug3_blendopt_fill_override_disabled_f() (0x0U) +#define gr_bes_crop_debug3_blendopt_fill_override_enabled_f() (0x4U) +#define gr_bes_crop_debug4_r() (0x0040894cU) +#define gr_bes_crop_debug4_clamp_fp_blend_m() (U32(0x1U) << 18U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) +#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) +#define gr_bes_crop_settings_r() (0x00408958U) +#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) +#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) +#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) +#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) +#define gr_zcull_subregion_qty_v() (0x00000010U) +#define gr_gpcs_tpcs_tex_in_dbg_r() (0x00419a00U) +#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(v) (((v)&0x1U) << 19U) +#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m() (U32(0x1U) << 19U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_r() (0x00419bf0U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(v) (((v)&0x1U) << 5U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m() (U32(0x1U) << 5U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(v) (((v)&0x1U) << 10U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m() (U32(0x1U) << 10U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m() (U32(0x1U) << 28U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f() (0x0U) +#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f() (0x10000000U) +#define gr_fe_pwr_mode_r() (0x00404170U) +#define gr_fe_pwr_mode_mode_auto_f() (0x0U) +#define gr_fe_pwr_mode_mode_force_on_f() (0x2U) +#define gr_fe_pwr_mode_req_v(r) (((r) >> 4U) & 0x1U) +#define gr_fe_pwr_mode_req_send_f() (0x10U) +#define gr_fe_pwr_mode_req_done_v() (0x00000000U) +#define gr_gpcs_pri_mmu_ctrl_r() (0x00418880U) +#define gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() (U32(0x1U) << 0U) +#define gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() (U32(0x1U) << 11U) +#define gr_gpcs_pri_mmu_ctrl_vol_fault_m() (U32(0x1U) << 1U) +#define gr_gpcs_pri_mmu_ctrl_comp_fault_m() (U32(0x1U) << 2U) +#define gr_gpcs_pri_mmu_ctrl_miss_gran_m() (U32(0x3U) << 3U) +#define gr_gpcs_pri_mmu_ctrl_cache_mode_m() (U32(0x3U) << 5U) +#define gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() (U32(0x3U) << 28U) +#define gr_gpcs_pri_mmu_ctrl_mmu_vol_m() (U32(0x1U) << 30U) +#define gr_gpcs_pri_mmu_ctrl_mmu_disable_m() (U32(0x1U) << 31U) +#define gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) +#define gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m()\ + (U32(0x1U) << 27U) +#define gr_gpcs_pri_mmu_pm_unit_mask_r() (0x00418890U) +#define gr_gpcs_pri_mmu_pm_req_mask_r() (0x00418894U) +#define gr_gpcs_pri_mmu_debug_ctrl_r() (0x004188b0U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) +#define gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) +#define gr_gpcs_pri_mmu_debug_wr_r() (0x004188b4U) +#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) +#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) +#define gr_gpcs_tpcs_sms_dbgr_control0_r() (0x00419e84U) +#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) +#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) +#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) +#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419bd8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ + (((v)&0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) +#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ + (0x100U) +#define gr_gpcs_tpcs_sm_disp_ctrl_r() (0x00419ba4U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) +#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) +#define gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m() (U32(0x1U) << 21U) +#define gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f() (0x200000U) +#define gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f() (0x0U) +#define gr_gpcs_tc_debug0_r() (0x00418708U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0x1ffU) << 0U) +#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrl_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrl_tu104.h index 17babb377..ee7253da2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrl_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrl_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,276 +59,75 @@ #include #include -static inline u32 ioctrl_reset_r(void) -{ - return 0x00000140U; -} -static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void) -{ - return 0x00000008U; -} -static inline u32 ioctrl_reset_linkreset_f(u32 v) -{ - return (v & 0x3U) << 8U; -} -static inline u32 ioctrl_reset_linkreset_m(void) -{ - return U32(0x3U) << 8U; -} -static inline u32 ioctrl_reset_linkreset_v(u32 r) -{ - return (r >> 8U) & 0x3U; -} -static inline u32 ioctrl_debug_reset_r(void) -{ - return 0x00000144U; -} -static inline u32 ioctrl_debug_reset_link_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ioctrl_debug_reset_link_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ioctrl_debug_reset_link_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ioctrl_debug_reset_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_debug_reset_common_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 ioctrl_debug_reset_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_clock_control_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ioctrl_clock_control__size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 ioctrl_clock_control_clkdis_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrl_clock_control_clkdis_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_top_intr_0_status_r(void) -{ - return 0x00000200U; -} -static inline u32 ioctrl_top_intr_0_status_link_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 ioctrl_top_intr_0_status_link_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 ioctrl_top_intr_0_status_common_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 ioctrl_top_intr_0_status_common_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_r(void) -{ - return 0x00000220U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_r(void) -{ - return 0x00000224U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000240U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000244U, nvgpu_safe_mult_u32(i, 20U)); -} -static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} +#define ioctrl_reset_r() (0x00000140U) +#define ioctrl_reset_sw_post_reset_delay_microseconds_v() (0x00000008U) +#define ioctrl_reset_linkreset_f(v) (((v)&0x3U) << 8U) +#define ioctrl_reset_linkreset_m() (U32(0x3U) << 8U) +#define ioctrl_reset_linkreset_v(r) (((r) >> 8U) & 0x3U) +#define ioctrl_debug_reset_r() (0x00000144U) +#define ioctrl_debug_reset_link_f(v) (((v)&0x3U) << 0U) +#define ioctrl_debug_reset_link_m() (U32(0x3U) << 0U) +#define ioctrl_debug_reset_link_v(r) (((r) >> 0U) & 0x3U) +#define ioctrl_debug_reset_common_f(v) (((v)&0x1U) << 31U) +#define ioctrl_debug_reset_common_m() (U32(0x1U) << 31U) +#define ioctrl_debug_reset_common_v(r) (((r) >> 31U) & 0x1U) +#define ioctrl_clock_control_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) +#define ioctrl_clock_control__size_1_v() (0x00000002U) +#define ioctrl_clock_control_clkdis_f(v) (((v)&0x1U) << 0U) +#define ioctrl_clock_control_clkdis_m() (U32(0x1U) << 0U) +#define ioctrl_clock_control_clkdis_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_top_intr_0_status_r() (0x00000200U) +#define ioctrl_top_intr_0_status_link_f(v) (((v)&0x3U) << 0U) +#define ioctrl_top_intr_0_status_link_m() (U32(0x3U) << 0U) +#define ioctrl_top_intr_0_status_link_v(r) (((r) >> 0U) & 0x3U) +#define ioctrl_top_intr_0_status_common_f(v) (((v)&0x1U) << 31U) +#define ioctrl_top_intr_0_status_common_m() (U32(0x1U) << 31U) +#define ioctrl_top_intr_0_status_common_v(r) (((r) >> 31U) & 0x1U) +#define ioctrl_common_intr_0_mask_r() (0x00000220U) +#define ioctrl_common_intr_0_mask_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_common_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_common_intr_0_mask_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_common_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_common_intr_0_mask_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_common_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_common_intr_0_mask_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_common_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_common_intr_0_mask_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_common_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U) +#define ioctrl_common_intr_0_status_r() (0x00000224U) +#define ioctrl_common_intr_0_status_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_common_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_common_intr_0_status_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_common_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_common_intr_0_status_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_common_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_common_intr_0_status_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_common_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_common_intr_0_status_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_common_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U) +#define ioctrl_link_intr_0_mask_r(i)\ + (nvgpu_safe_add_u32(0x00000240U, nvgpu_safe_mult_u32((i), 20U))) +#define ioctrl_link_intr_0_mask_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_link_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_link_intr_0_mask_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_link_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_link_intr_0_mask_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_link_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_link_intr_0_mask_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_link_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_link_intr_0_mask_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_link_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U) +#define ioctrl_link_intr_0_status_r(i)\ + (nvgpu_safe_add_u32(0x00000244U, nvgpu_safe_mult_u32((i), 20U))) +#define ioctrl_link_intr_0_status_fatal_f(v) (((v)&0x1U) << 0U) +#define ioctrl_link_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U) +#define ioctrl_link_intr_0_status_nonfatal_f(v) (((v)&0x1U) << 1U) +#define ioctrl_link_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define ioctrl_link_intr_0_status_correctable_f(v) (((v)&0x1U) << 2U) +#define ioctrl_link_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U) +#define ioctrl_link_intr_0_status_intra_f(v) (((v)&0x1U) << 3U) +#define ioctrl_link_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U) +#define ioctrl_link_intr_0_status_intrb_f(v) (((v)&0x1U) << 4U) +#define ioctrl_link_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrlmif_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrlmif_tu104.h index edc8bed26..2d81cae02 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrlmif_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ioctrlmif_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,268 +59,76 @@ #include #include -static inline u32 ioctrlmif_rx_err_contain_en_0_r(void) -{ - return 0x00000e0cU; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f(void) -{ - return 0x10U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_r(void) -{ - return 0x00000e04U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_r(void) -{ - return 0x00000e00U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 ioctrlmif_rx_err_first_0_r(void) -{ - return 0x00000e14U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_r(void) -{ - return 0x00000a90U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f(void) -{ - return 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v(void) -{ - return 0x00000001U; -} -static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f(void) -{ - return 0x2U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_r(void) -{ - return 0x00000a88U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_r(void) -{ - return 0x00000e08U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_r(void) -{ - return 0x00000a84U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 ioctrlmif_tx_err_first_0_r(void) -{ - return 0x00000a98U; -} -static inline u32 ioctrlmif_tx_ctrl_buffer_ready_r(void) -{ - return 0x00000a7cU; -} -static inline u32 ioctrlmif_rx_ctrl_buffer_ready_r(void) -{ - return 0x00000dfcU; -} +#define ioctrlmif_rx_err_contain_en_0_r() (0x00000e0cU) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(r)\ + (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(r)\ + (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v() (0x00000001U) +#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f() (0x10U) +#define ioctrlmif_rx_err_log_en_0_r() (0x00000e04U) +#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_report_en_0_r() (0x00000e08U) +#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(r)\ + (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_status_0_r() (0x00000e00U) +#define ioctrlmif_rx_err_status_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) +#define ioctrlmif_rx_err_status_0_rxramdataparityerr_m() (U32(0x1U) << 3U) +#define ioctrlmif_rx_err_status_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U) +#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) +#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) +#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) +#define ioctrlmif_rx_err_first_0_r() (0x00000e14U) +#define ioctrlmif_tx_err_contain_en_0_r() (0x00000a90U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(r)\ + (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v() (0x00000001U) +#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f() (0x1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(r)\ + (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v() (0x00000001U) +#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f() (0x2U) +#define ioctrlmif_tx_err_log_en_0_r() (0x00000a88U) +#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_report_en_0_r() (0x00000e08U) +#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(r)\ + (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_status_0_r() (0x00000a84U) +#define ioctrlmif_tx_err_status_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) +#define ioctrlmif_tx_err_status_0_txramdataparityerr_m() (U32(0x1U) << 0U) +#define ioctrlmif_tx_err_status_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U) +#define ioctrlmif_tx_err_status_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) +#define ioctrlmif_tx_err_status_0_txramhdrparityerr_m() (U32(0x1U) << 1U) +#define ioctrlmif_tx_err_status_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) +#define ioctrlmif_tx_err_first_0_r() (0x00000a98U) +#define ioctrlmif_tx_ctrl_buffer_ready_r() (0x00000a7cU) +#define ioctrlmif_rx_ctrl_buffer_ready_r() (0x00000dfcU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ltc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ltc_tu104.h index e9a2df654..0be9a5344 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ltc_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ltc_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,560 +59,173 @@ #include #include -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000U; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffffU; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200U; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400U; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200U; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318U; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4U; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046cU; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0xfffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x000fffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278U; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000bU; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0U) & 0x3ffffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27cU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param_amap_divide_rounding_v(u32 r) -{ - return (r >> 10U) & 0x3U; -} -static inline u32 ltc_ltcs_ltss_cbc_param_amap_swizzle_rounding_v(u32 r) -{ - return (r >> 12U) & 0x3U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4U; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_num_cache_lines_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_cache_line_size_v(u32 r) -{ - return (r >> 24U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(u32 r) -{ - return (r >> 28U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2acU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34cU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) -{ - return 0x0017e204U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) -{ - return 8U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20cU; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100U; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200U; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000U; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051cU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8U) & 0xfU; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1U; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058cU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0U) & 0xffffU; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16U) & 0x1fU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_1_r(void) -{ - return 0x0017e39cU; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_disabled_f(void) -{ - return 0x0U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f(void) -{ - return 0x0U; -} +#define ltc_pltcg_base_v() (0x00140000U) +#define ltc_pltcg_extent_v() (0x0017ffffU) +#define ltc_ltc0_ltss_v() (0x00140200U) +#define ltc_ltc0_lts0_v() (0x00140400U) +#define ltc_ltcs_ltss_v() (0x0017e200U) +#define ltc_ltcs_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltc0_lts0_dstg_cfg0_r() (0x00140518U) +#define ltc_ltcs_ltss_dstg_cfg0_r() (0x0017e318U) +#define ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m() (U32(0x1U) << 15U) +#define ltc_ltc0_lts0_tstg_cfg1_r() (0x00140494U) +#define ltc_ltc0_lts0_tstg_cfg1_active_ways_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_v(r) (((r) >> 16U) & 0x3U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v() (0x00000000U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v() (0x00000001U) +#define ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v() (0x00000002U) +#define ltc_ltcs_ltss_cbc_ctrl1_r() (0x0017e26cU) +#define ltc_ltcs_ltss_cbc_ctrl1_clean_active_f() (0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f() (0x2U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_v(r) (((r) >> 2U) & 0x1U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_v() (0x00000001U) +#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) +#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) +#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) +#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0xfffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0xfffffU) << 0U) +#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x000fffffU) +#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) +#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) +#define ltc_ltcs_ltss_cbc_base_address_v(r) (((r) >> 0U) & 0x3ffffffU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs__v(r) (((r) >> 0U) & 0x1fU) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(v)\ + (((v)&0x1U) << 24U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(r)\ + (((r) >> 24U) & 0x1U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(v) (((v)&0x1U) << 25U) +#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(r) (((r) >> 25U) & 0x1U) +#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U) +#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U) +#define ltc_ltcs_ltss_cbc_param_bytes_per_comptagline_per_slice_v(r)\ + (((r) >> 0U) & 0x3ffU) +#define ltc_ltcs_ltss_cbc_param_amap_divide_rounding_v(r) (((r) >> 10U) & 0x3U) +#define ltc_ltcs_ltss_cbc_param_amap_swizzle_rounding_v(r) (((r) >> 12U) & 0x3U) +#define ltc_ltcs_ltss_cbc_param2_r() (0x0017e3f4U) +#define ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(r)\ + (((r) >> 0U) & 0xffffU) +#define ltc_ltcs_ltss_cbc_param2_num_cache_lines_v(r) (((r) >> 16U) & 0xffU) +#define ltc_ltcs_ltss_cbc_param2_cache_line_size_v(r) (((r) >> 24U) & 0xfU) +#define ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU) +#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) +#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ + (((v)&0x1fU) << 16U) +#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) +#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ + (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) +#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ + (((v)&0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ + (U32(0xffffffffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffffffffU) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r() (0x0017e204U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s() (8U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(v)\ + (((v)&0xffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m() (U32(0xffU) << 0U) +#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(r)\ + (((r) >> 0U) & 0xffU) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_r() (0x0017e2b0U) +#define ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f() (0x10000000U) +#define ltc_ltcs_ltss_g_elpg_r() (0x0017e214U) +#define ltc_ltcs_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltc0_ltss_g_elpg_r() (0x00140214U) +#define ltc_ltc0_ltss_g_elpg_flush_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_g_elpg_flush_pending_f() (0x1U) +#define ltc_ltcs_ltss_intr_r() (0x0017e20cU) +#define ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() (0x100U) +#define ltc_ltcs_ltss_intr_ecc_ded_error_pending_f() (0x200U) +#define ltc_ltcs_ltss_intr_en_evicted_cb_m() (U32(0x1U) << 20U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_m() (U32(0x1U) << 21U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f() (0x200000U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f() (0x0U) +#define ltc_ltcs_ltss_intr_en_illegal_compstat_access_m() (U32(0x1U) << 30U) +#define ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() (0x1000000U) +#define ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f() (0x2000000U) +#define ltc_ltc0_lts0_intr_r() (0x0014040cU) +#define ltc_ltc0_lts0_dstg_ecc_report_r() (0x0014051cU) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_m() (U32(0xffU) << 0U) +#define ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(r) (((r) >> 0U) & 0xffU) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_m() (U32(0xffU) << 16U) +#define ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(r) (((r) >> 16U) & 0xffU) +#define ltc_ltcs_ltss_tstg_cmgmt0_r() (0x0017e2a0U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v()\ + (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f()\ + (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f()\ + (0x40000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_r() (0x0017e2a4U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(r)\ + (((r) >> 8U) & 0xfU) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v() (0x00000003U) +#define ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() (0x300U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(r)\ + (((r) >> 16U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() (0x10000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(r)\ + (((r) >> 28U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() (0x10000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(r)\ + (((r) >> 29U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v()\ + (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f()\ + (0x20000000U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(r)\ + (((r) >> 30U) & 0x1U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v() (0x00000001U) +#define ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f() (0x40000000U) +#define ltc_ltc0_ltss_tstg_cmgmt0_r() (0x001402a0U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f() (0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_r() (0x001402a4U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_v(r) (((r) >> 0U) & 0x1U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v() (0x00000001U) +#define ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f() (0x1U) +#define ltc_ltc0_lts0_tstg_info_1_r() (0x0014058cU) +#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU) +#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU) +#define ltc_ltcs_ltss_tstg_set_mgmt_1_r() (0x0017e39cU) +#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m() (U32(0x1U) << 7U) +#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_disabled_f() (0x0U) +#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m() (U32(0x1U) << 29U) +#define ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f() (0x0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_mc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_mc_tu104.h index 8aabda13b..4467e2807 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_mc_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_mc_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,172 +59,50 @@ #include #include -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000U; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24U) & 0x1fU; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20U) & 0xfU; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 mc_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100U; -} -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200U; -} -static inline u32 mc_intr_pfb_pending_f(void) -{ - return 0x2000U; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000U; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_intr_nvlink_pending_f(void) -{ - return 0x400000U; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200U; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1U; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 mc_enable_ce0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100U; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000U; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000U; -} -static inline u32 mc_enable_ce2_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000U; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000U; -} -static inline u32 mc_enable_nvdec_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvdec_enabled_f(void) -{ - return 0x8000U; -} -static inline u32 mc_enable_nvlink_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 mc_enable_nvlink_disabled_f(void) -{ - return 0x0U; -} -static inline u32 mc_enable_nvlink_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 mc_enable_nvlink_enabled_f(void) -{ - return 0x2000000U; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0U; -} -static inline u32 mc_intr_fbpa_r(void) -{ - return 0x000001d0U; -} -static inline u32 mc_intr_fbpa_part_mask_v(u32 r) -{ - return (r >> 0U) & 0x1ffffU; -} +#define mc_boot_0_r() (0x00000000U) +#define mc_boot_0_architecture_v(r) (((r) >> 24U) & 0x1fU) +#define mc_boot_0_implementation_v(r) (((r) >> 20U) & 0xfU) +#define mc_boot_0_major_revision_v(r) (((r) >> 4U) & 0xfU) +#define mc_boot_0_minor_revision_v(r) (((r) >> 0U) & 0xfU) +#define mc_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000100U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_pfifo_pending_f() (0x100U) +#define mc_intr_hub_pending_f() (0x200U) +#define mc_intr_pfb_pending_f() (0x2000U) +#define mc_intr_pgraph_pending_f() (0x1000U) +#define mc_intr_pmu_pending_f() (0x1000000U) +#define mc_intr_ltc_pending_f() (0x2000000U) +#define mc_intr_priv_ring_pending_f() (0x40000000U) +#define mc_intr_pbus_pending_f() (0x10000000U) +#define mc_intr_nvlink_pending_f() (0x400000U) +#define mc_intr_en_r(i)\ + (nvgpu_safe_add_u32(0x00000140U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_set_r(i)\ + (nvgpu_safe_add_u32(0x00000160U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_intr_en_clear_r(i)\ + (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) +#define mc_enable_r() (0x00000200U) +#define mc_enable_pmedia_s() (1U) +#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) +#define mc_enable_pmedia_m() (U32(0x1U) << 4U) +#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) +#define mc_enable_ce0_m() (U32(0x1U) << 6U) +#define mc_enable_pfifo_enabled_f() (0x100U) +#define mc_enable_pgraph_enabled_f() (0x1000U) +#define mc_enable_pwr_v(r) (((r) >> 13U) & 0x1U) +#define mc_enable_pwr_disabled_v() (0x00000000U) +#define mc_enable_pwr_enabled_f() (0x2000U) +#define mc_enable_ce2_m() (U32(0x1U) << 21U) +#define mc_enable_ce2_enabled_f() (0x200000U) +#define mc_enable_blg_enabled_f() (0x8000000U) +#define mc_enable_perfmon_enabled_f() (0x10000000U) +#define mc_enable_nvdec_disabled_v() (0x00000000U) +#define mc_enable_nvdec_enabled_f() (0x8000U) +#define mc_enable_nvlink_disabled_v() (0x00000000U) +#define mc_enable_nvlink_disabled_f() (0x0U) +#define mc_enable_nvlink_enabled_v() (0x00000001U) +#define mc_enable_nvlink_enabled_f() (0x2000000U) +#define mc_intr_ltc_r() (0x000001c0U) +#define mc_intr_fbpa_r() (0x000001d0U) +#define mc_intr_fbpa_part_mask_v(r) (((r) >> 0U) & 0x1ffffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_minion_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_minion_tu104.h index af76e2b3c..67af5be8b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_minion_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_minion_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,880 +59,225 @@ #include #include -static inline u32 minion_minion_status_r(void) -{ - return 0x00000830U; -} -static inline u32 minion_minion_status_status_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_minion_status_status_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 minion_minion_status_status_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_minion_status_status_boot_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_status_status_boot_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_status_intr_code_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 minion_minion_status_intr_code_m(void) -{ - return U32(0xffffffU) << 8U; -} -static inline u32 minion_minion_status_intr_code_v(u32 r) -{ - return (r >> 8U) & 0xffffffU; -} -static inline u32 minion_falcon_irqstat_r(void) -{ - return 0x00000008U; -} -static inline u32 minion_falcon_irqstat_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqstat_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqmask_r(void) -{ - return 0x00000018U; -} -static inline u32 minion_falcon_irqsclr_r(void) -{ - return 0x00000004U; -} -static inline u32 minion_falcon_irqsset_r(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqmset_r(void) -{ - return 0x00000010U; -} -static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_wdtmr_set_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqmset_halt_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 minion_falcon_irqmset_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_halt_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_halt_set_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 minion_falcon_irqmset_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_exterr_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_exterr_set_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 minion_falcon_irqmset_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 minion_falcon_irqmset_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqmset_swgen1_set_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_r(void) -{ - return 0x0000001cU; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void) -{ - return 0x2U; -} -static inline u32 minion_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 minion_falcon_irqdest_host_halt_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_halt_host_f(void) -{ - return 0x10U; -} -static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_exterr_host_f(void) -{ - return 0x20U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen0_host_f(void) -{ - return 0x40U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_falcon_irqdest_host_swgen1_host_f(void) -{ - return 0x80U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 minion_falcon_irqdest_target_halt_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_halt_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_exterr_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_f(void) -{ - return 0x0U; -} -static inline u32 minion_falcon_os_r(void) -{ - return 0x00000080U; -} -static inline u32 minion_falcon_mailbox1_r(void) -{ - return 0x00000044U; -} -static inline u32 minion_minion_intr_r(void) -{ - return 0x00000810U; -} -static inline u32 minion_minion_intr_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_fatal_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 minion_minion_intr_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_nonfatal_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_minion_intr_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 minion_minion_intr_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 minion_minion_intr_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_link_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 minion_minion_intr_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_minion_intr_nonstall_en_r(void) -{ - return 0x0000081cU; -} -static inline u32 minion_minion_intr_stall_en_r(void) -{ - return 0x00000818U; -} -static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_fatal_enable_f(void) -{ - return 0x1U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_fatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_enable_f(void) -{ - return 0x2U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_nonfatal_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_f(void) -{ - return 0x4U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_f(void) -{ - return 0x8U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_f(void) -{ - return 0x0U; -} -static inline u32 minion_minion_intr_stall_en_link_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 minion_minion_intr_stall_en_link_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 minion_nvlink_dl_cmd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000900U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 minion_nvlink_dl_cmd___size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_dl_cmd_command_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_dl_cmd_command_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_v(void) -{ - return 0x00000040U; -} -static inline u32 minion_nvlink_dl_cmd_command_configeom_f(void) -{ - return 0x40U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_dl_cmd_command_nop_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_dl_cmd_command_initphy_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_v(void) -{ - return 0x00000003U; -} -static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_f(void) -{ - return 0x3U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_v(void) -{ - return 0x00000004U; -} -static inline u32 minion_nvlink_dl_cmd_command_initdlpl_f(void) -{ - return 0x4U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_v(void) -{ - return 0x00000008U; -} -static inline u32 minion_nvlink_dl_cmd_command_lanedisable_f(void) -{ - return 0x8U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_v(void) -{ - return 0x00000009U; -} -static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_f(void) -{ - return 0x9U; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_v(void) -{ - return 0x0000000cU; -} -static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_f(void) -{ - return 0xcU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_v(void) -{ - return 0x0000000aU; -} -static inline u32 minion_nvlink_dl_cmd_command_setacmode_f(void) -{ - return 0xaU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_v(void) -{ - return 0x0000000bU; -} -static inline u32 minion_nvlink_dl_cmd_command_clracmode_f(void) -{ - return 0xbU; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_v(void) -{ - return 0x00000010U; -} -static inline u32 minion_nvlink_dl_cmd_command_enablepm_f(void) -{ - return 0x10U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_v(void) -{ - return 0x00000011U; -} -static inline u32 minion_nvlink_dl_cmd_command_disablepm_f(void) -{ - return 0x11U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_v(void) -{ - return 0x00000018U; -} -static inline u32 minion_nvlink_dl_cmd_command_savestate_f(void) -{ - return 0x18U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_v(void) -{ - return 0x00000019U; -} -static inline u32 minion_nvlink_dl_cmd_command_restorestate_f(void) -{ - return 0x19U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_v(void) -{ - return 0x00000020U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_0_f(void) -{ - return 0x20U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_v(void) -{ - return 0x00000021U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_1_f(void) -{ - return 0x21U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_v(void) -{ - return 0x00000022U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_2_f(void) -{ - return 0x22U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_v(void) -{ - return 0x00000023U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_3_f(void) -{ - return 0x23U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_v(void) -{ - return 0x00000024U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_4_f(void) -{ - return 0x24U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_v(void) -{ - return 0x00000025U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_5_f(void) -{ - return 0x25U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_v(void) -{ - return 0x00000026U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_6_f(void) -{ - return 0x26U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_v(void) -{ - return 0x00000027U; -} -static inline u32 minion_nvlink_dl_cmd_command_initpll_7_f(void) -{ - return 0x27U; -} -static inline u32 minion_nvlink_dl_cmd_command_turing_rxdet_v(void) -{ - return 0x00000058U; -} -static inline u32 minion_nvlink_dl_cmd_command_txclkswitch_pll_v(void) -{ - return 0x00000014U; -} -static inline u32 minion_nvlink_dl_cmd_command_turing_initdlpl_to_chipa_v(void) -{ - return 0x00000060U; -} -static inline u32 minion_nvlink_dl_cmd_command_inittl_v(void) -{ - return 0x00000006U; -} -static inline u32 minion_nvlink_dl_cmd_fault_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_dl_cmd_ready_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 minion_misc_0_r(void) -{ - return 0x000008b0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 minion_misc_0_scratch_swrw_0_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 minion_nvlink_link_intr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000a00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 minion_nvlink_link_intr___size_1_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_link_intr_code_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 minion_nvlink_link_intr_code_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 minion_nvlink_link_intr_code_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_code_na_v(void) -{ - return 0x00000000U; -} -static inline u32 minion_nvlink_link_intr_code_na_f(void) -{ - return 0x0U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_v(void) -{ - return 0x00000001U; -} -static inline u32 minion_nvlink_link_intr_code_swreq_f(void) -{ - return 0x1U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_v(void) -{ - return 0x00000002U; -} -static inline u32 minion_nvlink_link_intr_code_dlreq_f(void) -{ - return 0x2U; -} -static inline u32 minion_nvlink_link_intr_subcode_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 minion_nvlink_link_intr_subcode_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 minion_nvlink_link_intr_state_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 minion_nvlink_link_intr_state_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 minion_nvlink_link_intr_state_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} +#define minion_minion_status_r() (0x00000830U) +#define minion_minion_status_status_f(v) (((v)&0xffU) << 0U) +#define minion_minion_status_status_m() (U32(0xffU) << 0U) +#define minion_minion_status_status_v(r) (((r) >> 0U) & 0xffU) +#define minion_minion_status_status_boot_v() (0x00000001U) +#define minion_minion_status_status_boot_f() (0x1U) +#define minion_minion_status_intr_code_f(v) (((v)&0xffffffU) << 8U) +#define minion_minion_status_intr_code_m() (U32(0xffffffU) << 8U) +#define minion_minion_status_intr_code_v(r) (((r) >> 8U) & 0xffffffU) +#define minion_falcon_irqstat_r() (0x00000008U) +#define minion_falcon_irqstat_halt_f(v) (((v)&0x1U) << 4U) +#define minion_falcon_irqstat_halt_v(r) (((r) >> 4U) & 0x1U) +#define minion_falcon_irqmask_r() (0x00000018U) +#define minion_falcon_irqsclr_r() (0x00000004U) +#define minion_falcon_irqsset_r() (0x00000000U) +#define minion_falcon_irqmset_r() (0x00000010U) +#define minion_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define minion_falcon_irqmset_wdtmr_m() (U32(0x1U) << 1U) +#define minion_falcon_irqmset_wdtmr_v(r) (((r) >> 1U) & 0x1U) +#define minion_falcon_irqmset_wdtmr_set_v() (0x00000001U) +#define minion_falcon_irqmset_wdtmr_set_f() (0x2U) +#define minion_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define minion_falcon_irqmset_halt_m() (U32(0x1U) << 4U) +#define minion_falcon_irqmset_halt_v(r) (((r) >> 4U) & 0x1U) +#define minion_falcon_irqmset_halt_set_v() (0x00000001U) +#define minion_falcon_irqmset_halt_set_f() (0x10U) +#define minion_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define minion_falcon_irqmset_exterr_m() (U32(0x1U) << 5U) +#define minion_falcon_irqmset_exterr_v(r) (((r) >> 5U) & 0x1U) +#define minion_falcon_irqmset_exterr_set_v() (0x00000001U) +#define minion_falcon_irqmset_exterr_set_f() (0x20U) +#define minion_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define minion_falcon_irqmset_swgen0_m() (U32(0x1U) << 6U) +#define minion_falcon_irqmset_swgen0_v(r) (((r) >> 6U) & 0x1U) +#define minion_falcon_irqmset_swgen0_set_v() (0x00000001U) +#define minion_falcon_irqmset_swgen0_set_f() (0x40U) +#define minion_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define minion_falcon_irqmset_swgen1_m() (U32(0x1U) << 7U) +#define minion_falcon_irqmset_swgen1_v(r) (((r) >> 7U) & 0x1U) +#define minion_falcon_irqmset_swgen1_set_v() (0x00000001U) +#define minion_falcon_irqmset_swgen1_set_f() (0x80U) +#define minion_falcon_irqdest_r() (0x0000001cU) +#define minion_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define minion_falcon_irqdest_host_wdtmr_m() (U32(0x1U) << 1U) +#define minion_falcon_irqdest_host_wdtmr_v(r) (((r) >> 1U) & 0x1U) +#define minion_falcon_irqdest_host_wdtmr_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_wdtmr_host_f() (0x2U) +#define minion_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define minion_falcon_irqdest_host_halt_m() (U32(0x1U) << 4U) +#define minion_falcon_irqdest_host_halt_v(r) (((r) >> 4U) & 0x1U) +#define minion_falcon_irqdest_host_halt_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_halt_host_f() (0x10U) +#define minion_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define minion_falcon_irqdest_host_exterr_m() (U32(0x1U) << 5U) +#define minion_falcon_irqdest_host_exterr_v(r) (((r) >> 5U) & 0x1U) +#define minion_falcon_irqdest_host_exterr_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_exterr_host_f() (0x20U) +#define minion_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define minion_falcon_irqdest_host_swgen0_m() (U32(0x1U) << 6U) +#define minion_falcon_irqdest_host_swgen0_v(r) (((r) >> 6U) & 0x1U) +#define minion_falcon_irqdest_host_swgen0_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_swgen0_host_f() (0x40U) +#define minion_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define minion_falcon_irqdest_host_swgen1_m() (U32(0x1U) << 7U) +#define minion_falcon_irqdest_host_swgen1_v(r) (((r) >> 7U) & 0x1U) +#define minion_falcon_irqdest_host_swgen1_host_v() (0x00000001U) +#define minion_falcon_irqdest_host_swgen1_host_f() (0x80U) +#define minion_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define minion_falcon_irqdest_target_wdtmr_m() (U32(0x1U) << 17U) +#define minion_falcon_irqdest_target_wdtmr_v(r) (((r) >> 17U) & 0x1U) +#define minion_falcon_irqdest_target_wdtmr_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_wdtmr_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define minion_falcon_irqdest_target_halt_m() (U32(0x1U) << 20U) +#define minion_falcon_irqdest_target_halt_v(r) (((r) >> 20U) & 0x1U) +#define minion_falcon_irqdest_target_halt_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_halt_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define minion_falcon_irqdest_target_exterr_m() (U32(0x1U) << 21U) +#define minion_falcon_irqdest_target_exterr_v(r) (((r) >> 21U) & 0x1U) +#define minion_falcon_irqdest_target_exterr_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_exterr_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define minion_falcon_irqdest_target_swgen0_m() (U32(0x1U) << 22U) +#define minion_falcon_irqdest_target_swgen0_v(r) (((r) >> 22U) & 0x1U) +#define minion_falcon_irqdest_target_swgen0_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_swgen0_host_normal_f() (0x0U) +#define minion_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define minion_falcon_irqdest_target_swgen1_m() (U32(0x1U) << 23U) +#define minion_falcon_irqdest_target_swgen1_v(r) (((r) >> 23U) & 0x1U) +#define minion_falcon_irqdest_target_swgen1_host_normal_v() (0x00000000U) +#define minion_falcon_irqdest_target_swgen1_host_normal_f() (0x0U) +#define minion_falcon_os_r() (0x00000080U) +#define minion_falcon_mailbox1_r() (0x00000044U) +#define minion_minion_intr_r() (0x00000810U) +#define minion_minion_intr_fatal_f(v) (((v)&0x1U) << 0U) +#define minion_minion_intr_fatal_m() (U32(0x1U) << 0U) +#define minion_minion_intr_fatal_v(r) (((r) >> 0U) & 0x1U) +#define minion_minion_intr_nonfatal_f(v) (((v)&0x1U) << 1U) +#define minion_minion_intr_nonfatal_m() (U32(0x1U) << 1U) +#define minion_minion_intr_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define minion_minion_intr_falcon_stall_f(v) (((v)&0x1U) << 2U) +#define minion_minion_intr_falcon_stall_m() (U32(0x1U) << 2U) +#define minion_minion_intr_falcon_stall_v(r) (((r) >> 2U) & 0x1U) +#define minion_minion_intr_falcon_nostall_f(v) (((v)&0x1U) << 3U) +#define minion_minion_intr_falcon_nostall_m() (U32(0x1U) << 3U) +#define minion_minion_intr_falcon_nostall_v(r) (((r) >> 3U) & 0x1U) +#define minion_minion_intr_link_f(v) (((v)&0xffffU) << 16U) +#define minion_minion_intr_link_m() (U32(0xffffU) << 16U) +#define minion_minion_intr_link_v(r) (((r) >> 16U) & 0xffffU) +#define minion_minion_intr_nonstall_en_r() (0x0000081cU) +#define minion_minion_intr_stall_en_r() (0x00000818U) +#define minion_minion_intr_stall_en_fatal_f(v) (((v)&0x1U) << 0U) +#define minion_minion_intr_stall_en_fatal_m() (U32(0x1U) << 0U) +#define minion_minion_intr_stall_en_fatal_v(r) (((r) >> 0U) & 0x1U) +#define minion_minion_intr_stall_en_fatal_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_fatal_enable_f() (0x1U) +#define minion_minion_intr_stall_en_fatal_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_fatal_disable_f() (0x0U) +#define minion_minion_intr_stall_en_nonfatal_f(v) (((v)&0x1U) << 1U) +#define minion_minion_intr_stall_en_nonfatal_m() (U32(0x1U) << 1U) +#define minion_minion_intr_stall_en_nonfatal_v(r) (((r) >> 1U) & 0x1U) +#define minion_minion_intr_stall_en_nonfatal_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_nonfatal_enable_f() (0x2U) +#define minion_minion_intr_stall_en_nonfatal_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_nonfatal_disable_f() (0x0U) +#define minion_minion_intr_stall_en_falcon_stall_f(v) (((v)&0x1U) << 2U) +#define minion_minion_intr_stall_en_falcon_stall_m() (U32(0x1U) << 2U) +#define minion_minion_intr_stall_en_falcon_stall_v(r) (((r) >> 2U) & 0x1U) +#define minion_minion_intr_stall_en_falcon_stall_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_falcon_stall_enable_f() (0x4U) +#define minion_minion_intr_stall_en_falcon_stall_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_falcon_stall_disable_f() (0x0U) +#define minion_minion_intr_stall_en_falcon_nostall_f(v) (((v)&0x1U) << 3U) +#define minion_minion_intr_stall_en_falcon_nostall_m() (U32(0x1U) << 3U) +#define minion_minion_intr_stall_en_falcon_nostall_v(r) (((r) >> 3U) & 0x1U) +#define minion_minion_intr_stall_en_falcon_nostall_enable_v() (0x00000001U) +#define minion_minion_intr_stall_en_falcon_nostall_enable_f() (0x8U) +#define minion_minion_intr_stall_en_falcon_nostall_disable_v() (0x00000000U) +#define minion_minion_intr_stall_en_falcon_nostall_disable_f() (0x0U) +#define minion_minion_intr_stall_en_link_f(v) (((v)&0xffffU) << 16U) +#define minion_minion_intr_stall_en_link_m() (U32(0xffffU) << 16U) +#define minion_minion_intr_stall_en_link_v(r) (((r) >> 16U) & 0xffffU) +#define minion_nvlink_dl_cmd_r(i)\ + (nvgpu_safe_add_u32(0x00000900U, nvgpu_safe_mult_u32((i), 4U))) +#define minion_nvlink_dl_cmd___size_1_v() (0x00000002U) +#define minion_nvlink_dl_cmd_command_f(v) (((v)&0xffU) << 0U) +#define minion_nvlink_dl_cmd_command_v(r) (((r) >> 0U) & 0xffU) +#define minion_nvlink_dl_cmd_command_configeom_v() (0x00000040U) +#define minion_nvlink_dl_cmd_command_configeom_f() (0x40U) +#define minion_nvlink_dl_cmd_command_nop_v() (0x00000000U) +#define minion_nvlink_dl_cmd_command_nop_f() (0x0U) +#define minion_nvlink_dl_cmd_command_initphy_v() (0x00000001U) +#define minion_nvlink_dl_cmd_command_initphy_f() (0x1U) +#define minion_nvlink_dl_cmd_command_initlaneenable_v() (0x00000003U) +#define minion_nvlink_dl_cmd_command_initlaneenable_f() (0x3U) +#define minion_nvlink_dl_cmd_command_initdlpl_v() (0x00000004U) +#define minion_nvlink_dl_cmd_command_initdlpl_f() (0x4U) +#define minion_nvlink_dl_cmd_command_lanedisable_v() (0x00000008U) +#define minion_nvlink_dl_cmd_command_lanedisable_f() (0x8U) +#define minion_nvlink_dl_cmd_command_fastlanedisable_v() (0x00000009U) +#define minion_nvlink_dl_cmd_command_fastlanedisable_f() (0x9U) +#define minion_nvlink_dl_cmd_command_laneshutdown_v() (0x0000000cU) +#define minion_nvlink_dl_cmd_command_laneshutdown_f() (0xcU) +#define minion_nvlink_dl_cmd_command_setacmode_v() (0x0000000aU) +#define minion_nvlink_dl_cmd_command_setacmode_f() (0xaU) +#define minion_nvlink_dl_cmd_command_clracmode_v() (0x0000000bU) +#define minion_nvlink_dl_cmd_command_clracmode_f() (0xbU) +#define minion_nvlink_dl_cmd_command_enablepm_v() (0x00000010U) +#define minion_nvlink_dl_cmd_command_enablepm_f() (0x10U) +#define minion_nvlink_dl_cmd_command_disablepm_v() (0x00000011U) +#define minion_nvlink_dl_cmd_command_disablepm_f() (0x11U) +#define minion_nvlink_dl_cmd_command_savestate_v() (0x00000018U) +#define minion_nvlink_dl_cmd_command_savestate_f() (0x18U) +#define minion_nvlink_dl_cmd_command_restorestate_v() (0x00000019U) +#define minion_nvlink_dl_cmd_command_restorestate_f() (0x19U) +#define minion_nvlink_dl_cmd_command_initpll_0_v() (0x00000020U) +#define minion_nvlink_dl_cmd_command_initpll_0_f() (0x20U) +#define minion_nvlink_dl_cmd_command_initpll_1_v() (0x00000021U) +#define minion_nvlink_dl_cmd_command_initpll_1_f() (0x21U) +#define minion_nvlink_dl_cmd_command_initpll_2_v() (0x00000022U) +#define minion_nvlink_dl_cmd_command_initpll_2_f() (0x22U) +#define minion_nvlink_dl_cmd_command_initpll_3_v() (0x00000023U) +#define minion_nvlink_dl_cmd_command_initpll_3_f() (0x23U) +#define minion_nvlink_dl_cmd_command_initpll_4_v() (0x00000024U) +#define minion_nvlink_dl_cmd_command_initpll_4_f() (0x24U) +#define minion_nvlink_dl_cmd_command_initpll_5_v() (0x00000025U) +#define minion_nvlink_dl_cmd_command_initpll_5_f() (0x25U) +#define minion_nvlink_dl_cmd_command_initpll_6_v() (0x00000026U) +#define minion_nvlink_dl_cmd_command_initpll_6_f() (0x26U) +#define minion_nvlink_dl_cmd_command_initpll_7_v() (0x00000027U) +#define minion_nvlink_dl_cmd_command_initpll_7_f() (0x27U) +#define minion_nvlink_dl_cmd_command_turing_rxdet_v() (0x00000058U) +#define minion_nvlink_dl_cmd_command_txclkswitch_pll_v() (0x00000014U) +#define minion_nvlink_dl_cmd_command_turing_initdlpl_to_chipa_v() (0x00000060U) +#define minion_nvlink_dl_cmd_command_inittl_v() (0x00000006U) +#define minion_nvlink_dl_cmd_fault_f(v) (((v)&0x1U) << 30U) +#define minion_nvlink_dl_cmd_fault_v(r) (((r) >> 30U) & 0x1U) +#define minion_nvlink_dl_cmd_ready_f(v) (((v)&0x1U) << 31U) +#define minion_nvlink_dl_cmd_ready_v(r) (((r) >> 31U) & 0x1U) +#define minion_misc_0_r() (0x000008b0U) +#define minion_misc_0_scratch_swrw_0_f(v) (((v)&0xffffffffU) << 0U) +#define minion_misc_0_scratch_swrw_0_v(r) (((r) >> 0U) & 0xffffffffU) +#define minion_nvlink_link_intr_r(i)\ + (nvgpu_safe_add_u32(0x00000a00U, nvgpu_safe_mult_u32((i), 4U))) +#define minion_nvlink_link_intr___size_1_v() (0x00000002U) +#define minion_nvlink_link_intr_code_f(v) (((v)&0xffU) << 0U) +#define minion_nvlink_link_intr_code_m() (U32(0xffU) << 0U) +#define minion_nvlink_link_intr_code_v(r) (((r) >> 0U) & 0xffU) +#define minion_nvlink_link_intr_code_na_v() (0x00000000U) +#define minion_nvlink_link_intr_code_na_f() (0x0U) +#define minion_nvlink_link_intr_code_swreq_v() (0x00000001U) +#define minion_nvlink_link_intr_code_swreq_f() (0x1U) +#define minion_nvlink_link_intr_code_dlreq_v() (0x00000002U) +#define minion_nvlink_link_intr_code_dlreq_f() (0x2U) +#define minion_nvlink_link_intr_subcode_f(v) (((v)&0xffU) << 8U) +#define minion_nvlink_link_intr_subcode_m() (U32(0xffU) << 8U) +#define minion_nvlink_link_intr_subcode_v(r) (((r) >> 8U) & 0xffU) +#define minion_nvlink_link_intr_state_f(v) (((v)&0x1U) << 31U) +#define minion_nvlink_link_intr_state_m() (U32(0x1U) << 31U) +#define minion_nvlink_link_intr_state_v(r) (((r) >> 31U) & 0x1U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvl_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvl_tu104.h index 27c188bb0..38af22d57 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvl_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvl_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,1576 +59,398 @@ #include #include -static inline u32 nvl_link_state_r(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 nvl_link_state_state_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 nvl_link_state_state_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 nvl_link_state_state_init_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_state_state_init_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_state_state_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_state_state_hwcfg_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_state_state_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_state_state_swcfg_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_state_state_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_state_state_active_f(void) -{ - return 0x3U; -} -static inline u32 nvl_link_state_state_fault_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_link_state_state_fault_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_state_state_rcvy_ac_v(void) -{ - return 0x00000008U; -} -static inline u32 nvl_link_state_state_rcvy_ac_f(void) -{ - return 0x8U; -} -static inline u32 nvl_link_state_state_rcvy_sw_v(void) -{ - return 0x00000009U; -} -static inline u32 nvl_link_state_state_rcvy_sw_f(void) -{ - return 0x9U; -} -static inline u32 nvl_link_state_state_rcvy_rx_v(void) -{ - return 0x0000000aU; -} -static inline u32 nvl_link_state_state_rcvy_rx_f(void) -{ - return 0xaU; -} -static inline u32 nvl_link_state_an0_busy_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvl_link_state_an0_busy_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 nvl_link_state_an0_busy_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvl_link_state_tl_busy_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvl_link_state_tl_busy_m(void) -{ - return U32(0x1U) << 13U; -} -static inline u32 nvl_link_state_tl_busy_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvl_link_state_dbg_substate_f(u32 v) -{ - return (v & 0xffffU) << 16U; -} -static inline u32 nvl_link_state_dbg_substate_m(void) -{ - return U32(0xffffU) << 16U; -} -static inline u32 nvl_link_state_dbg_substate_v(u32 r) -{ - return (r >> 16U) & 0xffffU; -} -static inline u32 nvl_link_activity_r(void) -{ - return 0x0000000cU; -} -static inline u32 nvl_link_activity_blkact_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_link_activity_blkact_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 nvl_link_activity_blkact_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 nvl_sublink_activity_blkact0_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 nvl_sublink_activity_blkact0_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sublink_activity_blkact1_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_m(void) -{ - return U32(0x7U) << 8U; -} -static inline u32 nvl_sublink_activity_blkact1_v(u32 r) -{ - return (r >> 8U) & 0x7U; -} -static inline u32 nvl_link_config_r(void) -{ - return 0x00000018U; -} -static inline u32 nvl_link_config_ac_safe_en_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_link_config_ac_safe_en_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_config_ac_safe_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_ac_safe_en_on_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_config_link_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_config_link_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 nvl_link_config_link_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_config_link_en_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_config_link_en_on_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_link_change_r(void) -{ - return 0x00000040U; -} -static inline u32 nvl_link_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 nvl_link_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_link_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_link_change_newstate_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_link_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_link_change_newstate_hwcfg_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_newstate_hwcfg_f(void) -{ - return 0x10U; -} -static inline u32 nvl_link_change_newstate_swcfg_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_newstate_swcfg_f(void) -{ - return 0x20U; -} -static inline u32 nvl_link_change_newstate_active_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_link_change_newstate_active_f(void) -{ - return 0x30U; -} -static inline u32 nvl_link_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_link_change_action_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 nvl_link_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_link_change_action_ltssm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_action_ltssm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_link_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_link_change_status_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 nvl_link_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_link_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_link_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_link_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_link_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_sublink_change_r(void) -{ - return 0x00000044U; -} -static inline u32 nvl_sublink_change_countdown_f(u32 v) -{ - return (v & 0xfffU) << 20U; -} -static inline u32 nvl_sublink_change_countdown_m(void) -{ - return U32(0xfffU) << 20U; -} -static inline u32 nvl_sublink_change_countdown_v(u32 r) -{ - return (r >> 20U) & 0xfffU; -} -static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void) -{ - return 0xf0000U; -} -static inline u32 nvl_sublink_change_sublink_f(u32 v) -{ - return (v & 0xfU) << 12U; -} -static inline u32 nvl_sublink_change_sublink_m(void) -{ - return U32(0xfU) << 12U; -} -static inline u32 nvl_sublink_change_sublink_v(u32 r) -{ - return (r >> 12U) & 0xfU; -} -static inline u32 nvl_sublink_change_sublink_tx_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_sublink_tx_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_sublink_rx_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_sublink_rx_f(void) -{ - return 0x1000U; -} -static inline u32 nvl_sublink_change_newstate_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sublink_change_newstate_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_sublink_change_newstate_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sublink_change_newstate_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_newstate_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_newstate_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sublink_change_newstate_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sublink_change_newstate_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sublink_change_newstate_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sublink_change_newstate_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sublink_change_newstate_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sublink_change_newstate_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sublink_change_newstate_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sublink_change_action_f(u32 v) -{ - return (v & 0x3U) << 2U; -} -static inline u32 nvl_sublink_change_action_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 nvl_sublink_change_action_v(u32 r) -{ - return (r >> 2U) & 0x3U; -} -static inline u32 nvl_sublink_change_action_slsm_change_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_action_slsm_change_f(void) -{ - return 0x4U; -} -static inline u32 nvl_sublink_change_status_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 nvl_sublink_change_status_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 nvl_sublink_change_status_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 nvl_sublink_change_status_done_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sublink_change_status_done_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sublink_change_status_busy_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_sublink_change_status_busy_f(void) -{ - return 0x1U; -} -static inline u32 nvl_sublink_change_status_fault_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_sublink_change_status_fault_f(void) -{ - return 0x2U; -} -static inline u32 nvl_link_test_r(void) -{ - return 0x00000048U; -} -static inline u32 nvl_link_test_mode_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_link_test_mode_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_link_test_mode_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_link_test_mode_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_mode_enable_f(void) -{ - return 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_link_test_auto_hwcfg_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_hwcfg_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_link_test_auto_nvhs_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 nvl_link_test_auto_nvhs_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_link_test_auto_nvhs_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_r(void) -{ - return 0x00002024U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_stable_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_substate_stable_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_unknown_v(void) -{ - return 0x0000000dU; -} -static inline u32 nvl_sl0_slsm_status_tx_primary_state_unknown_f(void) -{ - return 0xd0U; -} -static inline u32 nvl_sl1_slsm_status_rx_r(void) -{ - return 0x00003014U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_stable_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl1_slsm_status_rx_substate_stable_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v) -{ - return (v & 0xfU) << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void) -{ - return U32(0xfU) << 4U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r) -{ - return (r >> 4U) & 0xfU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void) -{ - return 0x00000000U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void) -{ - return 0x0U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void) -{ - return 0x00000004U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void) -{ - return 0x40U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void) -{ - return 0x00000005U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void) -{ - return 0x50U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void) -{ - return 0x00000007U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void) -{ - return 0x70U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void) -{ - return 0x00000006U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void) -{ - return 0x60U; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_unknown_v(void) -{ - return 0x0000000dU; -} -static inline u32 nvl_sl1_slsm_status_rx_primary_state_unknown_f(void) -{ - return 0xd0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_r(void) -{ - return 0x00002008U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v) -{ - return (v & 0x7ffU) << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void) -{ - return U32(0x7ffU) << 0U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r) -{ - return (r >> 0U) & 0x7ffU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void) -{ - return 0x00000728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void) -{ - return 0x728U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v) -{ - return (v & 0x1fU) << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void) -{ - return U32(0x1fU) << 11U; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r) -{ - return (r >> 11U) & 0x1fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void) -{ - return 0x0000000fU; -} -static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void) -{ - return 0x7800U; -} -static inline u32 nvl_sl1_error_rate_ctrl_r(void) -{ - return 0x00003284U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r) -{ - return (r >> 0U) & 0x7U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v) -{ - return (v & 0x7U) << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void) -{ - return U32(0x7U) << 16U; -} -static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 nvl_sl1_rxslsm_timeout_2_r(void) -{ - return 0x00003034U; -} -static inline u32 nvl_txiobist_configreg_r(void) -{ - return 0x00002e14U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void) -{ - return U32(0x1U) << 17U; -} -static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvl_txiobist_config_r(void) -{ - return 0x00002e10U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_r(void) -{ - return 0x00000050U; -} -static inline u32 nvl_intr_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_tx_replay_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_intr_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvl_intr_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_intr_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 nvl_intr_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 nvl_intr_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 nvl_intr_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 nvl_intr_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 nvl_intr_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 nvl_intr_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_ltssm_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 nvl_intr_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 nvl_intr_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_request_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_intr_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_sw2_r(void) -{ - return 0x00000054U; -} -static inline u32 nvl_intr_minion_r(void) -{ - return 0x00000060U; -} -static inline u32 nvl_intr_minion_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_intr_minion_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_minion_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_minion_minion_request_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_intr_minion_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_nonstall_en_r(void) -{ - return 0x0000005cU; -} -static inline u32 nvl_intr_stall_en_r(void) -{ - return 0x00000058U; -} -static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void) -{ - return 0x2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void) -{ - return 0x4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void) -{ - return 0x10U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void) -{ - return 0x20U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void) -{ - return 0x100U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void) -{ - return 0x10000U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void) -{ - return 0x100000U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void) -{ - return U32(0x1U) << 21U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r) -{ - return (r >> 21U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void) -{ - return 0x200000U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void) -{ - return U32(0x1U) << 22U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void) -{ - return 0x400000U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void) -{ - return U32(0x1U) << 23U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r) -{ - return (r >> 23U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void) -{ - return 0x800000U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void) -{ - return 0x1000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_m(void) -{ - return U32(0x1U) << 28U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r) -{ - return (r >> 28U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void) -{ - return 0x10000000U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void) -{ - return U32(0x1U) << 29U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r) -{ - return (r >> 29U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 nvl_intr_stall_en_minion_request_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 nvl_intr_stall_en_minion_request_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_intr_stall_en_minion_request_enable_f(void) -{ - return 0x40000000U; -} -static inline u32 nvl_br0_cfg_cal_r(void) -{ - return 0x0000281cU; -} -static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void) -{ - return 0x00000001U; -} -static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void) -{ - return 0x1U; -} -static inline u32 nvl_br0_cfg_status_cal_r(void) -{ - return 0x00002838U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvl_sl0_link_rxdet_status_r(void) -{ - return 0x00002228U; -} -static inline u32 nvl_sl0_link_rxdet_status_sts_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 nvl_sl0_link_rxdet_status_sts_found_v(void) -{ - return 0x00000002U; -} -static inline u32 nvl_sl0_link_rxdet_status_sts_timeout_v(void) -{ - return 0x00000003U; -} -static inline u32 nvl_clk_status_r(void) -{ - return 0x0000001cU; -} -static inline u32 nvl_clk_status_txclk_sts_v(u32 r) -{ - return (r >> 19U) & 0x1U; -} -static inline u32 nvl_clk_status_txclk_sts_pll_clk_v(void) -{ - return 0x00000000U; -} +#define nvl_link_state_r() (0x00000000U) +#define nvl_link_state_state_f(v) (((v)&0xffU) << 0U) +#define nvl_link_state_state_m() (U32(0xffU) << 0U) +#define nvl_link_state_state_v(r) (((r) >> 0U) & 0xffU) +#define nvl_link_state_state_init_v() (0x00000000U) +#define nvl_link_state_state_init_f() (0x0U) +#define nvl_link_state_state_hwcfg_v() (0x00000001U) +#define nvl_link_state_state_hwcfg_f() (0x1U) +#define nvl_link_state_state_swcfg_v() (0x00000002U) +#define nvl_link_state_state_swcfg_f() (0x2U) +#define nvl_link_state_state_active_v() (0x00000003U) +#define nvl_link_state_state_active_f() (0x3U) +#define nvl_link_state_state_fault_v() (0x00000004U) +#define nvl_link_state_state_fault_f() (0x4U) +#define nvl_link_state_state_rcvy_ac_v() (0x00000008U) +#define nvl_link_state_state_rcvy_ac_f() (0x8U) +#define nvl_link_state_state_rcvy_sw_v() (0x00000009U) +#define nvl_link_state_state_rcvy_sw_f() (0x9U) +#define nvl_link_state_state_rcvy_rx_v() (0x0000000aU) +#define nvl_link_state_state_rcvy_rx_f() (0xaU) +#define nvl_link_state_an0_busy_f(v) (((v)&0x1U) << 12U) +#define nvl_link_state_an0_busy_m() (U32(0x1U) << 12U) +#define nvl_link_state_an0_busy_v(r) (((r) >> 12U) & 0x1U) +#define nvl_link_state_tl_busy_f(v) (((v)&0x1U) << 13U) +#define nvl_link_state_tl_busy_m() (U32(0x1U) << 13U) +#define nvl_link_state_tl_busy_v(r) (((r) >> 13U) & 0x1U) +#define nvl_link_state_dbg_substate_f(v) (((v)&0xffffU) << 16U) +#define nvl_link_state_dbg_substate_m() (U32(0xffffU) << 16U) +#define nvl_link_state_dbg_substate_v(r) (((r) >> 16U) & 0xffffU) +#define nvl_link_activity_r() (0x0000000cU) +#define nvl_link_activity_blkact_f(v) (((v)&0x7U) << 0U) +#define nvl_link_activity_blkact_m() (U32(0x7U) << 0U) +#define nvl_link_activity_blkact_v(r) (((r) >> 0U) & 0x7U) +#define nvl_sublink_activity_r(i)\ + (nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32((i), 4U))) +#define nvl_sublink_activity_blkact0_f(v) (((v)&0x7U) << 0U) +#define nvl_sublink_activity_blkact0_m() (U32(0x7U) << 0U) +#define nvl_sublink_activity_blkact0_v(r) (((r) >> 0U) & 0x7U) +#define nvl_sublink_activity_blkact1_f(v) (((v)&0x7U) << 8U) +#define nvl_sublink_activity_blkact1_m() (U32(0x7U) << 8U) +#define nvl_sublink_activity_blkact1_v(r) (((r) >> 8U) & 0x7U) +#define nvl_link_config_r() (0x00000018U) +#define nvl_link_config_ac_safe_en_f(v) (((v)&0x1U) << 30U) +#define nvl_link_config_ac_safe_en_m() (U32(0x1U) << 30U) +#define nvl_link_config_ac_safe_en_v(r) (((r) >> 30U) & 0x1U) +#define nvl_link_config_ac_safe_en_on_v() (0x00000001U) +#define nvl_link_config_ac_safe_en_on_f() (0x40000000U) +#define nvl_link_config_link_en_f(v) (((v)&0x1U) << 31U) +#define nvl_link_config_link_en_m() (U32(0x1U) << 31U) +#define nvl_link_config_link_en_v(r) (((r) >> 31U) & 0x1U) +#define nvl_link_config_link_en_on_v() (0x00000001U) +#define nvl_link_config_link_en_on_f() (0x80000000U) +#define nvl_link_change_r() (0x00000040U) +#define nvl_link_change_oldstate_mask_f(v) (((v)&0xfU) << 16U) +#define nvl_link_change_oldstate_mask_m() (U32(0xfU) << 16U) +#define nvl_link_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU) +#define nvl_link_change_oldstate_mask_dontcare_v() (0x0000000fU) +#define nvl_link_change_oldstate_mask_dontcare_f() (0xf0000U) +#define nvl_link_change_newstate_f(v) (((v)&0xfU) << 4U) +#define nvl_link_change_newstate_m() (U32(0xfU) << 4U) +#define nvl_link_change_newstate_v(r) (((r) >> 4U) & 0xfU) +#define nvl_link_change_newstate_hwcfg_v() (0x00000001U) +#define nvl_link_change_newstate_hwcfg_f() (0x10U) +#define nvl_link_change_newstate_swcfg_v() (0x00000002U) +#define nvl_link_change_newstate_swcfg_f() (0x20U) +#define nvl_link_change_newstate_active_v() (0x00000003U) +#define nvl_link_change_newstate_active_f() (0x30U) +#define nvl_link_change_action_f(v) (((v)&0x3U) << 2U) +#define nvl_link_change_action_m() (U32(0x3U) << 2U) +#define nvl_link_change_action_v(r) (((r) >> 2U) & 0x3U) +#define nvl_link_change_action_ltssm_change_v() (0x00000001U) +#define nvl_link_change_action_ltssm_change_f() (0x4U) +#define nvl_link_change_status_f(v) (((v)&0x3U) << 0U) +#define nvl_link_change_status_m() (U32(0x3U) << 0U) +#define nvl_link_change_status_v(r) (((r) >> 0U) & 0x3U) +#define nvl_link_change_status_done_v() (0x00000000U) +#define nvl_link_change_status_done_f() (0x0U) +#define nvl_link_change_status_busy_v() (0x00000001U) +#define nvl_link_change_status_busy_f() (0x1U) +#define nvl_link_change_status_fault_v() (0x00000002U) +#define nvl_link_change_status_fault_f() (0x2U) +#define nvl_sublink_change_r() (0x00000044U) +#define nvl_sublink_change_countdown_f(v) (((v)&0xfffU) << 20U) +#define nvl_sublink_change_countdown_m() (U32(0xfffU) << 20U) +#define nvl_sublink_change_countdown_v(r) (((r) >> 20U) & 0xfffU) +#define nvl_sublink_change_oldstate_mask_f(v) (((v)&0xfU) << 16U) +#define nvl_sublink_change_oldstate_mask_m() (U32(0xfU) << 16U) +#define nvl_sublink_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU) +#define nvl_sublink_change_oldstate_mask_dontcare_v() (0x0000000fU) +#define nvl_sublink_change_oldstate_mask_dontcare_f() (0xf0000U) +#define nvl_sublink_change_sublink_f(v) (((v)&0xfU) << 12U) +#define nvl_sublink_change_sublink_m() (U32(0xfU) << 12U) +#define nvl_sublink_change_sublink_v(r) (((r) >> 12U) & 0xfU) +#define nvl_sublink_change_sublink_tx_v() (0x00000000U) +#define nvl_sublink_change_sublink_tx_f() (0x0U) +#define nvl_sublink_change_sublink_rx_v() (0x00000001U) +#define nvl_sublink_change_sublink_rx_f() (0x1000U) +#define nvl_sublink_change_newstate_f(v) (((v)&0xfU) << 4U) +#define nvl_sublink_change_newstate_m() (U32(0xfU) << 4U) +#define nvl_sublink_change_newstate_v(r) (((r) >> 4U) & 0xfU) +#define nvl_sublink_change_newstate_hs_v() (0x00000000U) +#define nvl_sublink_change_newstate_hs_f() (0x0U) +#define nvl_sublink_change_newstate_eighth_v() (0x00000004U) +#define nvl_sublink_change_newstate_eighth_f() (0x40U) +#define nvl_sublink_change_newstate_train_v() (0x00000005U) +#define nvl_sublink_change_newstate_train_f() (0x50U) +#define nvl_sublink_change_newstate_safe_v() (0x00000006U) +#define nvl_sublink_change_newstate_safe_f() (0x60U) +#define nvl_sublink_change_newstate_off_v() (0x00000007U) +#define nvl_sublink_change_newstate_off_f() (0x70U) +#define nvl_sublink_change_action_f(v) (((v)&0x3U) << 2U) +#define nvl_sublink_change_action_m() (U32(0x3U) << 2U) +#define nvl_sublink_change_action_v(r) (((r) >> 2U) & 0x3U) +#define nvl_sublink_change_action_slsm_change_v() (0x00000001U) +#define nvl_sublink_change_action_slsm_change_f() (0x4U) +#define nvl_sublink_change_status_f(v) (((v)&0x3U) << 0U) +#define nvl_sublink_change_status_m() (U32(0x3U) << 0U) +#define nvl_sublink_change_status_v(r) (((r) >> 0U) & 0x3U) +#define nvl_sublink_change_status_done_v() (0x00000000U) +#define nvl_sublink_change_status_done_f() (0x0U) +#define nvl_sublink_change_status_busy_v() (0x00000001U) +#define nvl_sublink_change_status_busy_f() (0x1U) +#define nvl_sublink_change_status_fault_v() (0x00000002U) +#define nvl_sublink_change_status_fault_f() (0x2U) +#define nvl_link_test_r() (0x00000048U) +#define nvl_link_test_mode_f(v) (((v)&0x1U) << 0U) +#define nvl_link_test_mode_m() (U32(0x1U) << 0U) +#define nvl_link_test_mode_v(r) (((r) >> 0U) & 0x1U) +#define nvl_link_test_mode_enable_v() (0x00000001U) +#define nvl_link_test_mode_enable_f() (0x1U) +#define nvl_link_test_auto_hwcfg_f(v) (((v)&0x1U) << 30U) +#define nvl_link_test_auto_hwcfg_m() (U32(0x1U) << 30U) +#define nvl_link_test_auto_hwcfg_v(r) (((r) >> 30U) & 0x1U) +#define nvl_link_test_auto_hwcfg_enable_v() (0x00000001U) +#define nvl_link_test_auto_hwcfg_enable_f() (0x40000000U) +#define nvl_link_test_auto_nvhs_f(v) (((v)&0x1U) << 31U) +#define nvl_link_test_auto_nvhs_m() (U32(0x1U) << 31U) +#define nvl_link_test_auto_nvhs_v(r) (((r) >> 31U) & 0x1U) +#define nvl_link_test_auto_nvhs_enable_v() (0x00000001U) +#define nvl_link_test_auto_nvhs_enable_f() (0x80000000U) +#define nvl_sl0_slsm_status_tx_r() (0x00002024U) +#define nvl_sl0_slsm_status_tx_substate_f(v) (((v)&0xfU) << 0U) +#define nvl_sl0_slsm_status_tx_substate_m() (U32(0xfU) << 0U) +#define nvl_sl0_slsm_status_tx_substate_v(r) (((r) >> 0U) & 0xfU) +#define nvl_sl0_slsm_status_tx_substate_stable_v() (0x00000000U) +#define nvl_sl0_slsm_status_tx_substate_stable_f() (0x0U) +#define nvl_sl0_slsm_status_tx_primary_state_f(v) (((v)&0xfU) << 4U) +#define nvl_sl0_slsm_status_tx_primary_state_m() (U32(0xfU) << 4U) +#define nvl_sl0_slsm_status_tx_primary_state_v(r) (((r) >> 4U) & 0xfU) +#define nvl_sl0_slsm_status_tx_primary_state_hs_v() (0x00000000U) +#define nvl_sl0_slsm_status_tx_primary_state_hs_f() (0x0U) +#define nvl_sl0_slsm_status_tx_primary_state_eighth_v() (0x00000004U) +#define nvl_sl0_slsm_status_tx_primary_state_eighth_f() (0x40U) +#define nvl_sl0_slsm_status_tx_primary_state_train_v() (0x00000005U) +#define nvl_sl0_slsm_status_tx_primary_state_train_f() (0x50U) +#define nvl_sl0_slsm_status_tx_primary_state_off_v() (0x00000007U) +#define nvl_sl0_slsm_status_tx_primary_state_off_f() (0x70U) +#define nvl_sl0_slsm_status_tx_primary_state_safe_v() (0x00000006U) +#define nvl_sl0_slsm_status_tx_primary_state_safe_f() (0x60U) +#define nvl_sl0_slsm_status_tx_primary_state_unknown_v() (0x0000000dU) +#define nvl_sl0_slsm_status_tx_primary_state_unknown_f() (0xd0U) +#define nvl_sl1_slsm_status_rx_r() (0x00003014U) +#define nvl_sl1_slsm_status_rx_substate_f(v) (((v)&0xfU) << 0U) +#define nvl_sl1_slsm_status_rx_substate_m() (U32(0xfU) << 0U) +#define nvl_sl1_slsm_status_rx_substate_v(r) (((r) >> 0U) & 0xfU) +#define nvl_sl1_slsm_status_rx_substate_stable_v() (0x00000000U) +#define nvl_sl1_slsm_status_rx_substate_stable_f() (0x0U) +#define nvl_sl1_slsm_status_rx_primary_state_f(v) (((v)&0xfU) << 4U) +#define nvl_sl1_slsm_status_rx_primary_state_m() (U32(0xfU) << 4U) +#define nvl_sl1_slsm_status_rx_primary_state_v(r) (((r) >> 4U) & 0xfU) +#define nvl_sl1_slsm_status_rx_primary_state_hs_v() (0x00000000U) +#define nvl_sl1_slsm_status_rx_primary_state_hs_f() (0x0U) +#define nvl_sl1_slsm_status_rx_primary_state_eighth_v() (0x00000004U) +#define nvl_sl1_slsm_status_rx_primary_state_eighth_f() (0x40U) +#define nvl_sl1_slsm_status_rx_primary_state_train_v() (0x00000005U) +#define nvl_sl1_slsm_status_rx_primary_state_train_f() (0x50U) +#define nvl_sl1_slsm_status_rx_primary_state_off_v() (0x00000007U) +#define nvl_sl1_slsm_status_rx_primary_state_off_f() (0x70U) +#define nvl_sl1_slsm_status_rx_primary_state_safe_v() (0x00000006U) +#define nvl_sl1_slsm_status_rx_primary_state_safe_f() (0x60U) +#define nvl_sl1_slsm_status_rx_primary_state_unknown_v() (0x0000000dU) +#define nvl_sl1_slsm_status_rx_primary_state_unknown_f() (0xd0U) +#define nvl_sl0_safe_ctrl2_tx_r() (0x00002008U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_f(v) (((v)&0x7ffU) << 0U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_m() (U32(0x7ffU) << 0U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_v(r) (((r) >> 0U) & 0x7ffU) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_init_v() (0x00000728U) +#define nvl_sl0_safe_ctrl2_tx_ctr_init_init_f() (0x728U) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(v) (((v)&0x1fU) << 11U) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_m() (U32(0x1fU) << 11U) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(r) (((r) >> 11U) & 0x1fU) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v() (0x0000000fU) +#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f() (0x7800U) +#define nvl_sl1_error_rate_ctrl_r() (0x00003284U) +#define nvl_sl1_error_rate_ctrl_short_threshold_man_f(v) (((v)&0x7U) << 0U) +#define nvl_sl1_error_rate_ctrl_short_threshold_man_m() (U32(0x7U) << 0U) +#define nvl_sl1_error_rate_ctrl_short_threshold_man_v(r) (((r) >> 0U) & 0x7U) +#define nvl_sl1_error_rate_ctrl_long_threshold_man_f(v) (((v)&0x7U) << 16U) +#define nvl_sl1_error_rate_ctrl_long_threshold_man_m() (U32(0x7U) << 16U) +#define nvl_sl1_error_rate_ctrl_long_threshold_man_v(r) (((r) >> 16U) & 0x7U) +#define nvl_sl1_rxslsm_timeout_2_r() (0x00003034U) +#define nvl_txiobist_configreg_r() (0x00002e14U) +#define nvl_txiobist_configreg_io_bist_mode_in_f(v) (((v)&0x1U) << 17U) +#define nvl_txiobist_configreg_io_bist_mode_in_m() (U32(0x1U) << 17U) +#define nvl_txiobist_configreg_io_bist_mode_in_v(r) (((r) >> 17U) & 0x1U) +#define nvl_txiobist_config_r() (0x00002e10U) +#define nvl_txiobist_config_dpg_prbsseedld_f(v) (((v)&0x1U) << 2U) +#define nvl_txiobist_config_dpg_prbsseedld_m() (U32(0x1U) << 2U) +#define nvl_txiobist_config_dpg_prbsseedld_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_r() (0x00000050U) +#define nvl_intr_tx_replay_f(v) (((v)&0x1U) << 0U) +#define nvl_intr_tx_replay_m() (U32(0x1U) << 0U) +#define nvl_intr_tx_replay_v(r) (((r) >> 0U) & 0x1U) +#define nvl_intr_tx_recovery_short_f(v) (((v)&0x1U) << 1U) +#define nvl_intr_tx_recovery_short_m() (U32(0x1U) << 1U) +#define nvl_intr_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) +#define nvl_intr_tx_recovery_long_f(v) (((v)&0x1U) << 2U) +#define nvl_intr_tx_recovery_long_m() (U32(0x1U) << 2U) +#define nvl_intr_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_tx_fault_ram_f(v) (((v)&0x1U) << 4U) +#define nvl_intr_tx_fault_ram_m() (U32(0x1U) << 4U) +#define nvl_intr_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) +#define nvl_intr_tx_fault_interface_f(v) (((v)&0x1U) << 5U) +#define nvl_intr_tx_fault_interface_m() (U32(0x1U) << 5U) +#define nvl_intr_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) +#define nvl_intr_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) +#define nvl_intr_tx_fault_sublink_change_m() (U32(0x1U) << 8U) +#define nvl_intr_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) +#define nvl_intr_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) +#define nvl_intr_rx_fault_sublink_change_m() (U32(0x1U) << 16U) +#define nvl_intr_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) +#define nvl_intr_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) +#define nvl_intr_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) +#define nvl_intr_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) +#define nvl_intr_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) +#define nvl_intr_rx_short_error_rate_m() (U32(0x1U) << 21U) +#define nvl_intr_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) +#define nvl_intr_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) +#define nvl_intr_rx_long_error_rate_m() (U32(0x1U) << 22U) +#define nvl_intr_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) +#define nvl_intr_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) +#define nvl_intr_rx_ila_trigger_m() (U32(0x1U) << 23U) +#define nvl_intr_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) +#define nvl_intr_rx_crc_counter_f(v) (((v)&0x1U) << 24U) +#define nvl_intr_rx_crc_counter_m() (U32(0x1U) << 24U) +#define nvl_intr_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) +#define nvl_intr_ltssm_fault_f(v) (((v)&0x1U) << 28U) +#define nvl_intr_ltssm_fault_m() (U32(0x1U) << 28U) +#define nvl_intr_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) +#define nvl_intr_ltssm_protocol_f(v) (((v)&0x1U) << 29U) +#define nvl_intr_ltssm_protocol_m() (U32(0x1U) << 29U) +#define nvl_intr_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) +#define nvl_intr_minion_request_f(v) (((v)&0x1U) << 30U) +#define nvl_intr_minion_request_m() (U32(0x1U) << 30U) +#define nvl_intr_minion_request_v(r) (((r) >> 30U) & 0x1U) +#define nvl_intr_sw2_r() (0x00000054U) +#define nvl_intr_minion_r() (0x00000060U) +#define nvl_intr_minion_tx_replay_f(v) (((v)&0x1U) << 0U) +#define nvl_intr_minion_tx_replay_m() (U32(0x1U) << 0U) +#define nvl_intr_minion_tx_replay_v(r) (((r) >> 0U) & 0x1U) +#define nvl_intr_minion_tx_recovery_short_f(v) (((v)&0x1U) << 1U) +#define nvl_intr_minion_tx_recovery_short_m() (U32(0x1U) << 1U) +#define nvl_intr_minion_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) +#define nvl_intr_minion_tx_recovery_long_f(v) (((v)&0x1U) << 2U) +#define nvl_intr_minion_tx_recovery_long_m() (U32(0x1U) << 2U) +#define nvl_intr_minion_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_minion_tx_fault_ram_f(v) (((v)&0x1U) << 4U) +#define nvl_intr_minion_tx_fault_ram_m() (U32(0x1U) << 4U) +#define nvl_intr_minion_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) +#define nvl_intr_minion_tx_fault_interface_f(v) (((v)&0x1U) << 5U) +#define nvl_intr_minion_tx_fault_interface_m() (U32(0x1U) << 5U) +#define nvl_intr_minion_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) +#define nvl_intr_minion_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) +#define nvl_intr_minion_tx_fault_sublink_change_m() (U32(0x1U) << 8U) +#define nvl_intr_minion_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) +#define nvl_intr_minion_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) +#define nvl_intr_minion_rx_fault_sublink_change_m() (U32(0x1U) << 16U) +#define nvl_intr_minion_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) +#define nvl_intr_minion_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) +#define nvl_intr_minion_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) +#define nvl_intr_minion_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) +#define nvl_intr_minion_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) +#define nvl_intr_minion_rx_short_error_rate_m() (U32(0x1U) << 21U) +#define nvl_intr_minion_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) +#define nvl_intr_minion_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) +#define nvl_intr_minion_rx_long_error_rate_m() (U32(0x1U) << 22U) +#define nvl_intr_minion_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) +#define nvl_intr_minion_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) +#define nvl_intr_minion_rx_ila_trigger_m() (U32(0x1U) << 23U) +#define nvl_intr_minion_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) +#define nvl_intr_minion_rx_crc_counter_f(v) (((v)&0x1U) << 24U) +#define nvl_intr_minion_rx_crc_counter_m() (U32(0x1U) << 24U) +#define nvl_intr_minion_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) +#define nvl_intr_minion_ltssm_fault_f(v) (((v)&0x1U) << 28U) +#define nvl_intr_minion_ltssm_fault_m() (U32(0x1U) << 28U) +#define nvl_intr_minion_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) +#define nvl_intr_minion_ltssm_protocol_f(v) (((v)&0x1U) << 29U) +#define nvl_intr_minion_ltssm_protocol_m() (U32(0x1U) << 29U) +#define nvl_intr_minion_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) +#define nvl_intr_minion_minion_request_f(v) (((v)&0x1U) << 30U) +#define nvl_intr_minion_minion_request_m() (U32(0x1U) << 30U) +#define nvl_intr_minion_minion_request_v(r) (((r) >> 30U) & 0x1U) +#define nvl_intr_nonstall_en_r() (0x0000005cU) +#define nvl_intr_stall_en_r() (0x00000058U) +#define nvl_intr_stall_en_tx_replay_f(v) (((v)&0x1U) << 0U) +#define nvl_intr_stall_en_tx_replay_m() (U32(0x1U) << 0U) +#define nvl_intr_stall_en_tx_replay_v(r) (((r) >> 0U) & 0x1U) +#define nvl_intr_stall_en_tx_recovery_short_f(v) (((v)&0x1U) << 1U) +#define nvl_intr_stall_en_tx_recovery_short_m() (U32(0x1U) << 1U) +#define nvl_intr_stall_en_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) +#define nvl_intr_stall_en_tx_recovery_short_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_recovery_short_enable_f() (0x2U) +#define nvl_intr_stall_en_tx_recovery_long_f(v) (((v)&0x1U) << 2U) +#define nvl_intr_stall_en_tx_recovery_long_m() (U32(0x1U) << 2U) +#define nvl_intr_stall_en_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) +#define nvl_intr_stall_en_tx_recovery_long_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_recovery_long_enable_f() (0x4U) +#define nvl_intr_stall_en_tx_fault_ram_f(v) (((v)&0x1U) << 4U) +#define nvl_intr_stall_en_tx_fault_ram_m() (U32(0x1U) << 4U) +#define nvl_intr_stall_en_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) +#define nvl_intr_stall_en_tx_fault_ram_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_fault_ram_enable_f() (0x10U) +#define nvl_intr_stall_en_tx_fault_interface_f(v) (((v)&0x1U) << 5U) +#define nvl_intr_stall_en_tx_fault_interface_m() (U32(0x1U) << 5U) +#define nvl_intr_stall_en_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) +#define nvl_intr_stall_en_tx_fault_interface_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_fault_interface_enable_f() (0x20U) +#define nvl_intr_stall_en_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) +#define nvl_intr_stall_en_tx_fault_sublink_change_m() (U32(0x1U) << 8U) +#define nvl_intr_stall_en_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) +#define nvl_intr_stall_en_tx_fault_sublink_change_enable_v() (0x00000001U) +#define nvl_intr_stall_en_tx_fault_sublink_change_enable_f() (0x100U) +#define nvl_intr_stall_en_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) +#define nvl_intr_stall_en_rx_fault_sublink_change_m() (U32(0x1U) << 16U) +#define nvl_intr_stall_en_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) +#define nvl_intr_stall_en_rx_fault_sublink_change_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_fault_sublink_change_enable_f() (0x10000U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_fault_dl_protocol_enable_f() (0x100000U) +#define nvl_intr_stall_en_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) +#define nvl_intr_stall_en_rx_short_error_rate_m() (U32(0x1U) << 21U) +#define nvl_intr_stall_en_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) +#define nvl_intr_stall_en_rx_short_error_rate_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_short_error_rate_enable_f() (0x200000U) +#define nvl_intr_stall_en_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) +#define nvl_intr_stall_en_rx_long_error_rate_m() (U32(0x1U) << 22U) +#define nvl_intr_stall_en_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) +#define nvl_intr_stall_en_rx_long_error_rate_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_long_error_rate_enable_f() (0x400000U) +#define nvl_intr_stall_en_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) +#define nvl_intr_stall_en_rx_ila_trigger_m() (U32(0x1U) << 23U) +#define nvl_intr_stall_en_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) +#define nvl_intr_stall_en_rx_ila_trigger_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_ila_trigger_enable_f() (0x800000U) +#define nvl_intr_stall_en_rx_crc_counter_f(v) (((v)&0x1U) << 24U) +#define nvl_intr_stall_en_rx_crc_counter_m() (U32(0x1U) << 24U) +#define nvl_intr_stall_en_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) +#define nvl_intr_stall_en_rx_crc_counter_enable_v() (0x00000001U) +#define nvl_intr_stall_en_rx_crc_counter_enable_f() (0x1000000U) +#define nvl_intr_stall_en_ltssm_fault_f(v) (((v)&0x1U) << 28U) +#define nvl_intr_stall_en_ltssm_fault_m() (U32(0x1U) << 28U) +#define nvl_intr_stall_en_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) +#define nvl_intr_stall_en_ltssm_fault_enable_v() (0x00000001U) +#define nvl_intr_stall_en_ltssm_fault_enable_f() (0x10000000U) +#define nvl_intr_stall_en_ltssm_protocol_f(v) (((v)&0x1U) << 29U) +#define nvl_intr_stall_en_ltssm_protocol_m() (U32(0x1U) << 29U) +#define nvl_intr_stall_en_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) +#define nvl_intr_stall_en_ltssm_protocol_enable_v() (0x00000001U) +#define nvl_intr_stall_en_ltssm_protocol_enable_f() (0x20000000U) +#define nvl_intr_stall_en_minion_request_f(v) (((v)&0x1U) << 30U) +#define nvl_intr_stall_en_minion_request_m() (U32(0x1U) << 30U) +#define nvl_intr_stall_en_minion_request_v(r) (((r) >> 30U) & 0x1U) +#define nvl_intr_stall_en_minion_request_enable_v() (0x00000001U) +#define nvl_intr_stall_en_minion_request_enable_f() (0x40000000U) +#define nvl_br0_cfg_cal_r() (0x0000281cU) +#define nvl_br0_cfg_cal_rxcal_f(v) (((v)&0x1U) << 0U) +#define nvl_br0_cfg_cal_rxcal_m() (U32(0x1U) << 0U) +#define nvl_br0_cfg_cal_rxcal_v(r) (((r) >> 0U) & 0x1U) +#define nvl_br0_cfg_cal_rxcal_on_v() (0x00000001U) +#define nvl_br0_cfg_cal_rxcal_on_f() (0x1U) +#define nvl_br0_cfg_status_cal_r() (0x00002838U) +#define nvl_br0_cfg_status_cal_rxcal_done_f(v) (((v)&0x1U) << 2U) +#define nvl_br0_cfg_status_cal_rxcal_done_m() (U32(0x1U) << 2U) +#define nvl_br0_cfg_status_cal_rxcal_done_v(r) (((r) >> 2U) & 0x1U) +#define nvl_sl0_link_rxdet_status_r() (0x00002228U) +#define nvl_sl0_link_rxdet_status_sts_v(r) (((r) >> 28U) & 0x3U) +#define nvl_sl0_link_rxdet_status_sts_found_v() (0x00000002U) +#define nvl_sl0_link_rxdet_status_sts_timeout_v() (0x00000003U) +#define nvl_clk_status_r() (0x0000001cU) +#define nvl_clk_status_txclk_sts_v(r) (((r) >> 19U) & 0x1U) +#define nvl_clk_status_txclk_sts_pll_clk_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlinkip_discovery_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlinkip_discovery_tu104.h index af3031654..77edf76e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlinkip_discovery_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlinkip_discovery_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlipt_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlipt_tu104.h index daff273f4..a632eff48 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlipt_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvlipt_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,224 +59,61 @@ #include #include -static inline u32 nvlipt_intr_control_link0_r(void) -{ - return 0x000004b4U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_r(void) -{ - return 0x00000524U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 nvlipt_err_uc_status_link0_dlprotocol_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 nvlipt_err_uc_status_link0_datapoisoned_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 nvlipt_err_uc_status_link0_flowcontrol_v(u32 r) -{ - return (r >> 13U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 nvlipt_err_uc_status_link0_responsetimeout_v(u32 r) -{ - return (r >> 14U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_f(u32 v) -{ - return (v & 0x1U) << 15U; -} -static inline u32 nvlipt_err_uc_status_link0_targeterror_v(u32 r) -{ - return (r >> 15U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_v(u32 r) -{ - return (r >> 17U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 nvlipt_err_uc_status_link0_malformedpacket_v(u32 r) -{ - return (r >> 18U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_v(u32 r) -{ - return (r >> 19U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 nvlipt_err_uc_status_link0_ucinternal_v(u32 r) -{ - return (r >> 22U) & 0x1U; -} -static inline u32 nvlipt_err_uc_mask_link0_r(void) -{ - return 0x00000528U; -} -static inline u32 nvlipt_err_uc_severity_link0_r(void) -{ - return 0x0000052cU; -} -static inline u32 nvlipt_err_uc_first_link0_r(void) -{ - return 0x00000530U; -} -static inline u32 nvlipt_err_uc_advisory_link0_r(void) -{ - return 0x00000534U; -} -static inline u32 nvlipt_err_c_status_link0_r(void) -{ - return 0x00000538U; -} -static inline u32 nvlipt_err_c_mask_link0_r(void) -{ - return 0x0000053cU; -} -static inline u32 nvlipt_err_c_first_link0_r(void) -{ - return 0x00000540U; -} -static inline u32 nvlipt_err_control_link0_r(void) -{ - return 0x00000544U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_r(void) -{ - return 0x000004b0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 nvlipt_scratch_cold_r(void) -{ - return 0x000007d4U; -} -static inline u32 nvlipt_scratch_cold_data_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 nvlipt_scratch_cold_data_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 nvlipt_scratch_cold_data_init_v(void) -{ - return 0xdeadbaadU; -} +#define nvlipt_intr_control_link0_r() (0x000004b4U) +#define nvlipt_intr_control_link0_stallenable_f(v) (((v)&0x1U) << 0U) +#define nvlipt_intr_control_link0_stallenable_m() (U32(0x1U) << 0U) +#define nvlipt_intr_control_link0_stallenable_v(r) (((r) >> 0U) & 0x1U) +#define nvlipt_intr_control_link0_nostallenable_f(v) (((v)&0x1U) << 1U) +#define nvlipt_intr_control_link0_nostallenable_m() (U32(0x1U) << 1U) +#define nvlipt_intr_control_link0_nostallenable_v(r) (((r) >> 1U) & 0x1U) +#define nvlipt_err_uc_status_link0_r() (0x00000524U) +#define nvlipt_err_uc_status_link0_dlprotocol_f(v) (((v)&0x1U) << 4U) +#define nvlipt_err_uc_status_link0_dlprotocol_v(r) (((r) >> 4U) & 0x1U) +#define nvlipt_err_uc_status_link0_datapoisoned_f(v) (((v)&0x1U) << 12U) +#define nvlipt_err_uc_status_link0_datapoisoned_v(r) (((r) >> 12U) & 0x1U) +#define nvlipt_err_uc_status_link0_flowcontrol_f(v) (((v)&0x1U) << 13U) +#define nvlipt_err_uc_status_link0_flowcontrol_v(r) (((r) >> 13U) & 0x1U) +#define nvlipt_err_uc_status_link0_responsetimeout_f(v) (((v)&0x1U) << 14U) +#define nvlipt_err_uc_status_link0_responsetimeout_v(r) (((r) >> 14U) & 0x1U) +#define nvlipt_err_uc_status_link0_targeterror_f(v) (((v)&0x1U) << 15U) +#define nvlipt_err_uc_status_link0_targeterror_v(r) (((r) >> 15U) & 0x1U) +#define nvlipt_err_uc_status_link0_unexpectedresponse_f(v) (((v)&0x1U) << 16U) +#define nvlipt_err_uc_status_link0_unexpectedresponse_v(r) (((r) >> 16U) & 0x1U) +#define nvlipt_err_uc_status_link0_receiveroverflow_f(v) (((v)&0x1U) << 17U) +#define nvlipt_err_uc_status_link0_receiveroverflow_v(r) (((r) >> 17U) & 0x1U) +#define nvlipt_err_uc_status_link0_malformedpacket_f(v) (((v)&0x1U) << 18U) +#define nvlipt_err_uc_status_link0_malformedpacket_v(r) (((r) >> 18U) & 0x1U) +#define nvlipt_err_uc_status_link0_stompedpacketreceived_f(v)\ + (((v)&0x1U) << 19U) +#define nvlipt_err_uc_status_link0_stompedpacketreceived_v(r)\ + (((r) >> 19U) & 0x1U) +#define nvlipt_err_uc_status_link0_unsupportedrequest_f(v) (((v)&0x1U) << 20U) +#define nvlipt_err_uc_status_link0_unsupportedrequest_v(r) (((r) >> 20U) & 0x1U) +#define nvlipt_err_uc_status_link0_ucinternal_f(v) (((v)&0x1U) << 22U) +#define nvlipt_err_uc_status_link0_ucinternal_v(r) (((r) >> 22U) & 0x1U) +#define nvlipt_err_uc_mask_link0_r() (0x00000528U) +#define nvlipt_err_uc_severity_link0_r() (0x0000052cU) +#define nvlipt_err_uc_first_link0_r() (0x00000530U) +#define nvlipt_err_uc_advisory_link0_r() (0x00000534U) +#define nvlipt_err_c_status_link0_r() (0x00000538U) +#define nvlipt_err_c_mask_link0_r() (0x0000053cU) +#define nvlipt_err_c_first_link0_r() (0x00000540U) +#define nvlipt_err_control_link0_r() (0x00000544U) +#define nvlipt_err_control_link0_fatalenable_f(v) (((v)&0x1U) << 1U) +#define nvlipt_err_control_link0_fatalenable_m() (U32(0x1U) << 1U) +#define nvlipt_err_control_link0_fatalenable_v(r) (((r) >> 1U) & 0x1U) +#define nvlipt_err_control_link0_nonfatalenable_f(v) (((v)&0x1U) << 2U) +#define nvlipt_err_control_link0_nonfatalenable_m() (U32(0x1U) << 2U) +#define nvlipt_err_control_link0_nonfatalenable_v(r) (((r) >> 2U) & 0x1U) +#define nvlipt_intr_control_common_r() (0x000004b0U) +#define nvlipt_intr_control_common_stallenable_f(v) (((v)&0x1U) << 0U) +#define nvlipt_intr_control_common_stallenable_m() (U32(0x1U) << 0U) +#define nvlipt_intr_control_common_stallenable_v(r) (((r) >> 0U) & 0x1U) +#define nvlipt_intr_control_common_nonstallenable_f(v) (((v)&0x1U) << 1U) +#define nvlipt_intr_control_common_nonstallenable_m() (U32(0x1U) << 1U) +#define nvlipt_intr_control_common_nonstallenable_v(r) (((r) >> 1U) & 0x1U) +#define nvlipt_scratch_cold_r() (0x000007d4U) +#define nvlipt_scratch_cold_data_f(v) (((v)&0xffffffffU) << 0U) +#define nvlipt_scratch_cold_data_v(r) (((r) >> 0U) & 0xffffffffU) +#define nvlipt_scratch_cold_data_init_v() (0xdeadbaadU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvtlc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvtlc_tu104.h index f18948059..54de8643b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvtlc_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_nvtlc_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,40 +59,13 @@ #include #include -static inline u32 nvtlc_tx_err_report_en_0_r(void) -{ - return 0x00000708U; -} -static inline u32 nvtlc_rx_err_report_en_0_r(void) -{ - return 0x00000f08U; -} -static inline u32 nvtlc_rx_err_report_en_1_r(void) -{ - return 0x00000f20U; -} -static inline u32 nvtlc_tx_err_status_0_r(void) -{ - return 0x00000700U; -} -static inline u32 nvtlc_rx_err_status_0_r(void) -{ - return 0x00000f00U; -} -static inline u32 nvtlc_rx_err_status_1_r(void) -{ - return 0x00000f18U; -} -static inline u32 nvtlc_tx_err_first_0_r(void) -{ - return 0x00000714U; -} -static inline u32 nvtlc_rx_err_first_0_r(void) -{ - return 0x00000f14U; -} -static inline u32 nvtlc_rx_err_first_1_r(void) -{ - return 0x00000f2cU; -} +#define nvtlc_tx_err_report_en_0_r() (0x00000708U) +#define nvtlc_rx_err_report_en_0_r() (0x00000f08U) +#define nvtlc_rx_err_report_en_1_r() (0x00000f20U) +#define nvtlc_tx_err_status_0_r() (0x00000700U) +#define nvtlc_rx_err_status_0_r() (0x00000f00U) +#define nvtlc_rx_err_status_1_r() (0x00000f18U) +#define nvtlc_tx_err_first_0_r() (0x00000714U) +#define nvtlc_rx_err_first_0_r() (0x00000f14U) +#define nvtlc_rx_err_first_1_r() (0x00000f2cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pbdma_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pbdma_tu104.h index 264338b89..54bbb44f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pbdma_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pbdma_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,584 +59,190 @@ #include #include -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004U; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffffU) << 10U; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10U) & 0x1fffffU; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffffU) << 3U; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3U; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1fU) << 16U; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_pb_header_type_m(void) -{ - return U32(0x7U) << 29U; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000U; -} -static inline u32 pbdma_pb_header_type_immd_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_gp_shadow_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000U; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004U; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfffU) << 2U; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2U) & 0xfffU; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16U) & 0x7U; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method2_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_method3_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040088U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_pb_count_value_v(u32 r) -{ - return (r >> 0U) & 0x1fffU; -} -static inline u32 pbdma_pb_count_value_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xfU) << 11U; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000fU; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800U; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffffU) << 15U; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffffU; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000U; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_status_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_channel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xfaceU; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffffU) << 9U; -} -static inline u32 pbdma_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_config_l2_evict_first_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_l2_evict_normal_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_config_ce_split_enable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_ce_split_disable_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_config_auth_level_non_privileged_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100U; -} -static inline u32 pbdma_config_userd_writeback_disable_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_config_userd_writeback_enable_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2U; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4U; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8U; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10U; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20U; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40U; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80U; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200U; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400U; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800U; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000U; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000U; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000U; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000U; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000U; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000U; -} -static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) -{ - return 0x100000U; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000U; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000U; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000U; -} -static inline u32 pbdma_intr_0_eng_reset_pending_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000U; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000U; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000U; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_1_ctxnotvalid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008U; -} -static inline u32 pbdma_target_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1fU; -} -static inline u32 pbdma_target_eng_ctx_valid_true_f(void) -{ - return 0x10000U; -} -static inline u32 pbdma_target_eng_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_ce_ctx_valid_true_f(void) -{ - return 0x20000U; -} -static inline u32 pbdma_target_ce_ctx_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) -{ - return 0x1000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) -{ - return 0x2000000U; -} -static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) -{ - return 0x3000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_true_f(void) -{ - return 0x20000000U; -} -static inline u32 pbdma_target_should_send_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) -{ - return 0x80000000U; -} -static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) -{ - return 0x0U; -} -static inline u32 pbdma_set_channel_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_set_channel_info_veid_f(u32 v) -{ - return (v & 0x3fU) << 8U; -} -static inline u32 pbdma_timeout_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32(i, 8192U)); -} -static inline u32 pbdma_timeout_period_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 pbdma_timeout_period_max_f(void) -{ - return 0xffffffffU; -} -static inline u32 pbdma_timeout_period_init_f(void) -{ - return 0x10000U; -} +#define pbdma_gp_entry1_r() (0x10000004U) +#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) +#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) +#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) +#define pbdma_gp_base_r(i)\ + (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base__size_1_v() (0x0000000cU) +#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) +#define pbdma_gp_base_rsvd_s() (3U) +#define pbdma_gp_base_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) +#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) +#define pbdma_gp_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_get_r(i)\ + (nvgpu_safe_add_u32(0x00040014U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_put_r(i)\ + (nvgpu_safe_add_u32(0x00040000U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_r(i)\ + (nvgpu_safe_add_u32(0x00040054U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_fetch_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040058U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_r(i)\ + (nvgpu_safe_add_u32(0x00040018U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_get_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004001cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_r(i)\ + (nvgpu_safe_add_u32(0x0004005cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_put_hi_r(i)\ + (nvgpu_safe_add_u32(0x00040060U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_r(i)\ + (nvgpu_safe_add_u32(0x00040084U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_header_method_zero_f() (0x0U) +#define pbdma_pb_header_subchannel_zero_f() (0x0U) +#define pbdma_pb_header_level_main_f() (0x0U) +#define pbdma_pb_header_first_true_f() (0x400000U) +#define pbdma_pb_header_type_m() (U32(0x7U) << 29U) +#define pbdma_pb_header_type_inc_f() (0x20000000U) +#define pbdma_pb_header_type_non_inc_f() (0x60000000U) +#define pbdma_pb_header_type_immd_f() (0x80000000U) +#define pbdma_hdr_shadow_r(i)\ + (nvgpu_safe_add_u32(0x00040118U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_0_r(i)\ + (nvgpu_safe_add_u32(0x00040110U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_gp_shadow_1_r(i)\ + (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_r(i)\ + (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) +#define pbdma_subdevice_status_active_f() (0x10000000U) +#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) +#define pbdma_method0_r(i)\ + (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method0_fifo_size_v() (0x00000004U) +#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) +#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) +#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) +#define pbdma_method0_first_true_f() (0x400000U) +#define pbdma_method0_valid_true_f() (0x80000000U) +#define pbdma_method1_r(i)\ + (nvgpu_safe_add_u32(0x000400c8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method2_r(i)\ + (nvgpu_safe_add_u32(0x000400d0U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_method3_r(i)\ + (nvgpu_safe_add_u32(0x000400d8U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_count_r(i)\ + (nvgpu_safe_add_u32(0x00040088U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_pb_count_value_v(r) (((r) >> 0U) & 0x1fffU) +#define pbdma_pb_count_value_zero_f() (0x0U) +#define pbdma_data0_r(i)\ + (nvgpu_safe_add_u32(0x000400c4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_r(i)\ + (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_acquire_retry_man_2_f() (0x2U) +#define pbdma_acquire_retry_exp_2_f() (0x100U) +#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) +#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) +#define pbdma_acquire_timeout_exp_max_f() (0x7800U) +#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) +#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) +#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) +#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) +#define pbdma_acquire_timeout_en_disable_f() (0x0U) +#define pbdma_status_r(i)\ + (nvgpu_safe_add_u32(0x00040100U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_channel_r(i)\ + (nvgpu_safe_add_u32(0x00040120U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_r(i)\ + (nvgpu_safe_add_u32(0x00040010U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_signature_hw_valid_f() (0xfaceU) +#define pbdma_signature_sw_zero_f() (0x0U) +#define pbdma_userd_r(i)\ + (nvgpu_safe_add_u32(0x00040008U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_target_vid_mem_f() (0x0U) +#define pbdma_userd_target_sys_mem_coh_f() (0x2U) +#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) +#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) +#define pbdma_config_r(i)\ + (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_config_l2_evict_first_f() (0x0U) +#define pbdma_config_l2_evict_normal_f() (0x1U) +#define pbdma_config_ce_split_enable_f() (0x0U) +#define pbdma_config_ce_split_disable_f() (0x10U) +#define pbdma_config_auth_level_non_privileged_f() (0x0U) +#define pbdma_config_auth_level_privileged_f() (0x100U) +#define pbdma_config_userd_writeback_disable_f() (0x0U) +#define pbdma_config_userd_writeback_enable_f() (0x1000U) +#define pbdma_userd_hi_r(i)\ + (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) +#define pbdma_hce_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) +#define pbdma_intr_0_r(i)\ + (nvgpu_safe_add_u32(0x00040108U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_0_memreq_v(r) (((r) >> 0U) & 0x1U) +#define pbdma_intr_0_memreq_pending_f() (0x1U) +#define pbdma_intr_0_memack_timeout_pending_f() (0x2U) +#define pbdma_intr_0_memack_extra_pending_f() (0x4U) +#define pbdma_intr_0_memdat_timeout_pending_f() (0x8U) +#define pbdma_intr_0_memdat_extra_pending_f() (0x10U) +#define pbdma_intr_0_memflush_pending_f() (0x20U) +#define pbdma_intr_0_memop_pending_f() (0x40U) +#define pbdma_intr_0_lbconnect_pending_f() (0x80U) +#define pbdma_intr_0_lback_timeout_pending_f() (0x200U) +#define pbdma_intr_0_lback_extra_pending_f() (0x400U) +#define pbdma_intr_0_lbdat_timeout_pending_f() (0x800U) +#define pbdma_intr_0_lbdat_extra_pending_f() (0x1000U) +#define pbdma_intr_0_gpfifo_pending_f() (0x2000U) +#define pbdma_intr_0_gpptr_pending_f() (0x4000U) +#define pbdma_intr_0_gpentry_pending_f() (0x8000U) +#define pbdma_intr_0_gpcrc_pending_f() (0x10000U) +#define pbdma_intr_0_pbptr_pending_f() (0x20000U) +#define pbdma_intr_0_pbentry_pending_f() (0x40000U) +#define pbdma_intr_0_pbcrc_pending_f() (0x80000U) +#define pbdma_intr_0_clear_faulted_error_pending_f() (0x100000U) +#define pbdma_intr_0_method_pending_f() (0x200000U) +#define pbdma_intr_0_methodcrc_pending_f() (0x400000U) +#define pbdma_intr_0_device_pending_f() (0x800000U) +#define pbdma_intr_0_eng_reset_pending_f() (0x1000000U) +#define pbdma_intr_0_semaphore_pending_f() (0x2000000U) +#define pbdma_intr_0_acquire_pending_f() (0x4000000U) +#define pbdma_intr_0_pri_pending_f() (0x8000000U) +#define pbdma_intr_0_no_ctxsw_seg_pending_f() (0x20000000U) +#define pbdma_intr_0_pbseg_pending_f() (0x40000000U) +#define pbdma_intr_0_signature_pending_f() (0x80000000U) +#define pbdma_intr_1_r(i)\ + (nvgpu_safe_add_u32(0x00040148U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_1_ctxnotvalid_m() (U32(0x1U) << 31U) +#define pbdma_intr_1_ctxnotvalid_pending_f() (0x80000000U) +#define pbdma_intr_en_0_r(i)\ + (nvgpu_safe_add_u32(0x0004010cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_en_1_r(i)\ + (nvgpu_safe_add_u32(0x0004014cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_r(i)\ + (nvgpu_safe_add_u32(0x0004013cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_r(i)\ + (nvgpu_safe_add_u32(0x00040140U, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_intr_stall_1_hce_illegal_op_enabled_f() (0x1U) +#define pbdma_udma_nop_r() (0x00000008U) +#define pbdma_target_r(i)\ + (nvgpu_safe_add_u32(0x000400acU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_target_engine_sw_f() (0x1fU) +#define pbdma_target_eng_ctx_valid_true_f() (0x10000U) +#define pbdma_target_eng_ctx_valid_false_f() (0x0U) +#define pbdma_target_ce_ctx_valid_true_f() (0x20000U) +#define pbdma_target_ce_ctx_valid_false_f() (0x0U) +#define pbdma_target_host_tsg_event_reason_pbdma_idle_f() (0x0U) +#define pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f()\ + (0x1000000U) +#define pbdma_target_host_tsg_event_reason_tsg_yield_f() (0x2000000U) +#define pbdma_target_host_tsg_event_reason_host_subchannel_switch_f()\ + (0x3000000U) +#define pbdma_target_should_send_tsg_event_true_f() (0x20000000U) +#define pbdma_target_should_send_tsg_event_false_f() (0x0U) +#define pbdma_target_needs_host_tsg_event_true_f() (0x80000000U) +#define pbdma_target_needs_host_tsg_event_false_f() (0x0U) +#define pbdma_set_channel_info_r(i)\ + (nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_set_channel_info_veid_f(v) (((v)&0x3fU) << 8U) +#define pbdma_timeout_r(i)\ + (nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U))) +#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U) +#define pbdma_timeout_period_max_f() (0xffffffffU) +#define pbdma_timeout_period_init_f() (0x10000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h index 12faea80f..3055b029e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_perf_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,208 +59,58 @@ #include #include -static inline u32 perf_pmmgpc_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmsys_perdomain_offset_v(void) -{ - return 0x00000200U; -} -static inline u32 perf_pmmgpc_base_v(void) -{ - return 0x00180000U; -} -static inline u32 perf_pmmgpc_extent_v(void) -{ - return 0x00183fffU; -} -static inline u32 perf_pmmsys_base_v(void) -{ - return 0x00240000U; -} -static inline u32 perf_pmmsys_extent_v(void) -{ - return 0x00243fffU; -} -static inline u32 perf_pmmfbp_base_v(void) -{ - return 0x00200000U; -} -static inline u32 perf_pmasys_control_r(void) -{ - return 0x0024a000U; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20U; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x0024a070U; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3U) << 28U; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28U) & 0x3U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000U; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0U; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x0024a074U; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x0024a078U; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x0024a07cU; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x0024a084U; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x0024a088U; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffffU) << 4U; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x0024a0a4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001U; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10U; -} -static inline u32 perf_pmmsys_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0024006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmsys_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmfbp_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmfbp_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} -static inline u32 perf_pmmgpc_engine_sel_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32(i, 512U)); -} -static inline u32 perf_pmmgpc_engine_sel__size_1_v(void) -{ - return 0x00000020U; -} +#define perf_pmmgpc_perdomain_offset_v() (0x00000200U) +#define perf_pmmsys_perdomain_offset_v() (0x00000200U) +#define perf_pmmgpc_base_v() (0x00180000U) +#define perf_pmmgpc_extent_v() (0x00183fffU) +#define perf_pmmsys_base_v() (0x00240000U) +#define perf_pmmsys_extent_v() (0x00243fffU) +#define perf_pmmfbp_base_v() (0x00200000U) +#define perf_pmasys_control_r() (0x0024a000U) +#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) +#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) +#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) +#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) +#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) +#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) +#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_mem_block_r() (0x0024a070U) +#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) +#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) +#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) +#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) +#define perf_pmasys_mem_block_target_lfb_f() (0x0U) +#define perf_pmasys_mem_block_target_sys_coh_v() (0x00000002U) +#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) +#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) +#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) +#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) +#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) +#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) +#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) +#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) +#define perf_pmasys_mem_block_valid_false_f() (0x0U) +#define perf_pmasys_outbase_r() (0x0024a074U) +#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_outbaseupper_r() (0x0024a078U) +#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) +#define perf_pmasys_outsize_r() (0x0024a07cU) +#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) +#define perf_pmasys_mem_bytes_r() (0x0024a084U) +#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_mem_bump_r() (0x0024a088U) +#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) +#define perf_pmasys_enginestatus_r() (0x0024a0a4U) +#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) +#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) +#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) +#define perf_pmmsys_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0024006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmsys_engine_sel__size_1_v() (0x00000020U) +#define perf_pmmfbp_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0020006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmfbp_engine_sel__size_1_v() (0x00000020U) +#define perf_pmmgpc_engine_sel_r(i)\ + (nvgpu_safe_add_u32(0x0018006cU, nvgpu_safe_mult_u32((i), 512U))) +#define perf_pmmgpc_engine_sel__size_1_v() (0x00000020U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pgsp_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pgsp_tu104.h index 0d7f9d6dd..93051d97f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pgsp_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pgsp_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,588 +59,156 @@ #include #include -static inline u32 pgsp_falcon_irqsset_r(void) -{ - return 0x00110000U; -} -static inline u32 pgsp_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pgsp_falcon_irqsclr_r(void) -{ - return 0x00110004U; -} -static inline u32 pgsp_falcon_irqstat_r(void) -{ - return 0x00110008U; -} -static inline u32 pgsp_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pgsp_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pgsp_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pgsp_falcon_irqmode_r(void) -{ - return 0x0011000cU; -} -static inline u32 pgsp_falcon_irqmset_r(void) -{ - return 0x00110010U; -} -static inline u32 pgsp_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqmclr_r(void) -{ - return 0x00110014U; -} -static inline u32 pgsp_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_irqmask_r(void) -{ - return 0x00110018U; -} -static inline u32 pgsp_falcon_irqdest_r(void) -{ - return 0x0011001cU; -} -static inline u32 pgsp_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pgsp_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pgsp_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pgsp_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pgsp_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pgsp_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pgsp_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pgsp_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pgsp_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pgsp_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pgsp_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pgsp_falcon_curctx_r(void) -{ - return 0x00110050U; -} -static inline u32 pgsp_falcon_nxtctx_r(void) -{ - return 0x00110054U; -} -static inline u32 pgsp_falcon_nxtctx_ctxptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_fb_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pgsp_falcon_nxtctx_ctxvalid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pgsp_falcon_mailbox0_r(void) -{ - return 0x00110040U; -} -static inline u32 pgsp_falcon_mailbox1_r(void) -{ - return 0x00110044U; -} -static inline u32 pgsp_falcon_itfen_r(void) -{ - return 0x00110048U; -} -static inline u32 pgsp_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_falcon_idlestate_r(void) -{ - return 0x0011004cU; -} -static inline u32 pgsp_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pgsp_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pgsp_falcon_os_r(void) -{ - return 0x00110080U; -} -static inline u32 pgsp_falcon_engctl_r(void) -{ - return 0x001100a4U; -} -static inline u32 pgsp_falcon_engctl_switch_context_true_f(void) -{ - return 0x8U; -} -static inline u32 pgsp_falcon_engctl_switch_context_false_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_falcon_cpuctl_r(void) -{ - return 0x00110100U; -} -static inline u32 pgsp_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pgsp_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pgsp_falcon_cpuctl_alias_r(void) -{ - return 0x00110130U; -} -static inline u32 pgsp_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pgsp_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pgsp_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pgsp_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pgsp_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pgsp_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pgsp_falcon_sctl_r(void) -{ - return 0x00110240U; -} -static inline u32 pgsp_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pgsp_falcon_bootvec_r(void) -{ - return 0x00110104U; -} -static inline u32 pgsp_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pgsp_falcon_dmactl_r(void) -{ - return 0x0011010cU; -} -static inline u32 pgsp_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pgsp_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pgsp_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pgsp_falcon_hwcfg_r(void) -{ - return 0x00110108U; -} -static inline u32 pgsp_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pgsp_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pgsp_falcon_dmatrfbase_r(void) -{ - return 0x00110110U; -} -static inline u32 pgsp_falcon_dmatrfbase1_r(void) -{ - return 0x00110128U; -} -static inline u32 pgsp_falcon_dmatrfmoffs_r(void) -{ - return 0x00110114U; -} -static inline u32 pgsp_falcon_dmatrfcmd_r(void) -{ - return 0x00110118U; -} -static inline u32 pgsp_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pgsp_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pgsp_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pgsp_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pgsp_falcon_dmatrffboffs_r(void) -{ - return 0x0011011cU; -} -static inline u32 pgsp_falcon_exterraddr_r(void) -{ - return 0x00110168U; -} -static inline u32 pgsp_falcon_exterrstat_r(void) -{ - return 0x0011016cU; -} -static inline u32 pgsp_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pgsp_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pgsp_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_r(void) -{ - return 0x00110200U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pgsp_sec2_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pgsp_sec2_falcon_icd_rdata_r(void) -{ - return 0x0011020cU; -} -static inline u32 pgsp_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x001101c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pgsp_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pgsp_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pgsp_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pgsp_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pgsp_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pgsp_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pgsp_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x001101c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pgsp_falcon_debug1_r(void) -{ - return 0x00110090U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 pgsp_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00110600U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pgsp_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 pgsp_falcon_engine_r(void) -{ - return 0x001103c0U; -} -static inline u32 pgsp_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 pgsp_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_r(void) -{ - return 0x00110624U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_init_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_disallow_f(void) -{ - return 0x0U; -} -static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_allow_f(void) -{ - return 0x80U; -} +#define pgsp_falcon_irqsset_r() (0x00110000U) +#define pgsp_falcon_irqsset_swgen0_set_f() (0x40U) +#define pgsp_falcon_irqsclr_r() (0x00110004U) +#define pgsp_falcon_irqstat_r() (0x00110008U) +#define pgsp_falcon_irqstat_halt_true_f() (0x10U) +#define pgsp_falcon_irqstat_exterr_true_f() (0x20U) +#define pgsp_falcon_irqstat_swgen0_true_f() (0x40U) +#define pgsp_falcon_irqmode_r() (0x0011000cU) +#define pgsp_falcon_irqmset_r() (0x00110010U) +#define pgsp_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pgsp_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pgsp_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pgsp_falcon_irqmclr_r() (0x00110014U) +#define pgsp_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pgsp_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pgsp_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pgsp_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_irqmask_r() (0x00110018U) +#define pgsp_falcon_irqdest_r() (0x0011001cU) +#define pgsp_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pgsp_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pgsp_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pgsp_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pgsp_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pgsp_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pgsp_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pgsp_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pgsp_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pgsp_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pgsp_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pgsp_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pgsp_falcon_curctx_r() (0x00110050U) +#define pgsp_falcon_nxtctx_r() (0x00110054U) +#define pgsp_falcon_nxtctx_ctxptr_f(v) (((v)&0xfffffffU) << 0U) +#define pgsp_falcon_nxtctx_ctxtgt_fb_f() (0x0U) +#define pgsp_falcon_nxtctx_ctxtgt_sys_coh_f() (0x20000000U) +#define pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f() (0x30000000U) +#define pgsp_falcon_nxtctx_ctxvalid_f(v) (((v)&0x1U) << 30U) +#define pgsp_falcon_mailbox0_r() (0x00110040U) +#define pgsp_falcon_mailbox1_r() (0x00110044U) +#define pgsp_falcon_itfen_r() (0x00110048U) +#define pgsp_falcon_itfen_ctxen_enable_f() (0x1U) +#define pgsp_falcon_idlestate_r() (0x0011004cU) +#define pgsp_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pgsp_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pgsp_falcon_os_r() (0x00110080U) +#define pgsp_falcon_engctl_r() (0x001100a4U) +#define pgsp_falcon_engctl_switch_context_true_f() (0x8U) +#define pgsp_falcon_engctl_switch_context_false_f() (0x0U) +#define pgsp_falcon_cpuctl_r() (0x00110100U) +#define pgsp_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pgsp_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pgsp_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pgsp_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pgsp_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pgsp_falcon_cpuctl_alias_r() (0x00110130U) +#define pgsp_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pgsp_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00110180U, nvgpu_safe_mult_u32((i), 16U))) +#define pgsp_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pgsp_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pgsp_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00110184U, nvgpu_safe_mult_u32((i), 16U))) +#define pgsp_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00110188U, nvgpu_safe_mult_u32((i), 16U))) +#define pgsp_falcon_sctl_r() (0x00110240U) +#define pgsp_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pgsp_falcon_bootvec_r() (0x00110104U) +#define pgsp_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pgsp_falcon_dmactl_r() (0x0011010cU) +#define pgsp_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pgsp_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pgsp_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define pgsp_falcon_hwcfg_r() (0x00110108U) +#define pgsp_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pgsp_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pgsp_falcon_dmatrfbase_r() (0x00110110U) +#define pgsp_falcon_dmatrfbase1_r() (0x00110128U) +#define pgsp_falcon_dmatrfmoffs_r() (0x00110114U) +#define pgsp_falcon_dmatrfcmd_r() (0x00110118U) +#define pgsp_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pgsp_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pgsp_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pgsp_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pgsp_falcon_dmatrffboffs_r() (0x0011011cU) +#define pgsp_falcon_exterraddr_r() (0x00110168U) +#define pgsp_falcon_exterrstat_r() (0x0011016cU) +#define pgsp_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pgsp_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pgsp_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pgsp_sec2_falcon_icd_cmd_r() (0x00110200U) +#define pgsp_sec2_falcon_icd_cmd_opc_s() (4U) +#define pgsp_sec2_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pgsp_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pgsp_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pgsp_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pgsp_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pgsp_sec2_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pgsp_sec2_falcon_icd_rdata_r() (0x0011020cU) +#define pgsp_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x001101c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pgsp_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pgsp_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pgsp_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pgsp_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pgsp_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pgsp_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pgsp_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x001101c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pgsp_falcon_debug1_r() (0x00110090U) +#define pgsp_falcon_debug1_ctxsw_mode_s() (1U) +#define pgsp_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define pgsp_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define pgsp_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define pgsp_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define pgsp_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x00110600U, nvgpu_safe_mult_u32((i), 4U))) +#define pgsp_fbif_transcfg_target_local_fb_f() (0x0U) +#define pgsp_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pgsp_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pgsp_fbif_transcfg_mem_type_s() (1U) +#define pgsp_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pgsp_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pgsp_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pgsp_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pgsp_fbif_transcfg_mem_type_physical_f() (0x4U) +#define pgsp_falcon_engine_r() (0x001103c0U) +#define pgsp_falcon_engine_reset_true_f() (0x1U) +#define pgsp_falcon_engine_reset_false_f() (0x0U) +#define pgsp_fbif_ctl_r() (0x00110624U) +#define pgsp_fbif_ctl_allow_phys_no_ctx_init_f() (0x0U) +#define pgsp_fbif_ctl_allow_phys_no_ctx_disallow_f() (0x0U) +#define pgsp_fbif_ctl_allow_phys_no_ctx_allow_f() (0x80U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pnvdec_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pnvdec_tu104.h index 73cb739b0..9fff69f38 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pnvdec_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pnvdec_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pnvdec_falcon_irqsset_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00830000U, nvgpu_safe_mult_u32(i, 16384U)); -} +#define pnvdec_falcon_irqsset_r(i)\ + (nvgpu_safe_add_u32(0x00830000U, nvgpu_safe_mult_u32((i), 16384U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pram_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pram_tu104.h index cdc66afe1..7b964beeb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pram_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pram_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,8 +59,6 @@ #include #include -static inline u32 pram_data032_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32(i, 4U)); -} +#define pram_data032_r(i)\ + (nvgpu_safe_add_u32(0x00700000U, nvgpu_safe_mult_u32((i), 4U))) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h index db4aff630..c28d706d3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,112 +59,33 @@ #include #include -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004cU; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0U) & 0x3fU; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000U; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3U; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048U; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050U; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001U; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058U; -} -static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) -{ - return (r >> 1U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005cU; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0U; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074U; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078U; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006cU; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} +#define pri_ringmaster_command_r() (0x0012004cU) +#define pri_ringmaster_command_cmd_m() (U32(0x3fU) << 0U) +#define pri_ringmaster_command_cmd_v(r) (((r) >> 0U) & 0x3fU) +#define pri_ringmaster_command_cmd_no_cmd_v() (0x00000000U) +#define pri_ringmaster_command_cmd_start_ring_f() (0x1U) +#define pri_ringmaster_command_cmd_ack_interrupt_f() (0x2U) +#define pri_ringmaster_command_cmd_enumerate_stations_f() (0x3U) +#define pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f() (0x0U) +#define pri_ringmaster_command_data_r() (0x00120048U) +#define pri_ringmaster_start_results_r() (0x00120050U) +#define pri_ringmaster_start_results_connectivity_v(r) (((r) >> 0U) & 0x1U) +#define pri_ringmaster_start_results_connectivity_pass_v() (0x00000001U) +#define pri_ringmaster_intr_status0_r() (0x00120058U) +#define pri_ringmaster_intr_status0_ring_start_conn_fault_v(r)\ + (((r) >> 0U) & 0x1U) +#define pri_ringmaster_intr_status0_disconnect_fault_v(r) (((r) >> 1U) & 0x1U) +#define pri_ringmaster_intr_status0_overflow_fault_v(r) (((r) >> 2U) & 0x1U) +#define pri_ringmaster_intr_status0_gbl_write_error_sys_v(r)\ + (((r) >> 8U) & 0x1U) +#define pri_ringmaster_intr_status1_r() (0x0012005cU) +#define pri_ringmaster_global_ctl_r() (0x00120060U) +#define pri_ringmaster_global_ctl_ring_reset_asserted_f() (0x1U) +#define pri_ringmaster_global_ctl_ring_reset_deasserted_f() (0x0U) +#define pri_ringmaster_enum_fbp_r() (0x00120074U) +#define pri_ringmaster_enum_fbp_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_gpc_r() (0x00120078U) +#define pri_ringmaster_enum_gpc_count_v(r) (((r) >> 0U) & 0x1fU) +#define pri_ringmaster_enum_ltc_r() (0x0012006cU) +#define pri_ringmaster_enum_ltc_count_v(r) (((r) >> 0U) & 0x1fU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h index 4e7736111..810db4df5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,20 +59,8 @@ #include #include -static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) -{ - return 0x00128120U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) -{ - return 0x00128124U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) -{ - return 0x00128128U; -} -static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) -{ - return 0x0012812cU; -} +#define pri_ringstation_gpc_gpc0_priv_error_adr_r() (0x00128120U) +#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U) +#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U) +#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h index de2b4b152..ba9baec4e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,12 @@ #include #include -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return U32(0x7U) << 0U; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1U; -} -static inline u32 pri_ringstation_sys_priv_error_adr_r(void) -{ - return 0x00122120U; -} -static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) -{ - return 0x00122124U; -} -static inline u32 pri_ringstation_sys_priv_error_info_r(void) -{ - return 0x00122128U; -} -static inline u32 pri_ringstation_sys_priv_error_code_r(void) -{ - return 0x0012212cU; -} +#define pri_ringstation_sys_decode_config_r() (0x00122204U) +#define pri_ringstation_sys_decode_config_ring_m() (U32(0x7U) << 0U) +#define pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f()\ + (0x1U) +#define pri_ringstation_sys_priv_error_adr_r() (0x00122120U) +#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U) +#define pri_ringstation_sys_priv_error_info_r() (0x00122128U) +#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h index 0631a3823..b3513ee27 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_proj_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,144 +59,39 @@ #include #include -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000U; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000U; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000U; -} -static inline u32 proj_gpc_priv_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000U; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_fbpa_base_v(void) -{ - return 0x00900000U; -} -static inline u32 proj_fbpa_shared_base_v(void) -{ - return 0x009a0000U; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000U; -} -static inline u32 proj_ppc_in_gpc_shared_base_v(void) -{ - return 0x00003e00U; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000U; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800U; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400U; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000U; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800U; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800U; -} -static inline u32 proj_smpc_base_v(void) -{ - return 0x00000200U; -} -static inline u32 proj_smpc_shared_base_v(void) -{ - return 0x00000300U; -} -static inline u32 proj_smpc_unique_base_v(void) -{ - return 0x00000600U; -} -static inline u32 proj_smpc_stride_v(void) -{ - return 0x00000100U; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x0000000dU; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x0000000cU; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000010U; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000006U; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000003U; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004U; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000002U; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020U; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008U; -} -static inline u32 proj_sm_stride_v(void) -{ - return 0x00000080U; -} +#define proj_gpc_base_v() (0x00500000U) +#define proj_gpc_shared_base_v() (0x00418000U) +#define proj_gpc_stride_v() (0x00008000U) +#define proj_gpc_priv_stride_v() (0x00000800U) +#define proj_ltc_stride_v() (0x00002000U) +#define proj_lts_stride_v() (0x00000200U) +#define proj_fbpa_base_v() (0x00900000U) +#define proj_fbpa_shared_base_v() (0x009a0000U) +#define proj_fbpa_stride_v() (0x00004000U) +#define proj_ppc_in_gpc_base_v() (0x00003000U) +#define proj_ppc_in_gpc_shared_base_v() (0x00003e00U) +#define proj_ppc_in_gpc_stride_v() (0x00000200U) +#define proj_rop_base_v() (0x00410000U) +#define proj_rop_shared_base_v() (0x00408800U) +#define proj_rop_stride_v() (0x00000400U) +#define proj_tpc_in_gpc_base_v() (0x00004000U) +#define proj_tpc_in_gpc_stride_v() (0x00000800U) +#define proj_tpc_in_gpc_shared_base_v() (0x00001800U) +#define proj_smpc_base_v() (0x00000200U) +#define proj_smpc_shared_base_v() (0x00000300U) +#define proj_smpc_unique_base_v() (0x00000600U) +#define proj_smpc_stride_v() (0x00000100U) +#define proj_host_num_engines_v() (0x0000000dU) +#define proj_host_num_pbdma_v() (0x0000000cU) +#define proj_scal_litter_num_tpc_per_gpc_v() (0x00000006U) +#define proj_scal_litter_num_fbps_v() (0x00000008U) +#define proj_scal_litter_num_fbpas_v() (0x00000010U) +#define proj_scal_litter_num_gpcs_v() (0x00000006U) +#define proj_scal_litter_num_pes_per_gpc_v() (0x00000003U) +#define proj_scal_litter_num_tpcs_per_pes_v() (0x00000002U) +#define proj_scal_litter_num_zcull_banks_v() (0x00000004U) +#define proj_scal_litter_num_sm_per_tpc_v() (0x00000002U) +#define proj_scal_max_gpcs_v() (0x00000020U) +#define proj_scal_max_tpc_per_gpc_v() (0x00000008U) +#define proj_sm_stride_v() (0x00000080U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_psec_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_psec_tu104.h index 81b5f115e..2816784f9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_psec_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_psec_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,732 +59,198 @@ #include #include -static inline u32 psec_falcon_irqsset_r(void) -{ - return 0x00840000U; -} -static inline u32 psec_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqsclr_r(void) -{ - return 0x00840004U; -} -static inline u32 psec_falcon_irqstat_r(void) -{ - return 0x00840008U; -} -static inline u32 psec_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 psec_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 psec_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 psec_falcon_irqmode_r(void) -{ - return 0x0084000cU; -} -static inline u32 psec_falcon_irqmset_r(void) -{ - return 0x00840010U; -} -static inline u32 psec_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_r(void) -{ - return 0x00840014U; -} -static inline u32 psec_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqmask_r(void) -{ - return 0x00840018U; -} -static inline u32 psec_falcon_irqdest_r(void) -{ - return 0x0084001cU; -} -static inline u32 psec_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 psec_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 psec_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 psec_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 psec_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 psec_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 psec_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 psec_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 psec_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 psec_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 psec_falcon_curctx_r(void) -{ - return 0x00840050U; -} -static inline u32 psec_falcon_nxtctx_r(void) -{ - return 0x00840054U; -} -static inline u32 psec_falcon_mailbox0_r(void) -{ - return 0x00840040U; -} -static inline u32 psec_falcon_mailbox1_r(void) -{ - return 0x00840044U; -} -static inline u32 psec_falcon_itfen_r(void) -{ - return 0x00840048U; -} -static inline u32 psec_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_idlestate_r(void) -{ - return 0x0084004cU; -} -static inline u32 psec_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 psec_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 psec_falcon_os_r(void) -{ - return 0x00840080U; -} -static inline u32 psec_falcon_engctl_r(void) -{ - return 0x008400a4U; -} -static inline u32 psec_falcon_cpuctl_r(void) -{ - return 0x00840100U; -} -static inline u32 psec_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 psec_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 psec_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 psec_falcon_cpuctl_alias_r(void) -{ - return 0x00840130U; -} -static inline u32 psec_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 psec_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 psec_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 psec_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 psec_falcon_sctl_r(void) -{ - return 0x00840240U; -} -static inline u32 psec_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 psec_falcon_bootvec_r(void) -{ - return 0x00840104U; -} -static inline u32 psec_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_falcon_dmactl_r(void) -{ - return 0x0084010cU; -} -static inline u32 psec_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 psec_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 psec_falcon_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 psec_falcon_hwcfg_r(void) -{ - return 0x00840108U; -} -static inline u32 psec_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 psec_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 psec_falcon_dmatrfbase_r(void) -{ - return 0x00840110U; -} -static inline u32 psec_falcon_dmatrfbase1_r(void) -{ - return 0x00840128U; -} -static inline u32 psec_falcon_dmatrfmoffs_r(void) -{ - return 0x00840114U; -} -static inline u32 psec_falcon_dmatrfcmd_r(void) -{ - return 0x00840118U; -} -static inline u32 psec_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 psec_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 psec_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 psec_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 psec_falcon_dmatrffboffs_r(void) -{ - return 0x0084011cU; -} -static inline u32 psec_falcon_exterraddr_r(void) -{ - return 0x00840168U; -} -static inline u32 psec_falcon_exterrstat_r(void) -{ - return 0x0084016cU; -} -static inline u32 psec_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 psec_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 psec_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 psec_sec2_falcon_icd_cmd_r(void) -{ - return 0x00840200U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 psec_sec2_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 psec_sec2_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 psec_sec2_falcon_icd_rdata_r(void) -{ - return 0x0084020cU; -} -static inline u32 psec_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x008401c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 psec_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 psec_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 psec_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x008401c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_falcon_debug1_r(void) -{ - return 0x00840090U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_s(void) -{ - return 1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_v(u32 r) -{ - return (r >> 16U) & 0x1U; -} -static inline u32 psec_falcon_debug1_ctxsw_mode_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840600U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 psec_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 psec_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 psec_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 psec_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 psec_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 psec_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} -static inline u32 psec_falcon_engine_r(void) -{ - return 0x008403c0U; -} -static inline u32 psec_falcon_engine_reset_true_f(void) -{ - return 0x1U; -} -static inline u32 psec_falcon_engine_reset_false_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_r(void) -{ - return 0x00840624U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_init_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_disallow_f(void) -{ - return 0x0U; -} -static inline u32 psec_fbif_ctl_allow_phys_no_ctx_allow_f(void) -{ - return 0x80U; -} -static inline u32 psec_hwcfg_r(void) -{ - return 0x00840abcU; -} -static inline u32 psec_hwcfg_emem_size_f(u32 v) -{ - return (v & 0x1ffU) << 0U; -} -static inline u32 psec_hwcfg_emem_size_m(void) -{ - return U32(0x1ffU) << 0U; -} -static inline u32 psec_hwcfg_emem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 psec_falcon_hwcfg1_r(void) -{ - return 0x0084012cU; -} -static inline u32 psec_falcon_hwcfg1_dmem_tag_width_f(u32 v) -{ - return (v & 0x1fU) << 21U; -} -static inline u32 psec_falcon_hwcfg1_dmem_tag_width_m(void) -{ - return U32(0x1fU) << 21U; -} -static inline u32 psec_falcon_hwcfg1_dmem_tag_width_v(u32 r) -{ - return (r >> 21U) & 0x1fU; -} -static inline u32 psec_ememc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840ac0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_ememc__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 psec_ememc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 psec_ememc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 psec_ememc_blk_v(u32 r) -{ - return (r >> 8U) & 0xffU; -} -static inline u32 psec_ememc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 psec_ememc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 psec_ememc_offs_v(u32 r) -{ - return (r >> 2U) & 0x3fU; -} -static inline u32 psec_ememc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 psec_ememc_aincw_m(void) -{ - return U32(0x1U) << 24U; -} -static inline u32 psec_ememc_aincw_v(u32 r) -{ - return (r >> 24U) & 0x1U; -} -static inline u32 psec_ememc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 psec_ememc_aincr_m(void) -{ - return U32(0x1U) << 25U; -} -static inline u32 psec_ememc_aincr_v(u32 r) -{ - return (r >> 25U) & 0x1U; -} -static inline u32 psec_ememd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840ac4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_ememd__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 psec_ememd_data_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_ememd_data_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 psec_ememd_data_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_msgq_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840c80U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_msgq_head_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 psec_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_msgq_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840c84U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_msgq_tail_val_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 psec_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840c00U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_queue_head_address_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 psec_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 psec_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00840c04U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 psec_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 psec_queue_tail_address_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 psec_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} +#define psec_falcon_irqsset_r() (0x00840000U) +#define psec_falcon_irqsset_swgen0_set_f() (0x40U) +#define psec_falcon_irqsclr_r() (0x00840004U) +#define psec_falcon_irqstat_r() (0x00840008U) +#define psec_falcon_irqstat_halt_true_f() (0x10U) +#define psec_falcon_irqstat_exterr_true_f() (0x20U) +#define psec_falcon_irqstat_swgen0_true_f() (0x40U) +#define psec_falcon_irqmode_r() (0x0084000cU) +#define psec_falcon_irqmset_r() (0x00840010U) +#define psec_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define psec_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define psec_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define psec_falcon_irqmclr_r() (0x00840014U) +#define psec_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define psec_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define psec_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define psec_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_irqmask_r() (0x00840018U) +#define psec_falcon_irqdest_r() (0x0084001cU) +#define psec_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define psec_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define psec_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define psec_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define psec_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define psec_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define psec_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define psec_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define psec_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define psec_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define psec_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define psec_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define psec_falcon_curctx_r() (0x00840050U) +#define psec_falcon_nxtctx_r() (0x00840054U) +#define psec_falcon_mailbox0_r() (0x00840040U) +#define psec_falcon_mailbox1_r() (0x00840044U) +#define psec_falcon_itfen_r() (0x00840048U) +#define psec_falcon_itfen_ctxen_enable_f() (0x1U) +#define psec_falcon_idlestate_r() (0x0084004cU) +#define psec_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define psec_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define psec_falcon_os_r() (0x00840080U) +#define psec_falcon_engctl_r() (0x008400a4U) +#define psec_falcon_cpuctl_r() (0x00840100U) +#define psec_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define psec_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define psec_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define psec_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define psec_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define psec_falcon_cpuctl_alias_r() (0x00840130U) +#define psec_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define psec_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x00840180U, nvgpu_safe_mult_u32((i), 16U))) +#define psec_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define psec_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define psec_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x00840184U, nvgpu_safe_mult_u32((i), 16U))) +#define psec_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x00840188U, nvgpu_safe_mult_u32((i), 16U))) +#define psec_falcon_sctl_r() (0x00840240U) +#define psec_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define psec_falcon_bootvec_r() (0x00840104U) +#define psec_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define psec_falcon_dmactl_r() (0x0084010cU) +#define psec_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define psec_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define psec_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) +#define psec_falcon_hwcfg_r() (0x00840108U) +#define psec_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define psec_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define psec_falcon_dmatrfbase_r() (0x00840110U) +#define psec_falcon_dmatrfbase1_r() (0x00840128U) +#define psec_falcon_dmatrfmoffs_r() (0x00840114U) +#define psec_falcon_dmatrfcmd_r() (0x00840118U) +#define psec_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define psec_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define psec_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define psec_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define psec_falcon_dmatrffboffs_r() (0x0084011cU) +#define psec_falcon_exterraddr_r() (0x00840168U) +#define psec_falcon_exterrstat_r() (0x0084016cU) +#define psec_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define psec_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define psec_falcon_exterrstat_valid_true_v() (0x00000001U) +#define psec_sec2_falcon_icd_cmd_r() (0x00840200U) +#define psec_sec2_falcon_icd_cmd_opc_s() (4U) +#define psec_sec2_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define psec_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define psec_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define psec_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define psec_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define psec_sec2_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define psec_sec2_falcon_icd_rdata_r() (0x0084020cU) +#define psec_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x008401c0U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define psec_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define psec_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define psec_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define psec_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define psec_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define psec_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x008401c4U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_falcon_debug1_r() (0x00840090U) +#define psec_falcon_debug1_ctxsw_mode_s() (1U) +#define psec_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) +#define psec_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) +#define psec_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) +#define psec_falcon_debug1_ctxsw_mode_init_f() (0x0U) +#define psec_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x00840600U, nvgpu_safe_mult_u32((i), 4U))) +#define psec_fbif_transcfg_target_local_fb_f() (0x0U) +#define psec_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define psec_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define psec_fbif_transcfg_mem_type_s() (1U) +#define psec_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define psec_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define psec_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define psec_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define psec_fbif_transcfg_mem_type_physical_f() (0x4U) +#define psec_falcon_engine_r() (0x008403c0U) +#define psec_falcon_engine_reset_true_f() (0x1U) +#define psec_falcon_engine_reset_false_f() (0x0U) +#define psec_fbif_ctl_r() (0x00840624U) +#define psec_fbif_ctl_allow_phys_no_ctx_init_f() (0x0U) +#define psec_fbif_ctl_allow_phys_no_ctx_disallow_f() (0x0U) +#define psec_fbif_ctl_allow_phys_no_ctx_allow_f() (0x80U) +#define psec_hwcfg_r() (0x00840abcU) +#define psec_hwcfg_emem_size_f(v) (((v)&0x1ffU) << 0U) +#define psec_hwcfg_emem_size_m() (U32(0x1ffU) << 0U) +#define psec_hwcfg_emem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define psec_falcon_hwcfg1_r() (0x0084012cU) +#define psec_falcon_hwcfg1_dmem_tag_width_f(v) (((v)&0x1fU) << 21U) +#define psec_falcon_hwcfg1_dmem_tag_width_m() (U32(0x1fU) << 21U) +#define psec_falcon_hwcfg1_dmem_tag_width_v(r) (((r) >> 21U) & 0x1fU) +#define psec_ememc_r(i)\ + (nvgpu_safe_add_u32(0x00840ac0U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_ememc__size_1_v() (0x00000004U) +#define psec_ememc_blk_f(v) (((v)&0xffU) << 8U) +#define psec_ememc_blk_m() (U32(0xffU) << 8U) +#define psec_ememc_blk_v(r) (((r) >> 8U) & 0xffU) +#define psec_ememc_offs_f(v) (((v)&0x3fU) << 2U) +#define psec_ememc_offs_m() (U32(0x3fU) << 2U) +#define psec_ememc_offs_v(r) (((r) >> 2U) & 0x3fU) +#define psec_ememc_aincw_f(v) (((v)&0x1U) << 24U) +#define psec_ememc_aincw_m() (U32(0x1U) << 24U) +#define psec_ememc_aincw_v(r) (((r) >> 24U) & 0x1U) +#define psec_ememc_aincr_f(v) (((v)&0x1U) << 25U) +#define psec_ememc_aincr_m() (U32(0x1U) << 25U) +#define psec_ememc_aincr_v(r) (((r) >> 25U) & 0x1U) +#define psec_ememd_r(i)\ + (nvgpu_safe_add_u32(0x00840ac4U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_ememd__size_1_v() (0x00000004U) +#define psec_ememd_data_f(v) (((v)&0xffffffffU) << 0U) +#define psec_ememd_data_m() (U32(0xffffffffU) << 0U) +#define psec_ememd_data_v(r) (((r) >> 0U) & 0xffffffffU) +#define psec_msgq_head_r(i)\ + (nvgpu_safe_add_u32(0x00840c80U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define psec_msgq_head_val_m() (U32(0xffffffffU) << 0U) +#define psec_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define psec_msgq_tail_r(i)\ + (nvgpu_safe_add_u32(0x00840c84U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define psec_msgq_tail_val_m() (U32(0xffffffffU) << 0U) +#define psec_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define psec_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x00840c00U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define psec_queue_head_address_m() (U32(0xffffffffU) << 0U) +#define psec_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define psec_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x00840c04U, nvgpu_safe_mult_u32((i), 8U))) +#define psec_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define psec_queue_tail_address_m() (U32(0xffffffffU) << 0U) +#define psec_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h index a41dad7ef..d1acec0f1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,956 +59,264 @@ #include #include -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000U; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004U; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008U; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10U; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20U; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40U; -} -static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) -{ - return 0x800U; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00cU; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010U; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmset_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014U; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018U; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01cU; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 3U; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 9U; -} -static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 13U; -} -static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 14U; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1U) << 17U; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1U) << 18U; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1U) << 19U; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1U) << 21U; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1U) << 22U; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1U) << 23U; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) -{ - return (v & 0x1U) << 27U; -} -static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) -{ - return (v & 0x1U) << 28U; -} -static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) -{ - return (v & 0x1U) << 29U; -} -static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050U; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054U; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040U; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044U; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048U; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1U; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04cU; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1U) & 0x7fffU; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080U; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4U; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100U; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return U32(0x1U) << 6U; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6U) & 0x1U; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130U; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return U32(0x1U) << 20U; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20U) & 0x1U; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32(i, 16U)); -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240U; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4U; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104U; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10cU; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108U; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0U) & 0x1ffU; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9U) & 0x1ffU; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110U; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128U; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114U; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118U; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7U) << 8U; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7U) << 12U; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11cU; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168U; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16cU; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0U) & 0xfU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8U; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xeU; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20cU; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return U32(0x3fU) << 2U; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return U32(0xffU) << 8U; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1U) << 25U; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480U; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffffU) << 0U; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000U; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000U; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1U) << 30U; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488U; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ffU; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48cU; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return U32(0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010U; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0U) & 0xffU; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000008U; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8U; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4ccU; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0U) & 0xffffffffU; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010be40U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1U; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000U; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010bf80U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0U) & 0x7fffffffU; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010bfc0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2U; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0U; -} -static inline u32 pwr_pmu_idle_threshold_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010be00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_idle_threshold_value_f(u32 v) -{ - return (v & 0x7fffffffU) << 0U; -} -static inline u32 pwr_pmu_idle_intr_r(void) -{ - return 0x0010a9e8U; -} -static inline u32 pwr_pmu_idle_intr_en_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_en_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 pwr_pmu_idle_intr_en_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_r(void) -{ - return 0x0010a9ecU; -} -static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void) -{ - return 0x00000001U; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32(i, 8U)); -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004U; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000cU; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0U; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4U; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7acU; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8U; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988U; -} -static inline u32 pwr_pmu_bar0_host_error_r(void) -{ - return 0x0010a990U; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void) -{ - return U32(0x1U) << 3U; -} -static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void) -{ - return U32(0x1U) << 30U; -} -static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1U; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0U; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4U; -} +#define pwr_falcon_irqsset_r() (0x0010a000U) +#define pwr_falcon_irqsset_swgen0_set_f() (0x40U) +#define pwr_falcon_irqsclr_r() (0x0010a004U) +#define pwr_falcon_irqstat_r() (0x0010a008U) +#define pwr_falcon_irqstat_halt_true_f() (0x10U) +#define pwr_falcon_irqstat_exterr_true_f() (0x20U) +#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) +#define pwr_falcon_irqstat_ext_second_true_f() (0x800U) +#define pwr_falcon_irqmode_r() (0x0010a00cU) +#define pwr_falcon_irqmset_r() (0x0010a010U) +#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmset_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmset_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqmset_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqmset_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqmset_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqmset_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqmset_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqmclr_r() (0x0010a014U) +#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqmclr_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqmclr_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqmclr_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqmclr_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqmclr_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqmclr_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqmask_r() (0x0010a018U) +#define pwr_falcon_irqdest_r() (0x0010a01cU) +#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) +#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) +#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) +#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) +#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_irqdest_host_ext_ctxe_f(v) (((v)&0x1U) << 8U) +#define pwr_falcon_irqdest_host_ext_limitv_f(v) (((v)&0x1U) << 9U) +#define pwr_falcon_irqdest_host_ext_second_f(v) (((v)&0x1U) << 11U) +#define pwr_falcon_irqdest_host_ext_therm_f(v) (((v)&0x1U) << 12U) +#define pwr_falcon_irqdest_host_ext_miscio_f(v) (((v)&0x1U) << 13U) +#define pwr_falcon_irqdest_host_ext_rttimer_f(v) (((v)&0x1U) << 14U) +#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) +#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) +#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) +#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) +#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) +#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) +#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) +#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) +#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) +#define pwr_falcon_irqdest_target_ext_ctxe_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_irqdest_target_ext_limitv_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_irqdest_target_ext_second_f(v) (((v)&0x1U) << 27U) +#define pwr_falcon_irqdest_target_ext_therm_f(v) (((v)&0x1U) << 28U) +#define pwr_falcon_irqdest_target_ext_miscio_f(v) (((v)&0x1U) << 29U) +#define pwr_falcon_irqdest_target_ext_rttimer_f(v) (((v)&0x1U) << 30U) +#define pwr_falcon_curctx_r() (0x0010a050U) +#define pwr_falcon_nxtctx_r() (0x0010a054U) +#define pwr_falcon_mailbox0_r() (0x0010a040U) +#define pwr_falcon_mailbox1_r() (0x0010a044U) +#define pwr_falcon_itfen_r() (0x0010a048U) +#define pwr_falcon_itfen_ctxen_enable_f() (0x1U) +#define pwr_falcon_idlestate_r() (0x0010a04cU) +#define pwr_falcon_idlestate_falcon_busy_v(r) (((r) >> 0U) & 0x1U) +#define pwr_falcon_idlestate_ext_busy_v(r) (((r) >> 1U) & 0x7fffU) +#define pwr_falcon_os_r() (0x0010a080U) +#define pwr_falcon_engctl_r() (0x0010a0a4U) +#define pwr_falcon_cpuctl_r() (0x0010a100U) +#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) +#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) +#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) +#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) +#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) +#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) +#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) +#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) +#define pwr_falcon_imemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_imemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_imemt_r(i)\ + (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) +#define pwr_falcon_sctl_r() (0x0010a240U) +#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) +#define pwr_falcon_bootvec_r() (0x0010a104U) +#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_falcon_dmactl_r() (0x0010a10cU) +#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) +#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) +#define pwr_falcon_hwcfg_r() (0x0010a108U) +#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) +#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) +#define pwr_falcon_dmatrfbase_r() (0x0010a110U) +#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) +#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) +#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) +#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) +#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) +#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) +#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) +#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) +#define pwr_falcon_exterraddr_r() (0x0010a168U) +#define pwr_falcon_exterrstat_r() (0x0010a16cU) +#define pwr_falcon_exterrstat_valid_m() (U32(0x1U) << 31U) +#define pwr_falcon_exterrstat_valid_v(r) (((r) >> 31U) & 0x1U) +#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) +#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) +#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) +#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) +#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) +#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) +#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) +#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) +#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) +#define pwr_falcon_dmemc_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) +#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) +#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) +#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) +#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) +#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) +#define pwr_falcon_dmemd_r(i)\ + (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_new_instblk_r() (0x0010a480U) +#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) +#define pwr_pmu_new_instblk_target_fb_f() (0x0U) +#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) +#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) +#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) +#define pwr_pmu_mutex_id_r() (0x0010a488U) +#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) +#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) +#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) +#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) +#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) +#define pwr_pmu_mutex_r(i)\ + (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mutex__size_1_v() (0x00000010U) +#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) +#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) +#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) +#define pwr_pmu_queue_head_r(i)\ + (nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_head__size_1_v() (0x00000008U) +#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_queue_tail_r(i)\ + (nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_queue_tail__size_1_v() (0x00000008U) +#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_head_r() (0x0010a4c8U) +#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) +#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) +#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) +#define pwr_pmu_idle_mask_r(i)\ + (nvgpu_safe_add_u32(0x0010be40U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U) +#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) +#define pwr_pmu_idle_count_r(i)\ + (nvgpu_safe_add_u32(0x0010bf80U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) +#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) +#define pwr_pmu_idle_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x0010bfc0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) +#define pwr_pmu_idle_ctrl_value_busy_f() (0x2U) +#define pwr_pmu_idle_ctrl_value_always_f() (0x3U) +#define pwr_pmu_idle_ctrl_filter_m() (U32(0x1U) << 2U) +#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) +#define pwr_pmu_idle_threshold_r(i)\ + (nvgpu_safe_add_u32(0x0010be00U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) +#define pwr_pmu_idle_intr_r() (0x0010a9e8U) +#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) +#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) +#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) +#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) +#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) +#define pwr_pmu_idle_intr_status_intr_clear_v() (0x00000001U) +#define pwr_pmu_idle_mask_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_mask_1_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_idle_ctrl_supp_r(i)\ + (nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U))) +#define pwr_pmu_debug_r(i)\ + (nvgpu_safe_add_u32(0x0010a5c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_debug__size_1_v() (0x00000004U) +#define pwr_pmu_mailbox_r(i)\ + (nvgpu_safe_add_u32(0x0010a450U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_mailbox__size_1_v() (0x0000000cU) +#define pwr_pmu_bar0_addr_r() (0x0010a7a0U) +#define pwr_pmu_bar0_data_r() (0x0010a7a4U) +#define pwr_pmu_bar0_ctl_r() (0x0010a7acU) +#define pwr_pmu_bar0_timeout_r() (0x0010a7a8U) +#define pwr_pmu_bar0_fecs_error_r() (0x0010a988U) +#define pwr_pmu_bar0_host_error_r() (0x0010a990U) +#define pwr_pmu_bar0_error_status_r() (0x0010a7b0U) +#define pwr_pmu_bar0_error_status_timeout_host_m() (U32(0x1U) << 0U) +#define pwr_pmu_bar0_error_status_timeout_fecs_m() (U32(0x1U) << 1U) +#define pwr_pmu_bar0_error_status_cmd_hwerr_m() (U32(0x1U) << 2U) +#define pwr_pmu_bar0_error_status_err_cmd_m() (U32(0x1U) << 3U) +#define pwr_pmu_bar0_error_status_hosterr_m() (U32(0x1U) << 30U) +#define pwr_pmu_bar0_error_status_fecserr_m() (U32(0x1U) << 31U) +#define pwr_pmu_pg_idlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6c0U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_ppuidlefilth_r(i)\ + (nvgpu_safe_add_u32(0x0010a6e8U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_idle_cnt_r(i)\ + (nvgpu_safe_add_u32(0x0010a710U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_pmu_pg_intren_r(i)\ + (nvgpu_safe_add_u32(0x0010a760U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_r(i)\ + (nvgpu_safe_add_u32(0x0010ae00U, nvgpu_safe_mult_u32((i), 4U))) +#define pwr_fbif_transcfg_target_local_fb_f() (0x0U) +#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) +#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) +#define pwr_fbif_transcfg_mem_type_s() (1U) +#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) +#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) +#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) +#define pwr_fbif_transcfg_mem_type_physical_f() (0x4U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ram_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ram_tu104.h index 604aa1dbd..52b74a868 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ram_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ram_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,736 +59,199 @@ #include #include -static inline u32 ram_in_ramfc_s(void) -{ - return 4096U; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0U; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2U; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3U; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4U; -} -static inline u32 ram_in_page_dir_base_vol_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20U; -} -static inline u32 ram_in_use_ver2_pt_format_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_m(void) -{ - return U32(0x1U) << 10U; -} -static inline u32 ram_in_use_ver2_pt_format_w(void) -{ - return 128U; -} -static inline u32 ram_in_use_ver2_pt_format_true_f(void) -{ - return 0x400U; -} -static inline u32 ram_in_use_ver2_pt_format_false_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return U32(0x1U) << 11U; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128U; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800U; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128U; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129U; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0U; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8U; -} -static inline u32 ram_in_engine_wfi_mode_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_engine_wfi_mode_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_mode_physical_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_mode_virtual_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_engine_wfi_target_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_engine_wfi_target_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_engine_wfi_target_local_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_engine_wfi_ptr_lo_w(void) -{ - return 132U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_in_engine_wfi_ptr_hi_w(void) -{ - return 133U; -} -static inline u32 ram_in_engine_wfi_veid_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 ram_in_engine_wfi_veid_w(void) -{ - return 134U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) -{ - return 136U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) -{ - return 137U; -} -static inline u32 ram_in_sc_pdb_valid_w(u32 i) -{ - return 166U + ((i*1U)/32U); -} -static inline u32 ram_in_sc_pdb_valid__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) -{ - return (v & 0x3U) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) -{ - return (v & 0x1U) << (2U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_vol_w(u32 i) -{ - return 168U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) -{ - return (v & 0x1U) << (4U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) -{ - return (v & 0x1U) << (5U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) -{ - return (v & 0x1U) << (10U + i*0U); -} -static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) -{ - return (v & 0x1U) << (11U + i*0U); -} -static inline u32 ram_in_sc_big_page_size__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_big_page_size_64kb_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) -{ - return (v & 0xfffffU) << (12U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_lo_w(u32 i) -{ - return 168U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) -{ - return (v & 0xffffffffU) << (0U + i*0U); -} -static inline u32 ram_in_sc_page_dir_base_hi_w(u32 i) -{ - return 169U + ((i*128U)/32U); -} -static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_target_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) -{ - return (v & 0x1U) << 10U; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_big_page_size_0_f(u32 v) -{ - return (v & 0x1U) << 11U; -} -static inline u32 ram_in_sc_big_page_size_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) -{ - return 168U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) -{ - return 169U; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000cU; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000U; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0U; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2U; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3U; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4U; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5U; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6U; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7U; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8U; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9U; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12U; -} -static inline u32 ram_fc_sem_addr_hi_w(void) -{ - return 14U; -} -static inline u32 ram_fc_sem_addr_lo_w(void) -{ - return 15U; -} -static inline u32 ram_fc_sem_payload_lo_w(void) -{ - return 16U; -} -static inline u32 ram_fc_sem_payload_hi_w(void) -{ - return 39U; -} -static inline u32 ram_fc_sem_execute_w(void) -{ - return 17U; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18U; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19U; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20U; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21U; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22U; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23U; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24U; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33U; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34U; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37U; -} -static inline u32 ram_fc_target_w(void) -{ - return 43U; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57U; -} -static inline u32 ram_fc_config_w(void) -{ - return 61U; -} -static inline u32 ram_fc_set_channel_info_w(void) -{ - return 63U; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009U; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200U; -} -static inline u32 ram_userd_put_w(void) -{ - return 16U; -} -static inline u32 ram_userd_get_w(void) -{ - return 17U; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18U; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19U; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24U; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34U; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35U; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22U; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23U; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000010U; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 ram_rl_entry_type_channel_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_type_tsg_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) -{ - return (v & 0x1U) << 1U; -} -static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) -{ - return (v & 0x3U) << 4U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) -{ - return (v & 0x3U) << 6U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) -{ - return 0x00000002U; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) -{ - return (v & 0xffffffU) << 8U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) -{ - return (v & 0xfffffU) << 12U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) -{ - return (v & 0xffffffffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) -{ - return 0x00000003U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) -{ - return (v & 0xffU) << 24U; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0xffU) << 0U; -} -static inline u32 ram_rl_entry_tsg_length_init_v(void) -{ - return 0x00000000U; -} -static inline u32 ram_rl_entry_tsg_length_min_v(void) -{ - return 0x00000001U; -} -static inline u32 ram_rl_entry_tsg_length_max_v(void) -{ - return 0x00000080U; -} -static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) -{ - return (v & 0xfffU) << 0U; -} -static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008U; -} -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000cU; -} +#define ram_in_ramfc_s() (4096U) +#define ram_in_ramfc_w() (0U) +#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_page_dir_base_target_w() (128U) +#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) +#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) +#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) +#define ram_in_page_dir_base_vol_w() (128U) +#define ram_in_page_dir_base_vol_true_f() (0x4U) +#define ram_in_page_dir_base_vol_false_f() (0x0U) +#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) +#define ram_in_page_dir_base_fault_replay_tex_w() (128U) +#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) +#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) +#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) +#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) +#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) +#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) +#define ram_in_use_ver2_pt_format_w() (128U) +#define ram_in_use_ver2_pt_format_true_f() (0x400U) +#define ram_in_use_ver2_pt_format_false_f() (0x0U) +#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) +#define ram_in_big_page_size_m() (U32(0x1U) << 11U) +#define ram_in_big_page_size_w() (128U) +#define ram_in_big_page_size_128kb_f() (0x0U) +#define ram_in_big_page_size_64kb_f() (0x800U) +#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_page_dir_base_lo_w() (128U) +#define ram_in_page_dir_base_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_page_dir_base_hi_w() (129U) +#define ram_in_engine_cs_w() (132U) +#define ram_in_engine_cs_wfi_v() (0x00000000U) +#define ram_in_engine_cs_wfi_f() (0x0U) +#define ram_in_engine_cs_fg_v() (0x00000001U) +#define ram_in_engine_cs_fg_f() (0x8U) +#define ram_in_engine_wfi_mode_f(v) (((v)&0x1U) << 2U) +#define ram_in_engine_wfi_mode_w() (132U) +#define ram_in_engine_wfi_mode_physical_v() (0x00000000U) +#define ram_in_engine_wfi_mode_virtual_v() (0x00000001U) +#define ram_in_engine_wfi_target_f(v) (((v)&0x3U) << 0U) +#define ram_in_engine_wfi_target_w() (132U) +#define ram_in_engine_wfi_target_sys_mem_coh_v() (0x00000002U) +#define ram_in_engine_wfi_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_in_engine_wfi_target_local_mem_v() (0x00000000U) +#define ram_in_engine_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_engine_wfi_ptr_lo_w() (132U) +#define ram_in_engine_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) +#define ram_in_engine_wfi_ptr_hi_w() (133U) +#define ram_in_engine_wfi_veid_f(v) (((v)&0x3fU) << 0U) +#define ram_in_engine_wfi_veid_w() (134U) +#define ram_in_eng_method_buffer_addr_lo_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_eng_method_buffer_addr_lo_w() (136U) +#define ram_in_eng_method_buffer_addr_hi_f(v) (((v)&0x1ffffU) << 0U) +#define ram_in_eng_method_buffer_addr_hi_w() (137U) +#define ram_in_sc_pdb_valid_w(i)\ + (166U + ((i*1U)/32U)) +#define ram_in_sc_pdb_valid__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_f(v, i)\ + (((v) & 0x3) << (0U + i*0U)) +#define ram_in_sc_page_dir_base_target__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_vid_mem_v() (0x00000000U) +#define ram_in_sc_page_dir_base_target_invalid_v() (0x00000001U) +#define ram_in_sc_page_dir_base_target_sys_mem_coh_v() (0x00000002U) +#define ram_in_sc_page_dir_base_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_in_sc_page_dir_base_vol_f(v, i)\ + (((v) & 0x1) << (2U + i*0U)) +#define ram_in_sc_page_dir_base_vol_w(i)\ + (168U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_vol__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_vol_true_v() (0x00000001U) +#define ram_in_sc_page_dir_base_vol_false_v() (0x00000000U) +#define ram_in_sc_page_dir_base_fault_replay_tex_f(v, i)\ + (((v) & 0x1) << (4U + i*0U)) +#define ram_in_sc_page_dir_base_fault_replay_tex__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_fault_replay_tex_enabled_v() (0x00000001U) +#define ram_in_sc_page_dir_base_fault_replay_tex_disabled_v() (0x00000000U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_f(v, i)\ + (((v) & 0x1) << (5U + i*0U)) +#define ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v() (0x00000001U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v() (0x00000000U) +#define ram_in_sc_use_ver2_pt_format_f(v, i)\ + (((v) & 0x1) << (10U + i*0U)) +#define ram_in_sc_use_ver2_pt_format__size_1_v() (0x00000040U) +#define ram_in_sc_use_ver2_pt_format_false_v() (0x00000000U) +#define ram_in_sc_use_ver2_pt_format_true_v() (0x00000001U) +#define ram_in_sc_big_page_size_f(v, i)\ + (((v) & 0x1) << (11U + i*0U)) +#define ram_in_sc_big_page_size__size_1_v() (0x00000040U) +#define ram_in_sc_big_page_size_64kb_v() (0x00000001U) +#define ram_in_sc_page_dir_base_lo_f(v, i)\ + (((v) & 0xfffff) << (12U + i*0U)) +#define ram_in_sc_page_dir_base_lo_w(i)\ + (168U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_lo__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_hi_f(v, i)\ + (((v) & 0xffffffff) << (0U + i*0U)) +#define ram_in_sc_page_dir_base_hi_w(i)\ + (169U + ((i*128U)/32U)) +#define ram_in_sc_page_dir_base_hi__size_1_v() (0x00000040U) +#define ram_in_sc_page_dir_base_target_0_f(v) (((v)&0x3U) << 0U) +#define ram_in_sc_page_dir_base_target_0_w() (168U) +#define ram_in_sc_page_dir_base_vol_0_f(v) (((v)&0x1U) << 2U) +#define ram_in_sc_page_dir_base_vol_0_w() (168U) +#define ram_in_sc_page_dir_base_fault_replay_tex_0_f(v) (((v)&0x1U) << 4U) +#define ram_in_sc_page_dir_base_fault_replay_tex_0_w() (168U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_0_f(v) (((v)&0x1U) << 5U) +#define ram_in_sc_page_dir_base_fault_replay_gcc_0_w() (168U) +#define ram_in_sc_use_ver2_pt_format_0_f(v) (((v)&0x1U) << 10U) +#define ram_in_sc_use_ver2_pt_format_0_w() (168U) +#define ram_in_sc_big_page_size_0_f(v) (((v)&0x1U) << 11U) +#define ram_in_sc_big_page_size_0_w() (168U) +#define ram_in_sc_page_dir_base_lo_0_f(v) (((v)&0xfffffU) << 12U) +#define ram_in_sc_page_dir_base_lo_0_w() (168U) +#define ram_in_sc_page_dir_base_hi_0_f(v) (((v)&0xffffffffU) << 0U) +#define ram_in_sc_page_dir_base_hi_0_w() (169U) +#define ram_in_base_shift_v() (0x0000000cU) +#define ram_in_alloc_size_v() (0x00001000U) +#define ram_fc_size_val_v() (0x00000200U) +#define ram_fc_gp_put_w() (0U) +#define ram_fc_userd_w() (2U) +#define ram_fc_userd_hi_w() (3U) +#define ram_fc_signature_w() (4U) +#define ram_fc_gp_get_w() (5U) +#define ram_fc_pb_get_w() (6U) +#define ram_fc_pb_get_hi_w() (7U) +#define ram_fc_pb_top_level_get_w() (8U) +#define ram_fc_pb_top_level_get_hi_w() (9U) +#define ram_fc_acquire_w() (12U) +#define ram_fc_sem_addr_hi_w() (14U) +#define ram_fc_sem_addr_lo_w() (15U) +#define ram_fc_sem_payload_lo_w() (16U) +#define ram_fc_sem_payload_hi_w() (39U) +#define ram_fc_sem_execute_w() (17U) +#define ram_fc_gp_base_w() (18U) +#define ram_fc_gp_base_hi_w() (19U) +#define ram_fc_gp_fetch_w() (20U) +#define ram_fc_pb_fetch_w() (21U) +#define ram_fc_pb_fetch_hi_w() (22U) +#define ram_fc_pb_put_w() (23U) +#define ram_fc_pb_put_hi_w() (24U) +#define ram_fc_pb_header_w() (33U) +#define ram_fc_pb_count_w() (34U) +#define ram_fc_subdevice_w() (37U) +#define ram_fc_target_w() (43U) +#define ram_fc_hce_ctrl_w() (57U) +#define ram_fc_config_w() (61U) +#define ram_fc_set_channel_info_w() (63U) +#define ram_userd_base_shift_v() (0x00000009U) +#define ram_userd_chan_size_v() (0x00000200U) +#define ram_userd_put_w() (16U) +#define ram_userd_get_w() (17U) +#define ram_userd_ref_w() (18U) +#define ram_userd_put_hi_w() (19U) +#define ram_userd_top_level_get_w() (22U) +#define ram_userd_top_level_get_hi_w() (23U) +#define ram_userd_get_hi_w() (24U) +#define ram_userd_gp_get_w() (34U) +#define ram_userd_gp_put_w() (35U) +#define ram_userd_gp_top_level_get_w() (22U) +#define ram_userd_gp_top_level_get_hi_w() (23U) +#define ram_rl_entry_size_v() (0x00000010U) +#define ram_rl_entry_type_f(v) (((v)&0x1U) << 0U) +#define ram_rl_entry_type_channel_v() (0x00000000U) +#define ram_rl_entry_type_tsg_v() (0x00000001U) +#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_runqueue_selector_f(v) (((v)&0x1U) << 1U) +#define ram_rl_entry_chan_inst_target_f(v) (((v)&0x3U) << 4U) +#define ram_rl_entry_chan_inst_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_rl_entry_chan_inst_target_sys_mem_coh_v() (0x00000002U) +#define ram_rl_entry_chan_inst_target_vid_mem_v() (0x00000000U) +#define ram_rl_entry_chan_userd_target_f(v) (((v)&0x3U) << 6U) +#define ram_rl_entry_chan_userd_target_vid_mem_v() (0x00000000U) +#define ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v() (0x00000001U) +#define ram_rl_entry_chan_userd_target_sys_mem_coh_v() (0x00000002U) +#define ram_rl_entry_chan_userd_target_sys_mem_ncoh_v() (0x00000003U) +#define ram_rl_entry_chan_userd_ptr_lo_f(v) (((v)&0xffffffU) << 8U) +#define ram_rl_entry_chan_userd_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_inst_ptr_lo_f(v) (((v)&0xfffffU) << 12U) +#define ram_rl_entry_chan_inst_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) +#define ram_rl_entry_tsg_timeslice_scale_f(v) (((v)&0xfU) << 16U) +#define ram_rl_entry_tsg_timeslice_scale_3_v() (0x00000003U) +#define ram_rl_entry_tsg_timeslice_timeout_f(v) (((v)&0xffU) << 24U) +#define ram_rl_entry_tsg_timeslice_timeout_128_v() (0x00000080U) +#define ram_rl_entry_tsg_length_f(v) (((v)&0xffU) << 0U) +#define ram_rl_entry_tsg_length_init_v() (0x00000000U) +#define ram_rl_entry_tsg_length_min_v() (0x00000001U) +#define ram_rl_entry_tsg_length_max_v() (0x00000080U) +#define ram_rl_entry_tsg_tsgid_f(v) (((v)&0xfffU) << 0U) +#define ram_rl_entry_chan_userd_ptr_align_shift_v() (0x00000008U) +#define ram_rl_entry_chan_userd_align_shift_v() (0x00000008U) +#define ram_rl_entry_chan_inst_ptr_align_shift_v() (0x0000000cU) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_therm_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_therm_tu104.h index 3d624f5ff..ac0824008 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_therm_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_therm_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,248 +59,69 @@ #include #include -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024U; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050U; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130U; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1U) << 24U; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1U; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2U; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return U32(0x3U) << 2U; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_m(void) -{ - return U32(0x1U) << 4U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) -{ - return 0x0U; -} -static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) -{ - return 0x10U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return U32(0x1fU) << 8U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return U32(0x7U) << 13U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xfU) << 20U; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return U32(0xfU) << 20U; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288U; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028cU; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return U32(0xffffffffU) << 0U; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return U32(0x3fU) << 16U; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16U) & 0x3fU; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0U; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return U32(0x3fU) << 0U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xeU; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return U32(0x3fU) << 6U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return U32(0x3fU) << 12U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return U32(0x3fU) << 18U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3fU) << 24U; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return U32(0x3fU) << 24U; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0U; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1U; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1U; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4U; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffffU) << 0U; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000U; -} -static inline u32 therm_i2cs_sensor_00_r(void) -{ - return 0x00020400U; -} +#define therm_weight_1_r() (0x00020024U) +#define therm_config1_r() (0x00020050U) +#define therm_config2_r() (0x00020130U) +#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) +#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) +#define therm_gate_ctrl_r(i)\ + (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) +#define therm_gate_ctrl_eng_clk_run_f() (0x0U) +#define therm_gate_ctrl_eng_clk_auto_f() (0x1U) +#define therm_gate_ctrl_eng_clk_stop_f() (0x2U) +#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) +#define therm_gate_ctrl_blk_clk_run_f() (0x0U) +#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) +#define therm_gate_ctrl_idle_holdoff_m() (U32(0x1U) << 4U) +#define therm_gate_ctrl_idle_holdoff_off_f() (0x0U) +#define therm_gate_ctrl_idle_holdoff_on_f() (0x10U) +#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) +#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) +#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) +#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) +#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) +#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) +#define therm_fecs_idle_filter_r() (0x00020288U) +#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_hubmmu_idle_filter_r() (0x0002028cU) +#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) +#define therm_clk_slowdown_r(i)\ + (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) +#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) +#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) +#define therm_grad_stepping_table_r(i)\ + (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) +#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) +#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) +#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) +#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) +#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) +#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) +#define therm_grad_stepping0_r() (0x000202c0U) +#define therm_grad_stepping0_feature_s() (1U) +#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) +#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) +#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) +#define therm_grad_stepping0_feature_enable_f() (0x1U) +#define therm_grad_stepping1_r() (0x000202c4U) +#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) +#define therm_clk_timing_r(i)\ + (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) +#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) +#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) +#define therm_i2cs_sensor_00_r() (0x00020400U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h index 53552214d..6578d0454 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,60 +59,18 @@ #include #include -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080U; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return U32(0xffffffU) << 0U; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0U) & 0xffffffU; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return U32(0x1U) << 31U; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000U; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0U; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084U; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088U; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908cU; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400U; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410U; -} +#define timer_pri_timeout_r() (0x00009080U) +#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) +#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) +#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) +#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) +#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) +#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) +#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) +#define timer_pri_timeout_en_en_disabled_f() (0x0U) +#define timer_pri_timeout_save_0_r() (0x00009084U) +#define timer_pri_timeout_save_1_r() (0x00009088U) +#define timer_pri_timeout_fecs_errcode_r() (0x0000908cU) +#define timer_time_0_r() (0x00009400U) +#define timer_time_1_r() (0x00009410U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_top_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_top_tu104.h index 11f424f62..95c5beee6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_top_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_top_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,220 +59,59 @@ #include #include -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430U; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434U; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438U; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_fbpas_r(void) -{ - return 0x0002243cU; -} -static inline u32 top_num_fbpas_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450U; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245cU; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454U; -} -static inline u32 top_num_ces_r(void) -{ - return 0x00022444U; -} -static inline u32 top_num_ces_value_v(u32 r) -{ - return (r >> 0U) & 0x1fU; -} -static inline u32 top_device_info_r(u32 i) -{ - return nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040U; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31U) & 0x1U; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_chain_disable_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21U) & 0xfU; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15U) & 0x1fU; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9U) & 0x1fU; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2U) & 0x1fffffffU; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0U; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xcU; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013U; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4cU; -} -static inline u32 top_device_info_type_enum_ioctrl_v(void) -{ - return 0x00000012U; -} -static inline u32 top_device_info_type_enum_ioctrl_f(void) -{ - return 0x48U; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 top_device_info_engine_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4U) & 0x1U; -} -static inline u32 top_device_info_runlist_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3U) & 0x1U; -} -static inline u32 top_device_info_intr_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_reset_valid_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002U; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001U; -} -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000003U; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30U) & 0x1U; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000U; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26U) & 0xfU; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12U) & 0xfffU; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000cU; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3U) & 0x7fU; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001U; -} +#define top_num_gpcs_r() (0x00022430U) +#define top_num_gpcs_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_tpc_per_gpc_r() (0x00022434U) +#define top_tpc_per_gpc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbps_r() (0x00022438U) +#define top_num_fbps_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_fbpas_r() (0x0002243cU) +#define top_num_fbpas_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_ltc_per_fbp_r() (0x00022450U) +#define top_ltc_per_fbp_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_slices_per_ltc_r() (0x0002245cU) +#define top_slices_per_ltc_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_num_ltcs_r() (0x00022454U) +#define top_num_ces_r() (0x00022444U) +#define top_num_ces_value_v(r) (((r) >> 0U) & 0x1fU) +#define top_device_info_r(i)\ + (nvgpu_safe_add_u32(0x00022700U, nvgpu_safe_mult_u32((i), 4U))) +#define top_device_info__size_1_v() (0x00000040U) +#define top_device_info_chain_v(r) (((r) >> 31U) & 0x1U) +#define top_device_info_chain_enable_v() (0x00000001U) +#define top_device_info_chain_disable_v() (0x00000000U) +#define top_device_info_engine_enum_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_runlist_enum_v(r) (((r) >> 21U) & 0xfU) +#define top_device_info_intr_enum_v(r) (((r) >> 15U) & 0x1fU) +#define top_device_info_reset_enum_v(r) (((r) >> 9U) & 0x1fU) +#define top_device_info_type_enum_v(r) (((r) >> 2U) & 0x1fffffffU) +#define top_device_info_type_enum_graphics_v() (0x00000000U) +#define top_device_info_type_enum_graphics_f() (0x0U) +#define top_device_info_type_enum_copy2_v() (0x00000003U) +#define top_device_info_type_enum_copy2_f() (0xcU) +#define top_device_info_type_enum_lce_v() (0x00000013U) +#define top_device_info_type_enum_lce_f() (0x4cU) +#define top_device_info_type_enum_ioctrl_v() (0x00000012U) +#define top_device_info_type_enum_ioctrl_f() (0x48U) +#define top_device_info_engine_v(r) (((r) >> 5U) & 0x1U) +#define top_device_info_engine_valid_v() (0x00000001U) +#define top_device_info_runlist_v(r) (((r) >> 4U) & 0x1U) +#define top_device_info_runlist_valid_v() (0x00000001U) +#define top_device_info_intr_v(r) (((r) >> 3U) & 0x1U) +#define top_device_info_intr_valid_v() (0x00000001U) +#define top_device_info_reset_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_reset_valid_v() (0x00000001U) +#define top_device_info_entry_v(r) (((r) >> 0U) & 0x3U) +#define top_device_info_entry_not_valid_v() (0x00000000U) +#define top_device_info_entry_enum_v() (0x00000002U) +#define top_device_info_entry_data_v() (0x00000001U) +#define top_device_info_entry_engine_type_v() (0x00000003U) +#define top_device_info_data_type_v(r) (((r) >> 30U) & 0x1U) +#define top_device_info_data_type_enum2_v() (0x00000000U) +#define top_device_info_data_inst_id_v(r) (((r) >> 26U) & 0xfU) +#define top_device_info_data_pri_base_v(r) (((r) >> 12U) & 0xfffU) +#define top_device_info_data_pri_base_align_v() (0x0000000cU) +#define top_device_info_data_fault_id_enum_v(r) (((r) >> 3U) & 0x7fU) +#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U) +#define top_device_info_data_fault_id_valid_v() (0x00000001U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h index e385c2d17..2a140c43c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,144 +59,42 @@ #include #include -static inline u32 trim_sys_nvlink_uphy_cfg_r(void) -{ - return 0x00132410U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v) -{ - return (v & 0x3ffU) << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void) -{ - return U32(0x3ffU) << 0U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r) -{ - return (r >> 0U) & 0x3ffU; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v) -{ - return (v & 0x1U) << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void) -{ - return U32(0x1U) << 12U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r) -{ - return (r >> 12U) & 0x1U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v) -{ - return (v & 0xffU) << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void) -{ - return U32(0xffU) << 16U; -} -static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r) -{ - return (r >> 16U) & 0xffU; -} -static inline u32 trim_sys_nvlink0_ctrl_r(void) -{ - return 0x00132420U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r) -{ - return (r >> 0U) & 0x1U; -} -static inline u32 trim_sys_nvlink0_status_r(void) -{ - return 0x00132424U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v) -{ - return (v & 0x1U) << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_m(void) -{ - return U32(0x1U) << 5U; -} -static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r) -{ - return (r >> 5U) & 0x1U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_r(void) -{ - return 0x001371c4U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v) -{ - return (v & 0x3U) << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void) -{ - return U32(0x3U) << 16U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r) -{ - return (r >> 16U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f(void) -{ - return 0x30000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void) -{ - return U32(0x3U) << 0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v(void) -{ - return 0x00000000U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f(void) -{ - return 0x0U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v(void) -{ - return 0x00000002U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f(void) -{ - return 0x2U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v(void) -{ - return 0x00000003U; -} -static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void) -{ - return 0x3U; -} +#define trim_sys_nvlink_uphy_cfg_r() (0x00132410U) +#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(v)\ + (((v)&0x3ffU) << 0U) +#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m()\ + (U32(0x3ffU) << 0U) +#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(r)\ + (((r) >> 0U) & 0x3ffU) +#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(v) (((v)&0x1U) << 12U) +#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m() (U32(0x1U) << 12U) +#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(r) (((r) >> 12U) & 0x1U) +#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(v) (((v)&0xffU) << 16U) +#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m() (U32(0xffU) << 16U) +#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(r) (((r) >> 16U) & 0xffU) +#define trim_sys_nvlink0_ctrl_r() (0x00132420U) +#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(v) (((v)&0x1U) << 0U) +#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m() (U32(0x1U) << 0U) +#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(r) (((r) >> 0U) & 0x1U) +#define trim_sys_nvlink0_status_r() (0x00132424U) +#define trim_sys_nvlink0_status_pll_off_f(v) (((v)&0x1U) << 5U) +#define trim_sys_nvlink0_status_pll_off_m() (U32(0x1U) << 5U) +#define trim_sys_nvlink0_status_pll_off_v(r) (((r) >> 5U) & 0x1U) +#define trim_sys_nvl_common_clk_alt_switch_r() (0x001371c4U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_f(v) (((v)&0x3U) << 16U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_m() (U32(0x3U) << 16U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_v(r) (((r) >> 16U) & 0x3U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v() (0x00000003U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f() (0x30000U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v() (0x00000000U) +#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f() (0x0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_f(v) (((v)&0x3U) << 0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_m() (U32(0x3U) << 0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_v(r) (((r) >> 0U) & 0x3U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v() (0x00000000U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f() (0x0U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v() (0x00000002U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f() (0x2U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v() (0x00000003U) +#define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f() (0x3U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_usermode_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_usermode_tu104.h index e59b1ced8..3639523bf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_usermode_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_usermode_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,32 +59,11 @@ #include #include -static inline u32 usermode_cfg0_r(void) -{ - return 0x00810000U; -} -static inline u32 usermode_cfg0_class_id_f(u32 v) -{ - return (v & 0xffffU) << 0U; -} -static inline u32 usermode_cfg0_class_id_value_v(void) -{ - return 0x0000c461U; -} -static inline u32 usermode_time_0_r(void) -{ - return 0x00810080U; -} -static inline u32 usermode_time_0_nsec_f(u32 v) -{ - return (v & 0x7ffffffU) << 5U; -} -static inline u32 usermode_time_1_r(void) -{ - return 0x00810084U; -} -static inline u32 usermode_time_1_nsec_f(u32 v) -{ - return (v & 0x1fffffffU) << 0U; -} +#define usermode_cfg0_r() (0x00810000U) +#define usermode_cfg0_class_id_f(v) (((v)&0xffffU) << 0U) +#define usermode_cfg0_class_id_value_v() (0x0000c461U) +#define usermode_time_0_r() (0x00810080U) +#define usermode_time_0_nsec_f(v) (((v)&0x7ffffffU) << 5U) +#define usermode_time_1_r() (0x00810084U) +#define usermode_time_1_nsec_f(v) (((v)&0x1fffffffU) << 0U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h index afbe2bea3..bfdba2f49 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xp_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,88 +59,27 @@ #include #include -static inline u32 xp_dl_mgr_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 xp_dl_mgr_safe_timing_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 xp_pl_link_config_r(u32 i) -{ - return nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32(i, 4U)); -} -static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) -{ - return (v & 0x1U) << 4U; -} -static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) -{ - return (v & 0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_m(void) -{ - return U32(0xfU) << 0U; -} -static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) -{ - return 0x00000000U; -} -static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) -{ - return (v & 0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_m(void) -{ - return U32(0x3U) << 18U; -} -static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) -{ - return 0x00000003U; -} -static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) -{ - return 0x00000002U; -} -static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) -{ - return 0x00000001U; -} -static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) -{ - return (v & 0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_m(void) -{ - return U32(0x7U) << 20U; -} -static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) -{ - return 0x00000007U; -} -static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) -{ - return 0x00000006U; -} -static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) -{ - return 0x00000005U; -} -static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) -{ - return 0x00000004U; -} -static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) -{ - return 0x00000000U; -} +#define xp_dl_mgr_r(i)\ + (nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32((i), 4U))) +#define xp_dl_mgr_safe_timing_f(v) (((v)&0x1U) << 2U) +#define xp_pl_link_config_r(i)\ + (nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32((i), 4U))) +#define xp_pl_link_config_ltssm_status_f(v) (((v)&0x1U) << 4U) +#define xp_pl_link_config_ltssm_status_idle_v() (0x00000000U) +#define xp_pl_link_config_ltssm_directive_f(v) (((v)&0xfU) << 0U) +#define xp_pl_link_config_ltssm_directive_m() (U32(0xfU) << 0U) +#define xp_pl_link_config_ltssm_directive_normal_operations_v() (0x00000000U) +#define xp_pl_link_config_ltssm_directive_change_speed_v() (0x00000001U) +#define xp_pl_link_config_max_link_rate_f(v) (((v)&0x3U) << 18U) +#define xp_pl_link_config_max_link_rate_m() (U32(0x3U) << 18U) +#define xp_pl_link_config_max_link_rate_2500_mtps_v() (0x00000003U) +#define xp_pl_link_config_max_link_rate_5000_mtps_v() (0x00000002U) +#define xp_pl_link_config_max_link_rate_8000_mtps_v() (0x00000001U) +#define xp_pl_link_config_target_tx_width_f(v) (((v)&0x7U) << 20U) +#define xp_pl_link_config_target_tx_width_m() (U32(0x7U) << 20U) +#define xp_pl_link_config_target_tx_width_x1_v() (0x00000007U) +#define xp_pl_link_config_target_tx_width_x2_v() (0x00000006U) +#define xp_pl_link_config_target_tx_width_x4_v() (0x00000005U) +#define xp_pl_link_config_target_tx_width_x8_v() (0x00000004U) +#define xp_pl_link_config_target_tx_width_x16_v() (0x00000000U) #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h index dfcb087f5..ca58c4de4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_xve_tu104.h @@ -20,7 +20,7 @@ * DEALINGS IN THE SOFTWARE. */ /* - * Function naming determines intended use: + * Function/Macro naming determines intended use: * * _r(void) : Returns the offset for register . * @@ -59,152 +59,41 @@ #include #include -static inline u32 xve_rom_ctrl_r(void) -{ - return 0x00000050U; -} -static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) -{ - return (v & 0x1U) << 0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) -{ - return 0x0U; -} -static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) -{ - return 0x1U; -} -static inline u32 xve_link_control_status_r(void) -{ - return 0x00000088U; -} -static inline u32 xve_link_control_status_link_speed_m(void) -{ - return U32(0xfU) << 16U; -} -static inline u32 xve_link_control_status_link_speed_v(u32 r) -{ - return (r >> 16U) & 0xfU; -} -static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) -{ - return 0x00000003U; -} -static inline u32 xve_link_control_status_link_width_m(void) -{ - return U32(0x3fU) << 20U; -} -static inline u32 xve_link_control_status_link_width_v(u32 r) -{ - return (r >> 20U) & 0x3fU; -} -static inline u32 xve_link_control_status_link_width_x1_v(void) -{ - return 0x00000001U; -} -static inline u32 xve_link_control_status_link_width_x2_v(void) -{ - return 0x00000002U; -} -static inline u32 xve_link_control_status_link_width_x4_v(void) -{ - return 0x00000004U; -} -static inline u32 xve_link_control_status_link_width_x8_v(void) -{ - return 0x00000008U; -} -static inline u32 xve_link_control_status_link_width_x16_v(void) -{ - return 0x00000010U; -} -static inline u32 xve_priv_xv_r(void) -{ - return 0x00000150U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) -{ - return (v & 0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_m(void) -{ - return U32(0x1U) << 7U; -} -static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) -{ - return (r >> 7U) & 0x1U; -} -static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) -{ - return (v & 0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_m(void) -{ - return U32(0x1U) << 8U; -} -static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) -{ - return (r >> 8U) & 0x1U; -} -static inline u32 xve_cya_2_r(void) -{ - return 0x00000704U; -} -static inline u32 xve_reset_r(void) -{ - return 0x00000718U; -} -static inline u32 xve_reset_reset_m(void) -{ - return U32(0x1U) << 0U; -} -static inline u32 xve_reset_gpu_on_sw_reset_m(void) -{ - return U32(0x1U) << 1U; -} -static inline u32 xve_reset_counter_en_m(void) -{ - return U32(0x1U) << 2U; -} -static inline u32 xve_reset_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_m(void) -{ - return U32(0x7ffU) << 4U; -} -static inline u32 xve_reset_counter_val_v(u32 r) -{ - return (r >> 4U) & 0x7ffU; -} -static inline u32 xve_reset_clock_on_sw_reset_m(void) -{ - return U32(0x1U) << 15U; -} -static inline u32 xve_reset_clock_counter_en_m(void) -{ - return U32(0x1U) << 16U; -} -static inline u32 xve_reset_clock_counter_val_f(u32 v) -{ - return (v & 0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_m(void) -{ - return U32(0x7ffU) << 17U; -} -static inline u32 xve_reset_clock_counter_val_v(u32 r) -{ - return (r >> 17U) & 0x7ffU; -} +#define xve_rom_ctrl_r() (0x00000050U) +#define xve_rom_ctrl_rom_shadow_f(v) (((v)&0x1U) << 0U) +#define xve_rom_ctrl_rom_shadow_disabled_f() (0x0U) +#define xve_rom_ctrl_rom_shadow_enabled_f() (0x1U) +#define xve_link_control_status_r() (0x00000088U) +#define xve_link_control_status_link_speed_m() (U32(0xfU) << 16U) +#define xve_link_control_status_link_speed_v(r) (((r) >> 16U) & 0xfU) +#define xve_link_control_status_link_speed_link_speed_2p5_v() (0x00000001U) +#define xve_link_control_status_link_speed_link_speed_5p0_v() (0x00000002U) +#define xve_link_control_status_link_speed_link_speed_8p0_v() (0x00000003U) +#define xve_link_control_status_link_width_m() (U32(0x3fU) << 20U) +#define xve_link_control_status_link_width_v(r) (((r) >> 20U) & 0x3fU) +#define xve_link_control_status_link_width_x1_v() (0x00000001U) +#define xve_link_control_status_link_width_x2_v() (0x00000002U) +#define xve_link_control_status_link_width_x4_v() (0x00000004U) +#define xve_link_control_status_link_width_x8_v() (0x00000008U) +#define xve_link_control_status_link_width_x16_v() (0x00000010U) +#define xve_priv_xv_r() (0x00000150U) +#define xve_priv_xv_cya_l0s_enable_f(v) (((v)&0x1U) << 7U) +#define xve_priv_xv_cya_l0s_enable_m() (U32(0x1U) << 7U) +#define xve_priv_xv_cya_l0s_enable_v(r) (((r) >> 7U) & 0x1U) +#define xve_priv_xv_cya_l1_enable_f(v) (((v)&0x1U) << 8U) +#define xve_priv_xv_cya_l1_enable_m() (U32(0x1U) << 8U) +#define xve_priv_xv_cya_l1_enable_v(r) (((r) >> 8U) & 0x1U) +#define xve_cya_2_r() (0x00000704U) +#define xve_reset_r() (0x00000718U) +#define xve_reset_reset_m() (U32(0x1U) << 0U) +#define xve_reset_gpu_on_sw_reset_m() (U32(0x1U) << 1U) +#define xve_reset_counter_en_m() (U32(0x1U) << 2U) +#define xve_reset_counter_val_f(v) (((v)&0x7ffU) << 4U) +#define xve_reset_counter_val_m() (U32(0x7ffU) << 4U) +#define xve_reset_counter_val_v(r) (((r) >> 4U) & 0x7ffU) +#define xve_reset_clock_on_sw_reset_m() (U32(0x1U) << 15U) +#define xve_reset_clock_counter_en_m() (U32(0x1U) << 16U) +#define xve_reset_clock_counter_val_f(v) (((v)&0x7ffU) << 17U) +#define xve_reset_clock_counter_val_m() (U32(0x7ffU) << 17U) +#define xve_reset_clock_counter_val_v(r) (((r) >> 17U) & 0x7ffU) #endif