gpu: nvgpu: prepare sec2 cmd unit

sec2_ipc.c now has the SEC2 command management functionality. Let us
rename it to sec2_cmd.c. Also update the header includes.

JIRA NVGPU-2074

Change-Id: I884829c6c68344f869c19b09130078ba413dc221
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085751
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -449,7 +449,7 @@ nvgpu-y += \
 	common/init/hal_init.o \
 	common/sec2/sec2.o \
 	common/sec2/sec2_allocator.o \
-	common/sec2/sec2_ipc.o \
+	common/sec2/sec2_cmd.o \
 	common/sec2/sec2_lsfm.o \
 	common/sec2/sec2_msg.o \
 	common/sec2/sec2_queue.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -161,7 +161,7 @@ srcs += common/sim.c \
 	common/acr/acr_sw_tu104.c \
 	common/sec2/sec2.c \
 	common/sec2/sec2_allocator.c \
-	common/sec2/sec2_ipc.c \
+	common/sec2/sec2_cmd.c \
 	common/sec2/sec2_lsfm.c \
 	common/sec2/sec2_msg.c \
 	common/sec2/sec2_queue.c \

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -33,6 +33,7 @@
 #include <nvgpu/acr.h>
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/pmu/lsfm.h>
+#include <nvgpu/sec2/lsfm.h>
 
 #include "gr_falcon_priv.h"
 

drivers/gpu/nvgpu/common/pmu/pmu.c

@@ -36,6 +36,7 @@
 #include <nvgpu/power_features/cg.h>
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/pmu/lsfm.h>
+#include <nvgpu/sec2/lsfm.h>
 #include <nvgpu/pmu/super_surface.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 

drivers/gpu/nvgpu/common/sec2/sec2_cmd.c

@@ -23,13 +23,10 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pmu.h>
 #include <nvgpu/log.h>
-#include <nvgpu/bug.h>
-#include <nvgpu/timers.h>
-#include <nvgpu/lock.h>
 #include <nvgpu/sec2.h>
-#include <nvgpu/engine_queue.h>
 #include <nvgpu/sec2/queue.h>
 #include <nvgpu/sec2if/sec2_if_cmn.h>
+#include <nvgpu/sec2/cmd.h>
 
 /* command post operation functions */
 static bool sec2_validate_cmd(struct nvgpu_sec2 *sec2,
@@ -60,7 +57,7 @@ static bool sec2_validate_cmd(struct nvgpu_sec2 *sec2,
 
 invalid_cmd:
 	nvgpu_err(g, "invalid sec2 cmd :");
-	nvgpu_err(g, "queue_id=%d, cmd_size=%d, cmd_unit_id=%d \n",
+	nvgpu_err(g, "queue_id=%d, cmd_size=%d, cmd_unit_id=%d\n",
 		queue_id, cmd->hdr.size, cmd->hdr.unit_id);
 
 	return false;
@@ -70,8 +67,8 @@ static int sec2_write_cmd(struct nvgpu_sec2 *sec2,
 	struct nv_flcn_cmd_sec2 *cmd, u32 queue_id,
 	u32 timeout_ms)
 {
-	struct gk20a *g = sec2->g;
 	struct nvgpu_timeout timeout;
+	struct gk20a *g = sec2->g;
 	int err;
 
 	nvgpu_log_fn(g, " ");
@@ -81,7 +78,8 @@ static int sec2_write_cmd(struct nvgpu_sec2 *sec2,
 	do {
 		err = nvgpu_sec2_queue_push(sec2->queues, queue_id, &sec2->flcn,
 					    cmd, cmd->hdr.size);
-		if ((err == -EAGAIN) && (nvgpu_timeout_expired(&timeout) == 0)) {
+		if ((err == -EAGAIN) &&
+		    (nvgpu_timeout_expired(&timeout) == 0)) {
 			nvgpu_usleep_range(1000U, 2000U);
 		} else {
 			break;
@@ -105,7 +103,8 @@ int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd,
 
 	if ((cmd == NULL) || (!sec2->sec2_ready)) {
 		if (cmd == NULL) {
-			nvgpu_warn(g, "%s(): SEC2 cmd buffer is NULL", __func__);
+			nvgpu_warn(g,
+				   "%s(): SEC2 cmd buffer is NULL", __func__);
 		} else {
 			nvgpu_warn(g, "%s(): SEC2 is not ready", __func__);
 		}
@@ -143,28 +142,3 @@ int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd,
 exit:
 	return err;
 }
-
-int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
-	void *var, u8 val)
-{
-	struct gk20a *g = sec2->g;
-	struct nvgpu_timeout timeout;
-	u32 delay = POLL_DELAY_MIN_US;
-
-	nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
-
-	do {
-		if (*(u8 *)var == val) {
-			return 0;
-		}
-
-		if (g->ops.sec2.is_interrupted(&g->sec2)) {
-			g->ops.sec2.isr(g);
-		}
-
-		nvgpu_usleep_range(delay, delay * 2U);
-		delay = min_t(u32, delay << 1U, POLL_DELAY_MAX_US);
-	} while (nvgpu_timeout_expired(&timeout) == 0);
-
-	return -ETIMEDOUT;
-}

drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c

@@ -24,7 +24,8 @@
 #include <nvgpu/sec2/lsfm.h>
 #include <nvgpu/sec2/msg.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/sec2.h>
+#include <nvgpu/sec2/cmd.h>
+#include <nvgpu/sec2if/sec2_if_cmn.h>
 
 /* Add code below to handle SEC2 RTOS commands */
 /* LSF's bootstrap command */

drivers/gpu/nvgpu/common/sec2/sec2_msg.c

@@ -199,3 +199,28 @@ int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2)
 exit:
 	return status;
 }
+
+int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
+	void *var, u8 val)
+{
+	struct gk20a *g = sec2->g;
+	struct nvgpu_timeout timeout;
+	u32 delay = POLL_DELAY_MIN_US;
+
+	nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
+
+	do {
+		if (*(u8 *)var == val) {
+			return 0;
+		}
+
+		if (g->ops.sec2.is_interrupted(sec2)) {
+			g->ops.sec2.isr(g);
+		}
+
+		nvgpu_usleep_range(delay, delay * 2U);
+		delay = min_t(u32, delay << 1U, POLL_DELAY_MAX_US);
+	} while (nvgpu_timeout_expired(&timeout) == 0);
+
+	return -ETIMEDOUT;
+}

drivers/gpu/nvgpu/include/nvgpu/sec2.h

@@ -34,8 +34,6 @@
 #include <nvgpu/sec2/seq.h>
 #include <nvgpu/sec2/queue_cmn.h>
 
-#include <nvgpu/sec2if/sec2_cmd_if.h>
-
 #define nvgpu_sec2_dbg(g, fmt, args...) \
 	nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
 
@@ -68,13 +66,6 @@ struct nvgpu_sec2 {
 	u32 command_ack;
 };
 
-/* command/message handling methods*/
-int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd,
-	u32 queue_id, sec2_callback callback,
-	void *cb_param, u32 timeout);
-int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
-	void *var, u8 val);
-
 /* sec2 init */
 int nvgpu_init_sec2_setup_sw(struct gk20a *g, struct nvgpu_sec2 *sec2);
 int nvgpu_init_sec2_support(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/sec2/cmd.h

@@ -24,6 +24,11 @@
 #define NVGPU_SEC2_CMD_IF_H
 
 #include <nvgpu/sec2/lsfm.h>
+#include <nvgpu/flcnif_cmn.h>
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct nvgpu_sec2;
 
 struct nv_flcn_cmd_sec2 {
 	struct pmu_hdr hdr;
@@ -32,9 +37,9 @@ struct nv_flcn_cmd_sec2 {
 	} cmd;
 };
 
-#define  NV_SEC2_UNIT_REWIND          NV_FLCN_UNIT_ID_REWIND
-#define  NV_SEC2_UNIT_INIT            (0x01U)
-#define  NV_SEC2_UNIT_ACR             (0x07U)
-#define  NV_SEC2_UNIT_END             (0x0AU)
+/* command handling methods*/
+int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd,
+	u32 queue_id, sec2_callback callback,
+	void *cb_param, u32 timeout);
 
 #endif /* NVGPU_SEC2_CMD_IF_H */

drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h

@@ -76,5 +76,7 @@ struct nv_flcn_msg_sec2 {
 };
 
 int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2);
+int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
+	void *var, u8 val);
 
 #endif /* NVGPU_SEC2_MSG_H */

drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_cmn.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,6 +30,11 @@
  */
 #define NV_SEC2_MAX_NUM_SEQUENCES	256U
 
+#define  NV_SEC2_UNIT_REWIND          NV_FLCN_UNIT_ID_REWIND
+#define  NV_SEC2_UNIT_INIT            (0x01U)
+#define  NV_SEC2_UNIT_ACR             (0x07U)
+#define  NV_SEC2_UNIT_END             (0x0AU)
+
 /*
  * Compares an unit id against the values in the unit_id enumeration and
  * verifies that the id is valid.  It is expected that the id is specified