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gpu: nvgpu: tu104: init subctx pdb in ramfc setup

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Subctx pdb setup removed from AS_IOCTL_BIND_CHANNEL, is to be done
done during ramfc setup. tu104 hal was missing the subctx pdb
setup. Add it.

Bug 3677982

Change-Id: I48d2ac243691ab54e374d1058cdc6e1118216d8f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2684060
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2022-03-19 16:23:53 +05:30
committed by mobile promotions
parent 5b55088970
commit 8b4bc0e51c
1 changed files with 14 additions and 1 deletions
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15
drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -39,11 +39,24 @@ int tu104_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
struct gk20a *g = ch->g; struct gk20a *g = ch->g;
struct nvgpu_mem *mem = &ch->inst_block; struct nvgpu_mem *mem = &ch->inst_block;
u32 data; u32 data;
bool replayable = false;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
if ((flags & NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE) != 0U) {
replayable = true;
}
#endif
nvgpu_log_info(g, "%llu %u", pbdma_acquire_timeout,
g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
g->ops.ramin.init_subctx_pdb(g, mem, ch->vm->pdb.mem,
replayable, nvgpu_channel_get_max_subctx_count(ch));
nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(), nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
g->ops.pbdma.get_gp_base(gpfifo_base)); g->ops.pbdma.get_gp_base(gpfifo_base));