From 8b57b3b9389a138adb6cf0a8df7a4a06e899ad8c Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 19 Dec 2018 11:26:45 +0530 Subject: [PATCH] gpu: nvgpu: restructure sync cmdbufs specific gpu_ops sync cmbbuf specific ops pointers are moved into a new struct sync_ops under the parent struct gpu_ops. The HAL assignments to the gk20a and gv11b versions are updated to match the new struct type. Jira NVGPU-1308 Change-Id: I1d9832ed5e938cb65747f0f6d34088552f75e2bc Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1975919 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../common/sync/channel_sync_semaphore.c | 6 +-- .../nvgpu/common/sync/channel_sync_syncpt.c | 19 +++---- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 15 +++--- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 17 ++++--- drivers/gpu/nvgpu/gv100/hal_gv100.c | 25 +++++----- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 27 +++++----- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 49 ++++++++++--------- drivers/gpu/nvgpu/os/linux/ioctl_as.c | 4 +- drivers/gpu/nvgpu/tu104/hal_tu104.c | 31 ++++++------ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 7 ++- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 17 ++++--- 11 files changed, 121 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c index 4a2a45b40..8820203a5 100644 --- a/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c +++ b/drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c @@ -81,7 +81,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, nvgpu_semaphore_prepare(s, c->hw_sema); } - g->ops.fifo.add_sema_cmd(g, s, va, cmd, off, acquire, wfi); + g->ops.sync.add_sema_cmd(g, s, va, cmd, off, acquire, wfi); if (acquire) { gpu_sema_verbose_dbg(g, "(A) c=%d ACQ_GE %-4u pool=%-3llu" @@ -151,7 +151,7 @@ static int channel_sync_semaphore_wait_fd( goto cleanup; } - wait_cmd_size = c->g->ops.fifo.get_sema_wait_cmd_size(); + wait_cmd_size = c->g->ops.sync.get_sema_wait_cmd_size(); err = gk20a_channel_alloc_priv_cmdbuf(c, wait_cmd_size * num_fences, entry); if (err != 0) { @@ -192,7 +192,7 @@ static int channel_sync_semaphore_incr_common( return -ENOMEM; } - incr_cmd_size = c->g->ops.fifo.get_sema_incr_cmd_size(); + incr_cmd_size = c->g->ops.sync.get_sema_incr_cmd_size(); err = gk20a_channel_alloc_priv_cmdbuf(c, incr_cmd_size, incr_cmd); if (err != 0) { nvgpu_err(c->g, diff --git a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c index 83f6c006a..93fa547f0 100644 --- a/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c +++ b/drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c @@ -72,7 +72,8 @@ static int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c, } else { if (!preallocated) { err = gk20a_channel_alloc_priv_cmdbuf(c, - c->g->ops.fifo.get_syncpt_wait_cmd_size(), wait_cmd); + c->g->ops.sync.get_syncpt_wait_cmd_size(), + wait_cmd); if (err != 0) { nvgpu_err(c->g, "not enough priv cmd buffer space"); return err; @@ -80,7 +81,7 @@ static int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c, } nvgpu_log(c->g, gpu_dbg_info, "sp->id %d gpu va %llx", id, c->vm->syncpt_ro_map_gpu_va); - c->g->ops.fifo.add_syncpt_wait_cmd(c->g, wait_cmd, + c->g->ops.sync.add_syncpt_wait_cmd(c->g, wait_cmd, pos * wait_cmd_size, id, thresh, c->vm->syncpt_ro_map_gpu_va); } @@ -93,7 +94,7 @@ static int channel_sync_syncpt_wait_raw(struct nvgpu_channel_sync_syncpt *s, { struct channel_gk20a *c = s->c; int err = 0; - u32 wait_cmd_size = c->g->ops.fifo.get_syncpt_wait_cmd_size(); + u32 wait_cmd_size = c->g->ops.sync.get_syncpt_wait_cmd_size(); if (!nvgpu_nvhost_syncpt_is_valid_pt_ext(s->nvhost_dev, id)) { return -EINVAL; @@ -149,7 +150,7 @@ static int channel_sync_syncpt_wait_fd(struct nvgpu_channel_sync *s, int fd, } } - wait_cmd_size = c->g->ops.fifo.get_syncpt_wait_cmd_size(); + wait_cmd_size = c->g->ops.sync.get_syncpt_wait_cmd_size(); err = gk20a_channel_alloc_priv_cmdbuf(c, wait_cmd_size * num_fences, wait_cmd); if (err != 0) { @@ -195,7 +196,7 @@ static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s, struct nvgpu_os_fence os_fence = {0}; err = gk20a_channel_alloc_priv_cmdbuf(c, - c->g->ops.fifo.get_syncpt_incr_cmd_size(wfi_cmd), + c->g->ops.sync.get_syncpt_incr_cmd_size(wfi_cmd), incr_cmd); if (err != 0) { return err; @@ -203,11 +204,11 @@ static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s, nvgpu_log(c->g, gpu_dbg_info, "sp->id %d gpu va %llx", sp->id, sp->syncpt_buf.gpu_va); - c->g->ops.fifo.add_syncpt_incr_cmd(c->g, wfi_cmd, + c->g->ops.sync.add_syncpt_incr_cmd(c->g, wfi_cmd, incr_cmd, sp->id, sp->syncpt_buf.gpu_va); thresh = nvgpu_nvhost_syncpt_incr_max_ext(sp->nvhost_dev, sp->id, - c->g->ops.fifo.get_syncpt_incr_per_release()); + c->g->ops.sync.get_syncpt_incr_per_release()); if (register_irq) { struct channel_gk20a *referenced = gk20a_channel_get(c); @@ -322,7 +323,7 @@ static void channel_sync_syncpt_destroy(struct nvgpu_channel_sync *s) nvgpu_channel_sync_syncpt_from_ops(s); - sp->c->g->ops.fifo.free_syncpt_buf(sp->c, &sp->syncpt_buf); + sp->c->g->ops.sync.free_syncpt_buf(sp->c, &sp->syncpt_buf); nvgpu_nvhost_syncpt_set_min_eq_max_ext(sp->nvhost_dev, sp->id); nvgpu_nvhost_syncpt_put_ref_ext(sp->nvhost_dev, sp->id); @@ -390,7 +391,7 @@ nvgpu_channel_sync_syncpt_create(struct channel_gk20a *c, bool user_managed) return NULL; } - sp->c->g->ops.fifo.alloc_syncpt_buf(sp->c, sp->id, + sp->c->g->ops.sync.alloc_syncpt_buf(sp->c, sp->id, &sp->syncpt_buf); nvgpu_nvhost_syncpt_set_min_eq_max_ext(sp->nvhost_dev, sp->id); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 3465d0cf6..d46db5152 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -529,6 +529,14 @@ static const struct gpu_ops gm20b_ops = { .channel_resume = gk20a_channel_resume, .set_error_notifier = nvgpu_set_error_notifier, .setup_sw = gk20a_init_fifo_setup_sw, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, + .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, + .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, + .init_ce_engine_info = gm20b_fifo_init_ce_engine_info, + .read_pbdma_data = gk20a_fifo_read_pbdma_data, + .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, + }, + .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, @@ -543,12 +551,6 @@ static const struct gpu_ops gm20b_ops = { .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, - .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, - .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, - .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, - .init_ce_engine_info = gm20b_fifo_init_ce_engine_info, - .read_pbdma_data = gk20a_fifo_read_pbdma_data, - .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, .runlist = { .update_runlist = gk20a_fifo_update_runlist, @@ -786,6 +788,7 @@ int gm20b_init_hal(struct gk20a *g) gops->clock_gating = gm20b_ops.clock_gating; gops->fifo = gm20b_ops.fifo; gops->runlist = gm20b_ops.runlist; + gops->sync = gm20b_ops.sync; gops->netlist = gm20b_ops.netlist; gops->mm = gm20b_ops.mm; gops->therm = gm20b_ops.therm; diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 08cdfd6e3..d7f5921c6 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -578,6 +578,15 @@ static const struct gpu_ops gp10b_ops = { .channel_resume = gk20a_channel_resume, .set_error_notifier = nvgpu_set_error_notifier, .setup_sw = gk20a_init_fifo_setup_sw, + .resetup_ramfc = gp10b_fifo_resetup_ramfc, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, + .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, + .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, + .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, + .read_pbdma_data = gk20a_fifo_read_pbdma_data, + .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, + }, + .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, @@ -589,16 +598,9 @@ static const struct gpu_ops gp10b_ops = { .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, .get_sync_ro_map = NULL, #endif - .resetup_ramfc = gp10b_fifo_resetup_ramfc, .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, - .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, - .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, - .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, - .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, - .read_pbdma_data = gk20a_fifo_read_pbdma_data, - .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, .runlist = { .reschedule_runlist = gk20a_fifo_reschedule_runlist, @@ -867,6 +869,7 @@ int gp10b_init_hal(struct gk20a *g) gops->clock_gating = gp10b_ops.clock_gating; gops->fifo = gp10b_ops.fifo; gops->runlist = gp10b_ops.runlist; + gops->sync = gp10b_ops.sync; gops->netlist = gp10b_ops.netlist; #ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = gp10b_ops.fecs_trace; diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 33c2cbefd..d4a67b690 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -751,6 +751,19 @@ static const struct gpu_ops gv100_ops = { .channel_resume = gk20a_channel_resume, .set_error_notifier = nvgpu_set_error_notifier_if_empty, .setup_sw = gk20a_init_fifo_setup_sw, + .resetup_ramfc = NULL, + .free_channel_ctx_header = gv11b_free_subctx_header, + .ring_channel_doorbell = gv11b_ring_channel_doorbell, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, + .usermode_base = gv11b_fifo_usermode_base, + .doorbell_token = gv11b_fifo_doorbell_token, + .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, + .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, + .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, + .read_pbdma_data = gk20a_fifo_read_pbdma_data, + .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, + }, + .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, @@ -762,20 +775,9 @@ static const struct gpu_ops gv100_ops = { gv11b_fifo_get_syncpt_incr_per_release, .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, #endif - .resetup_ramfc = NULL, - .free_channel_ctx_header = gv11b_free_subctx_header, - .ring_channel_doorbell = gv11b_ring_channel_doorbell, .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gv11b_fifo_add_sema_cmd, - .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, - .usermode_base = gv11b_fifo_usermode_base, - .doorbell_token = gv11b_fifo_doorbell_token, - .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, - .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, - .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, - .read_pbdma_data = gk20a_fifo_read_pbdma_data, - .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, .runlist = { .update_runlist = gk20a_fifo_update_runlist, @@ -1130,6 +1132,7 @@ int gv100_init_hal(struct gk20a *g) gops->clock_gating = gv100_ops.clock_gating; gops->fifo = gv100_ops.fifo; gops->runlist = gv100_ops.runlist; + gops->sync = gv100_ops.sync; gops->netlist = gv100_ops.netlist; gops->mm = gv100_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 630fce104..d58ca7338 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -703,6 +703,20 @@ static const struct gpu_ops gv11b_ops = { .channel_resume = gk20a_channel_resume, .set_error_notifier = nvgpu_set_error_notifier_if_empty, .setup_sw = gk20a_init_fifo_setup_sw, + .resetup_ramfc = NULL, + .free_channel_ctx_header = gv11b_free_subctx_header, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + .ring_channel_doorbell = gv11b_ring_channel_doorbell, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, + .usermode_base = gv11b_fifo_usermode_base, + .doorbell_token = gv11b_fifo_doorbell_token, + .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, + .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, + .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, + .read_pbdma_data = gk20a_fifo_read_pbdma_data, + .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, + }, + .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, @@ -714,21 +728,9 @@ static const struct gpu_ops gv11b_ops = { gv11b_fifo_get_syncpt_incr_per_release, .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, #endif - .resetup_ramfc = NULL, - .free_channel_ctx_header = gv11b_free_subctx_header, - .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, - .ring_channel_doorbell = gv11b_ring_channel_doorbell, .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gv11b_fifo_add_sema_cmd, - .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, - .usermode_base = gv11b_fifo_usermode_base, - .doorbell_token = gv11b_fifo_doorbell_token, - .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, - .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, - .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, - .read_pbdma_data = gk20a_fifo_read_pbdma_data, - .reset_pbdma_header = gk20a_fifo_reset_pbdma_header, }, .runlist = { .reschedule_runlist = gv11b_fifo_reschedule_runlist, @@ -1004,6 +1006,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->runlist = gv11b_ops.runlist; + gops->sync = gv11b_ops.sync; gops->netlist = gv11b_ops.netlist; gops->mm = gv11b_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 0a5b6a11c..b44173f2e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -827,32 +827,9 @@ struct gpu_ops { int (*channel_suspend)(struct gk20a *g); int (*channel_resume)(struct gk20a *g); void (*set_error_notifier)(struct channel_gk20a *ch, u32 error); -#ifdef CONFIG_TEGRA_GK20A_NVHOST - int (*alloc_syncpt_buf)(struct channel_gk20a *c, - u32 syncpt_id, struct nvgpu_mem *syncpt_buf); - void (*free_syncpt_buf)(struct channel_gk20a *c, - struct nvgpu_mem *syncpt_buf); - void (*add_syncpt_wait_cmd)(struct gk20a *g, - struct priv_cmd_entry *cmd, u32 off, - u32 id, u32 thresh, u64 gpu_va); - u32 (*get_syncpt_wait_cmd_size)(void); - void (*add_syncpt_incr_cmd)(struct gk20a *g, - bool wfi_cmd, struct priv_cmd_entry *cmd, - u32 id, u64 gpu_va); - u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd); - int (*get_sync_ro_map)(struct vm_gk20a *vm, - u64 *base_gpuva, u32 *sync_size); - u32 (*get_syncpt_incr_per_release)(void); -#endif void (*ring_channel_doorbell)(struct channel_gk20a *c); u64 (*usermode_base)(struct gk20a *g); u32 (*doorbell_token)(struct channel_gk20a *c); - u32 (*get_sema_wait_cmd_size)(void); - u32 (*get_sema_incr_cmd_size)(void); - void (*add_sema_cmd)(struct gk20a *g, - struct nvgpu_semaphore *s, u64 sema_va, - struct priv_cmd_entry *cmd, - u32 off, bool acquire, bool wfi); int (*init_pdb_cache_war)(struct gk20a *g); void (*deinit_pdb_cache_war)(struct gk20a *g); int (*set_sm_exception_type_mask)(struct channel_gk20a *ch, @@ -892,6 +869,32 @@ struct gpu_ops { void (*runlist_write_state)(struct gk20a *g, u32 runlists_mask, u32 runlist_state); } runlist; + + struct { +#ifdef CONFIG_TEGRA_GK20A_NVHOST + int (*alloc_syncpt_buf)(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf); + void (*free_syncpt_buf)(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf); + void (*add_syncpt_wait_cmd)(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va); + u32 (*get_syncpt_wait_cmd_size)(void); + void (*add_syncpt_incr_cmd)(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va); + u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd); + int (*get_sync_ro_map)(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size); + u32 (*get_syncpt_incr_per_release)(void); +#endif + u32 (*get_sema_wait_cmd_size)(void); + u32 (*get_sema_incr_cmd_size)(void); + void (*add_sema_cmd)(struct gk20a *g, + struct nvgpu_semaphore *s, u64 sema_va, + struct priv_cmd_entry *cmd, + u32 off, bool acquire, bool wfi); + } sync; struct pmu_v { u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu, diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_as.c b/drivers/gpu/nvgpu/os/linux/ioctl_as.c index 34f2de6d8..c3ad895e9 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_as.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_as.c @@ -279,13 +279,13 @@ static int nvgpu_as_ioctl_get_sync_ro_map( u32 sync_size; int err = 0; - if (!g->ops.fifo.get_sync_ro_map) + if (g->ops.sync.get_sync_ro_map == NULL) return -EINVAL; if (!nvgpu_has_syncpoints(g)) return -EINVAL; - err = g->ops.fifo.get_sync_ro_map(vm, &base_gpuva, &sync_size); + err = g->ops.sync.get_sync_ro_map(vm, &base_gpuva, &sync_size); if (err) return err; diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index e8f0ee07b..6125c6018 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -778,6 +778,22 @@ static const struct gpu_ops tu104_ops = { .channel_resume = gk20a_channel_resume, .set_error_notifier = nvgpu_set_error_notifier_if_empty, .setup_sw = gk20a_init_fifo_setup_sw, + .resetup_ramfc = NULL, + .free_channel_ctx_header = gv11b_free_subctx_header, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + .ring_channel_doorbell = tu104_ring_channel_doorbell, + .usermode_base = tu104_fifo_usermode_base, + .doorbell_token = tu104_fifo_doorbell_token, + .init_pdb_cache_war = tu104_init_pdb_cache_war, + .deinit_pdb_cache_war = tu104_deinit_pdb_cache_war, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, + .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, + .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, + .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, + .read_pbdma_data = tu104_fifo_read_pbdma_data, + .reset_pbdma_header = tu104_fifo_reset_pbdma_header, + }, + .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, @@ -789,23 +805,9 @@ static const struct gpu_ops tu104_ops = { gv11b_fifo_get_syncpt_incr_per_release, .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, #endif - .resetup_ramfc = NULL, - .free_channel_ctx_header = gv11b_free_subctx_header, - .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, - .ring_channel_doorbell = tu104_ring_channel_doorbell, .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gv11b_fifo_add_sema_cmd, - .usermode_base = tu104_fifo_usermode_base, - .doorbell_token = tu104_fifo_doorbell_token, - .init_pdb_cache_war = tu104_init_pdb_cache_war, - .deinit_pdb_cache_war = tu104_deinit_pdb_cache_war, - .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, - .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, - .find_pbdma_for_runlist = gk20a_fifo_find_pbdma_for_runlist, - .init_ce_engine_info = gp10b_fifo_init_ce_engine_info, - .read_pbdma_data = tu104_fifo_read_pbdma_data, - .reset_pbdma_header = tu104_fifo_reset_pbdma_header, }, .runlist = { .update_runlist = gk20a_fifo_update_runlist, @@ -1163,6 +1165,7 @@ int tu104_init_hal(struct gk20a *g) gops->clock_gating = tu104_ops.clock_gating; gops->fifo = tu104_ops.fifo; gops->runlist = tu104_ops.runlist; + gops->sync = tu104_ops.sync; gops->netlist = tu104_ops.netlist; gops->mm = tu104_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 7f3940cd1..f45300e01 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -404,6 +404,10 @@ static const struct gpu_ops vgpu_gp10b_ops = { .channel_resume = gk20a_channel_resume, .set_error_notifier = nvgpu_set_error_notifier, .setup_sw = gk20a_init_fifo_setup_sw, + .resetup_ramfc = NULL, + .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, + }, + .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, @@ -415,11 +419,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, .get_sync_ro_map = NULL, #endif - .resetup_ramfc = NULL, .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, - .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, }, .runlist = { .reschedule_runlist = NULL, @@ -659,6 +661,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->clock_gating = vgpu_gp10b_ops.clock_gating; gops->fifo = vgpu_gp10b_ops.fifo; gops->runlist = vgpu_gp10b_ops.runlist; + gops->sync = vgpu_gp10b_ops.sync; gops->netlist = vgpu_gp10b_ops.netlist; #ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = vgpu_gp10b_ops.fecs_trace; diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index b76af42ae..294424d20 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -477,6 +477,15 @@ static const struct gpu_ops vgpu_gv11b_ops = { .channel_resume = gk20a_channel_resume, .set_error_notifier = nvgpu_set_error_notifier, .setup_sw = gk20a_init_fifo_setup_sw, + .resetup_ramfc = NULL, + .free_channel_ctx_header = vgpu_gv11b_free_subctx_header, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + .ring_channel_doorbell = gv11b_ring_channel_doorbell, + .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, + .usermode_base = gv11b_fifo_usermode_base, + .doorbell_token = gv11b_fifo_doorbell_token, + }, + .sync = { #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, .free_syncpt_buf = vgpu_gv11b_fifo_free_syncpt_buf, @@ -488,16 +497,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, .get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map, #endif - .resetup_ramfc = NULL, - .free_channel_ctx_header = vgpu_gv11b_free_subctx_header, - .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, - .ring_channel_doorbell = gv11b_ring_channel_doorbell, .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gv11b_fifo_add_sema_cmd, - .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, - .usermode_base = gv11b_fifo_usermode_base, - .doorbell_token = gv11b_fifo_doorbell_token, }, .runlist = { .reschedule_runlist = NULL, @@ -736,6 +738,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g) gops->clock_gating = vgpu_gv11b_ops.clock_gating; gops->fifo = vgpu_gv11b_ops.fifo; gops->runlist = vgpu_gv11b_ops.runlist; + gops->sync = vgpu_gv11b_ops.sync; gops->netlist = vgpu_gv11b_ops.netlist; gops->mm = vgpu_gv11b_ops.mm; #ifdef CONFIG_GK20A_CTXSW_TRACE