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gpu: nvgpu: remove whitelisting for wrongly reported violations by tool

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- Earlier we whitelisted wrongly reported static analysis violations
  by tool, raised coverity tool bugs for these cases.

- These bugs are fixed with new version of tool, so no need fo whitelisting.

JIRA NVGPU-7119

Change-Id: I8a456accaef6911be7ba5e21e4b28dc89f51069f
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2604366
(cherry picked from commit be968f2fe93ac01319cecf588cebd726c88aa6af)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2677522
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
srajum
2021-10-02 17:59:08 +05:30
committed by mobile promotions
parent 07583dffed
commit 8be6ab837a
3 changed files with 9 additions and 74 deletions
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7
drivers/gpu/nvgpu/include/nvgpu/bug.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -49,11 +49,7 @@
*/
#define nvgpu_assert(cond) \
({ \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532") \
BUG_ON((cond) == ((bool)(0 != 0))); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6)) \
})
#endif
@@ -64,7 +60,6 @@
* Invokes the macro #nvgpu_assert with parameter as #true.
*/
#define nvgpu_do_assert() \
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 10_3), "Bug 2623654") \
nvgpu_assert((bool)(0 != 0))
/*

67
drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h
View File

@@ -69,13 +69,7 @@ typedef struct nvgpu_posix_atomic64 {
* @param i Value to set in atomic variable.
*/
#define NVGPU_POSIX_ATOMIC_SET(v, i) \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(EXP37_C), "Bug 200584380") \
atomic_store(&((v)->v), (i)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(EXP37_C))
atomic_store(&((v)->v), (i))
/**
* @brief Define for atomic read.
@@ -83,13 +77,7 @@ typedef struct nvgpu_posix_atomic64 {
* @param v Atomic variable to be read.
*/
#define NVGPU_POSIX_ATOMIC_READ(v) \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(EXP37_C), "Bug 200584380") \
atomic_load(&((v)->v)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(EXP37_C))
atomic_load(&((v)->v))
/**
* @brief Define for atomic add and return.
@@ -103,18 +91,9 @@ typedef struct nvgpu_posix_atomic64 {
({ \
typeof(i) tmp; \
\
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(INT31_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(EXP37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \
NVGPU_MISRA(Rule, 10_3), "TID 374") \
tmp = (typeof(i))atomic_fetch_add(&((v)->v), (i)); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(INT31_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(EXP37_C)) \
tmp = (typeof((v)->v))atomic_fetch_add(&((v)->v), (i)); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3)) \
tmp = __builtin_choose_expr( \
IS_SIGNED_LONG_TYPE(i), \
@@ -135,18 +114,9 @@ typedef struct nvgpu_posix_atomic64 {
({ \
typeof(i) tmp; \
\
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(INT31_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(EXP37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \
NVGPU_MISRA(Rule, 10_3), "TID 374") \
tmp = (typeof(i))atomic_fetch_sub(&((v)->v), (i)); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(INT31_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(EXP37_C)) \
tmp = (typeof((v)->v))atomic_fetch_sub(&((v)->v), (i)); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3)) \
tmp = __builtin_choose_expr( \
IS_SIGNED_LONG_TYPE(i), \
@@ -170,19 +140,10 @@ typedef struct nvgpu_posix_atomic64 {
({ \
typeof(old) tmp = (old); \
\
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(EXP37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_MISRA(Rule, 17_7), "Bug 2793032") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \
NVGPU_MISRA(Rule, 10_3), "TID 374") \
(void) atomic_compare_exchange_strong(&((v)->v), \
&tmp, (new)); \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(EXP37_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 17_7)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3)) \
tmp; \
})
@@ -196,13 +157,7 @@ typedef struct nvgpu_posix_atomic64 {
* @return Original value in the atomic variable.
*/
#define NVGPU_POSIX_ATOMIC_XCHG(v, new) \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380") \
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(EXP37_C), "Bug 200584380") \
atomic_exchange(&((v)->v), (new)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C)) \
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(EXP37_C))
atomic_exchange(&((v)->v), (new))
/**
* @brief POSIX implementation of atomic set.
@@ -439,15 +394,9 @@ static inline int nvgpu_atomic_add_unless_impl(nvgpu_atomic_t *v, int a, int u)
if (old == (u)) {
break;
}
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_MISRA(Rule, 17_7), "Bug 2793032")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \
NVGPU_MISRA(Rule, 10_3), "TID 374")
} while (!atomic_compare_exchange_strong(&((v)->v), &old, old + (a)));
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 17_7))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
return old;
@@ -529,15 +478,9 @@ static inline long nvgpu_atomic64_add_unless_impl(nvgpu_atomic64_t *v, long a,
if (old == (u)) {
break;
}
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_CERT(DCL37_C), "Bug 200584380")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, \
NVGPU_MISRA(Rule, 17_7), "Bug 2793032")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, \
NVGPU_MISRA(Rule, 10_3), "TID 374")
} while (!atomic_compare_exchange_strong(&((v)->v), &old, old + (a)));
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_CERT(DCL37_C))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 17_7))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
return old;

3
drivers/gpu/nvgpu/include/nvgpu/static_analysis.h
View File

@@ -114,7 +114,6 @@ static inline s32 nvgpu_safe_add_s32(s32 si_a, s32 si_b)
*/
static inline u64 nvgpu_safe_add_u64(u64 ul_a, u64 ul_b)
{
NVGPU_COV_WHITELIST(false_positive, NVGPU_CERT(INT30_C), "Bug 2643092")
if ((ULONG_MAX - ul_a) < ul_b) {
BUG();
return 0U;
@@ -604,7 +603,6 @@ static inline u32 nvgpu_safe_cast_bool_to_u32(bool bl_a)
*/
static inline u8 nvgpu_safe_cast_s8_to_u8(s8 sc_a)
{
NVGPU_COV_WHITELIST(false_positive, NVGPU_CERT(STR34_C), "Bug 2673832")
if (sc_a < 0) {
BUG();
return 0U;
@@ -770,7 +768,6 @@ static inline s32 nvgpu_safe_cast_u64_to_s32(u64 ul_a)
*/
static inline s64 nvgpu_safe_cast_u64_to_s64(u64 ul_a)
{
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_3), "Bug 2615925")
if (ul_a > nvgpu_safe_cast_s64_to_u64(LONG_MAX)) {
BUG();
return 0;