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gpu: nvgpu: skip classes in obj_alloc

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Currently, we are performing obj ctx alloction for bellow classes

 1. VOLTA_COMPUTE_A
 2. VOLTA_DMA_COPY_A
 3. VOLTA_CHANNEL_GPFIFO_A

In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.

Jira NVGPU-4378

Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
sagar
2020-01-30 13:06:21 +05:30
committed by Alex Waterman
parent 052bcfb2d2
commit 8c04d2f000
13 changed files with 70 additions and 83 deletions
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31
drivers/gpu/nvgpu/hal/class/class_gm20b.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -41,3 +41,32 @@ bool gm20b_class_is_valid_compute(u32 class_num)
return false;
}
}
bool gm20b_class_is_valid(u32 class_num)
{
bool valid;
switch (class_num) {
case KEPLER_DMA_COPY_A:
case KEPLER_INLINE_TO_MEMORY_B:
case MAXWELL_DMA_COPY_A:
case MAXWELL_CHANNEL_GPFIFO_A:
valid = true;
break;
case MAXWELL_COMPUTE_B:
valid = true;
break;
#ifdef CONFIG_NVGPU_GRAPHICS
case MAXWELL_B:
case FERMI_TWOD_A:
valid = true;
break;
#endif
default:
valid = false;
break;
}
return valid;
}