nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 17:36:20 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: skip classes in obj_alloc

Browse Source 
Currently, we are performing obj ctx alloction for bellow classes

 1. VOLTA_COMPUTE_A
 2. VOLTA_DMA_COPY_A
 3. VOLTA_CHANNEL_GPFIFO_A

In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.

Jira NVGPU-4378

Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
sagar
2020-01-30 13:06:21 +05:30
committed by Alex Waterman
parent 052bcfb2d2
commit 8c04d2f000
13 changed files with 70 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
userspace/units/class/nvgpu-class.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -59,12 +59,6 @@ u32 valid_classes[] = {
0xC3C0U, /* VOLTA_COMPUTE_A */
0xC3B5U, /* VOLTA_DMA_COPY_A */
0xC36FU, /* VOLTA_CHANNEL_GPFIFO_A */
0xC0B5U, /* PASCAL_DMA_COPY_A */
0xC06FU, /* PASCAL_CHANNEL_GPFIFO_A */
0xB06FU, /* MAXWELL_CHANNEL_GPFIFO_A */
0xB0B5U, /* MAXWELL_DMA_COPY_A */
0xA140U, /* KEPLER_INLINE_TO_MEMORY_B */
0xA0B5U, /* KEPLER_DMA_COPY_A */
};
u32 invalid_classes[] = {
@@ -75,6 +69,12 @@ u32 invalid_classes[] = {
0xB1C0U, /* MAXWELL_COMPUTE_B */
0xB197U, /* MAXWELL_B */
0x902DU, /* FERMI_TWOD_A */
0xC0B5U, /* PASCAL_DMA_COPY_A */
0xC06FU, /* PASCAL_CHANNEL_GPFIFO_A */
0xB06FU, /* MAXWELL_CHANNEL_GPFIFO_A */
0xB0B5U, /* MAXWELL_DMA_COPY_A */
0xA140U, /* KEPLER_INLINE_TO_MEMORY_B */
0xA0B5U, /* KEPLER_DMA_COPY_A */
0x76543210U, /* random value */
0x0000U, /* random value */
0xC000U, /* random value */

6
userspace/units/gr/setup/nvgpu-gr-setup.c
View File

@@ -660,6 +660,12 @@ int test_gr_setup_alloc_obj_ctx(struct unit_module *m,
unit_return_fail(m, "setup channel allocation failed\n");
}
/* DMA_COPY should pass, but it own't allocate obj ctx */
err = g->ops.gr.setup.alloc_obj_ctx(gr_setup_ch, VOLTA_DMA_COPY_A, 0);
if (err != 0) {
unit_return_fail(m, "setup alloc obj_ctx failed\n");
}
err = g->ops.gr.setup.alloc_obj_ctx(gr_setup_ch, VOLTA_COMPUTE_A, 0);
if (err != 0) {
unit_return_fail(m, "setup alloc obj_ctx failed\n");