gpu: nvgpu: skip classes in obj_alloc

Currently, we are performing obj ctx alloction for bellow classes

 1. VOLTA_COMPUTE_A
 2. VOLTA_DMA_COPY_A
 3. VOLTA_CHANNEL_GPFIFO_A

In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.

Jira NVGPU-4378

Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

arch/nvgpu-hal-new.yaml

@@ -738,9 +738,7 @@ pramin:
 class_fusa:
   safe: yes
   owner: Seshendra G
-  sources: [ hal/class/class_gm20b_fusa.c,
+  sources: [ hal/class/class_gm20b.h,
-             hal/class/class_gm20b.h,
-             hal/class/class_gp10b_fusa.c,
              hal/class/class_gp10b.h,
              hal/class/class_gv11b_fusa.c,
              hal/class/class_gv11b.h ]
@@ -749,6 +747,7 @@ class:
   safe: no
   owner: Seshendra G
   sources: [ hal/class/class_gm20b.c,
+             hal/class/class_gp10b.c,
              hal/class/class_tu104.c,
              hal/class/class_tu104.h ]
 

drivers/gpu/nvgpu/Makefile

@@ -195,6 +195,7 @@ nvgpu-y += \
 	hal/bus/bus_gv100.o \
 	hal/bus/bus_tu104.o \
 	hal/class/class_gm20b.o \
+	hal/class/class_gp10b.o \
 	hal/class/class_tu104.o \
 	hal/clk/clk_gm20b.o \
 	hal/clk/clk_tu104.o \
@@ -577,8 +578,6 @@ nvgpu-y += \
 	hal/bus/bus_gv11b_fusa.o \
 	hal/ce/ce_gp10b_fusa.o \
 	hal/ce/ce_gv11b_fusa.o \
-	hal/class/class_gm20b_fusa.o \
-	hal/class/class_gp10b_fusa.o \
 	hal/class/class_gv11b_fusa.o \
 	hal/falcon/falcon_gk20a_fusa.o \
 	hal/fb/fb_gm20b_fusa.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -169,8 +169,6 @@ srcs += hal/mm/mm_gv11b_fusa.c \
 	hal/bus/bus_gv11b_fusa.c \
 	hal/ce/ce_gp10b_fusa.c \
 	hal/ce/ce_gv11b_fusa.c \
-	hal/class/class_gm20b_fusa.c \
-	hal/class/class_gp10b_fusa.c \
 	hal/class/class_gv11b_fusa.c \
 	hal/falcon/falcon_gk20a_fusa.c \
 	hal/fb/fb_gm20b_fusa.c \
@@ -256,6 +254,7 @@ srcs += hal/init/hal_gp10b.c \
 	hal/mc/mc_gm20b.c  \
 	hal/bus/bus_gk20a.c \
 	hal/class/class_gm20b.c \
+	hal/class/class_gp10b.c \
 	hal/clk/clk_gm20b.c \
 	hal/falcon/falcon_gk20a.c \
 	hal/gr/config/gr_config_gm20b.c \

drivers/gpu/nvgpu/common/gr/gr_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -154,6 +154,17 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num,
 
 	c->obj_class = class_num;
 
+#ifndef CONFIG_NVGPU_HAL_NON_FUSA
+	/*
+	 * Only compute class is valid in safety build, Return success for valid
+	 * non compute classees. Invalid classes are indentified by above check
+	 * with nvgpu_gr_setup_validate_channel_and_class() function.
+	 */
+	if (!g->ops.gpu_class.is_valid_compute(class_num)) {
+		return 0;
+	}
+#endif
+
 	tsg = nvgpu_tsg_from_ch(c);
 	if (tsg == NULL) {
 		return -EINVAL;

drivers/gpu/nvgpu/hal/class/class_gm20b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -41,3 +41,32 @@ bool gm20b_class_is_valid_compute(u32 class_num)
 		return false;
 	}
 }
+
+bool gm20b_class_is_valid(u32 class_num)
+{
+	bool valid;
+
+	switch (class_num) {
+	case KEPLER_DMA_COPY_A:
+	case KEPLER_INLINE_TO_MEMORY_B:
+	case MAXWELL_DMA_COPY_A:
+	case MAXWELL_CHANNEL_GPFIFO_A:
+		valid = true;
+		break;
+
+	case MAXWELL_COMPUTE_B:
+		valid = true;
+		break;
+#ifdef CONFIG_NVGPU_GRAPHICS
+	case MAXWELL_B:
+	case FERMI_TWOD_A:
+		valid = true;
+		break;
+#endif
+	default:
+		valid = false;
+		break;
+	}
+
+	return valid;
+}

drivers/gpu/nvgpu/hal/class/class_gm20b.h

@@ -26,10 +26,7 @@
 #include <nvgpu/types.h>
 
 bool gm20b_class_is_valid(u32 class_num);
-
-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 bool gm20b_class_is_valid_gfx(u32 class_num);
 bool gm20b_class_is_valid_compute(u32 class_num);
-#endif
 
 #endif /* NVGPU_CLASS_GM20B */

drivers/gpu/nvgpu/hal/class/class_gm20b_fusa.c

@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2019 NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/class.h>
-
-#include "class_gm20b.h"
-
-bool gm20b_class_is_valid(u32 class_num)
-{
-	bool valid;
-
-	switch (class_num) {
-	case KEPLER_DMA_COPY_A:
-	case KEPLER_INLINE_TO_MEMORY_B:
-	case MAXWELL_DMA_COPY_A:
-	case MAXWELL_CHANNEL_GPFIFO_A:
-		valid = true;
-		break;
-
-#ifdef CONFIG_NVGPU_NON_FUSA
-	case MAXWELL_COMPUTE_B:
-		valid = true;
-		break;
-#endif
-#ifdef CONFIG_NVGPU_GRAPHICS
-	case MAXWELL_B:
-	case FERMI_TWOD_A:
-		valid = true;
-		break;
-#endif
-	default:
-		valid = false;
-		break;
-	}
-
-	return valid;
-}

drivers/gpu/nvgpu/hal/class/class_gp10b.c

@@ -41,11 +41,9 @@ bool gp10b_class_is_valid(u32 class_num)
 		valid = true;
 		break;
 #endif
-#ifdef CONFIG_NVGPU_NON_FUSA
 	case PASCAL_COMPUTE_A:
 		valid = true;
 		break;
-#endif
 	default:
 		valid = gm20b_class_is_valid(class_num);
 		break;
@@ -64,7 +62,6 @@ bool gp10b_class_is_valid_gfx(u32 class_num)
 }
 #endif
 
-#ifdef CONFIG_NVGPU_NON_FUSA
 bool gp10b_class_is_valid_compute(u32 class_num)
 {
 	if (class_num == PASCAL_COMPUTE_A ||  class_num == MAXWELL_COMPUTE_B) {
@@ -73,4 +70,3 @@ bool gp10b_class_is_valid_compute(u32 class_num)
 		return false;
 	}
 }
-#endif

drivers/gpu/nvgpu/hal/class/class_gp10b.h

@@ -26,9 +26,7 @@
 #include <nvgpu/types.h>
 
 bool gp10b_class_is_valid(u32 class_num);
-#ifdef CONFIG_NVGPU_NON_FUSA
 bool gp10b_class_is_valid_compute(u32 class_num);
-#endif
 
 #ifdef CONFIG_NVGPU_GRAPHICS
 bool gp10b_class_is_valid_gfx(u32 class_num);

drivers/gpu/nvgpu/hal/class/class_gv11b_fusa.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,9 @@
 #include <nvgpu/class.h>
 #include <nvgpu/barrier.h>
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 #include "class_gp10b.h"
+#endif
 #include "class_gv11b.h"
 
 bool gv11b_class_is_valid(u32 class_num)
@@ -44,7 +46,11 @@ bool gv11b_class_is_valid(u32 class_num)
 		break;
 #endif
 	default:
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 		valid = gp10b_class_is_valid(class_num);
+#else
+		valid = false;
+#endif
 		break;
 	}
 	return valid;

drivers/gpu/nvgpu/include/nvgpu/gr/setup.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -64,6 +64,9 @@ struct nvgpu_gr_ctx;
  * - Mapping global context buffers into context image.
  * - Committing the context image into channel instance block.
  *
+ * Note that if requested class is a valid class but not a COMPUTE class, this
+ * function will return 0.
+ *
  * @return 0 in case of success, < 0 in case of failure.
  * @retval -ENOMEM if memory allocation fails for any context image.
  * @retval -EINVAL if invalid GPU class ID is provided.

userspace/units/class/nvgpu-class.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -59,12 +59,6 @@ u32 valid_classes[] = {
 	0xC3C0U, /* VOLTA_COMPUTE_A */
 	0xC3B5U, /* VOLTA_DMA_COPY_A */
 	0xC36FU, /* VOLTA_CHANNEL_GPFIFO_A */
-	0xC0B5U, /* PASCAL_DMA_COPY_A */
-	0xC06FU, /* PASCAL_CHANNEL_GPFIFO_A */
-	0xB06FU, /* MAXWELL_CHANNEL_GPFIFO_A */
-	0xB0B5U, /* MAXWELL_DMA_COPY_A */
-	0xA140U, /* KEPLER_INLINE_TO_MEMORY_B */
-	0xA0B5U, /* KEPLER_DMA_COPY_A */
 };
 
 u32 invalid_classes[] = {
@@ -75,6 +69,12 @@ u32 invalid_classes[] = {
 	0xB1C0U, /* MAXWELL_COMPUTE_B */
 	0xB197U, /* MAXWELL_B */
 	0x902DU, /* FERMI_TWOD_A */
+	0xC0B5U, /* PASCAL_DMA_COPY_A */
+	0xC06FU, /* PASCAL_CHANNEL_GPFIFO_A */
+	0xB06FU, /* MAXWELL_CHANNEL_GPFIFO_A */
+	0xB0B5U, /* MAXWELL_DMA_COPY_A */
+	0xA140U, /* KEPLER_INLINE_TO_MEMORY_B */
+	0xA0B5U, /* KEPLER_DMA_COPY_A */
 	0x76543210U, /* random value */
 	0x0000U, /* random value */
 	0xC000U, /* random value */

userspace/units/gr/setup/nvgpu-gr-setup.c

@@ -660,6 +660,12 @@ int test_gr_setup_alloc_obj_ctx(struct unit_module *m,
 		unit_return_fail(m, "setup channel allocation failed\n");
 	}
 
+	/* DMA_COPY should pass, but it own't allocate obj ctx */
+	err = g->ops.gr.setup.alloc_obj_ctx(gr_setup_ch, VOLTA_DMA_COPY_A, 0);
+	if (err != 0) {
+		unit_return_fail(m, "setup alloc obj_ctx failed\n");
+	}
+
 	err = g->ops.gr.setup.alloc_obj_ctx(gr_setup_ch, VOLTA_COMPUTE_A, 0);
 	if (err != 0) {
 		unit_return_fail(m, "setup alloc obj_ctx failed\n");