diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 62c8a3479..4d2980750 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -117,8 +117,8 @@ mc: class: safe: yes owner: Seshendra G - sources: [ include/nvgpu/class.h ] - + sources: [ include/nvgpu/class.h, + include/nvgpu/gops_class.h ] netlist: safe: yes diff --git a/drivers/gpu/nvgpu/include/nvgpu/class.h b/drivers/gpu/nvgpu/include/nvgpu/class.h index 07f01f4cd..bf31d6d07 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/class.h +++ b/drivers/gpu/nvgpu/include/nvgpu/class.h @@ -22,19 +22,80 @@ #ifndef NVGPU_CLASS_H #define NVGPU_CLASS_H +/** + * @defgroup NVGPU_CLASS_VALID_NUM + * + * List of valid class numbers allowed in FuSa code. + */ +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for DMA copy class methods on Kepler chips. + */ #define KEPLER_DMA_COPY_A 0xA0B5U +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for Inline to memory class methods on Kepler and chips beyond. + * The source data is always from the pushbuffer, hence the name + * inline_to_memory. + */ #define KEPLER_INLINE_TO_MEMORY_B 0xA140U -#define MAXWELL_DMA_COPY_A 0xB0B5U +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for Channel_GPFIFO class methods on Maxwell chips. + */ #define MAXWELL_CHANNEL_GPFIFO_A 0xB06FU +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for DMA copy class methods on Maxwell chips. + */ +#define MAXWELL_DMA_COPY_A 0xB0B5U +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for Channel_GPFIFO class methods on Pascal chips. + */ #define PASCAL_CHANNEL_GPFIFO_A 0xC06FU +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for DMA copy class methods on Pascal chips. + */ #define PASCAL_DMA_COPY_A 0xC0B5U +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for 3D graphics class methods on Volta chips. + * + * WAR: Lot of qnx safety tests are still using graphics 3d class. Until these + * tests get fixed, allowing 3d graphics class as valid class for + * safety build. + */ #define VOLTA_A 0xC397U +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for Channel_GPFIFO class methods on Volta chips. + */ #define VOLTA_CHANNEL_GPFIFO_A 0xC36FU +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for compute class methods on Volta chips. + */ #define VOLTA_COMPUTE_A 0xC3C0U +/** + * @ingroup NVGPU_CLASS_VALID_NUM + * + * Class number for DMA copy class methods on Volta chips. + */ #define VOLTA_DMA_COPY_A 0xC3B5U #ifdef CONFIG_NVGPU_GRAPHICS diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 96bc1d818..778d37355 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -138,6 +138,7 @@ enum nvgpu_unit; #include #include +#include #include #include #include @@ -283,14 +284,7 @@ struct gpu_ops { #endif struct gops_ce ce; struct gops_gr gr; - struct { - bool (*is_valid)(u32 class_num); - bool (*is_valid_compute)(u32 class_num); -#ifdef CONFIG_NVGPU_GRAPHICS - bool (*is_valid_gfx)(u32 class_num); -#endif - } gpu_class; - + struct gops_class gpu_class; struct gops_fb fb; struct { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_class.h b/drivers/gpu/nvgpu/include/nvgpu/gops_class.h new file mode 100644 index 000000000..d6778e930 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_class.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_GOPS_CLASS_H +#define NVGPU_GOPS_CLASS_H + +#include + +/** + * @file + * + * common.class unit HAL interface + * + */ + +/** + * common.class unit HAL operations + * + * @see gpu_ops + */ +struct gops_class { + /** + * @brief Checks if given class number is valid as per our GPU + * architechture. + * + * List of valid class numbers: + *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * 1. Graphics classes: (WAR: Lot of qnx safety tests are still using + * graphics 3d class. Until these tests get fixed, + * allowing 3d graphics class as valid class for + * safety build.) + * a. VOLTA_A --> 0xC397U + * 2. Compute classes: + * a. VOLTA_COMPUTE_A --> 0xC3C0U + * 3. DMA copy + * a. KEPLER_DMA_COPY_A --> 0xA0B5U + * b. MAXWELL_DMA_COPY_A --> 0xB0B5U + * c. PASCAL_DMA_COPY_A --> 0xC0B5U + * d. VOLTA_DMA_COPY_A --> 0xC3B5U + * 4. Inline to memory + * a. KEPLER_INLINE_TO_MEMORY_B --> 0xA140U + *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * @param class_num [in] Class number to be checked. + * + * @return true when \a class_num is one of the numbers in above list or + * false otherwise. + */ + bool (*is_valid)(u32 class_num); + + /** + * @brief Checks if given class number is valid compute class number + * as per our GPU architechture. + * + * List of valid compute class numbers: + *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * a. VOLTA_COMPUTE_A --> 0xC3C0U + *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * @param class_num [in] Class number to be checked. + * + * @return true when \a class_num is one of the numbers in above list or + * false otherwise. + */ + bool (*is_valid_compute)(u32 class_num); + + /** @cond DOXYGEN_SHOULD_SKIP_THIS */ +#ifdef CONFIG_NVGPU_GRAPHICS + bool (*is_valid_gfx)(u32 class_num); +#endif + /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ +}; + +#endif /* NVGPU_GOPS_CLASS_H */