gpu: nvgpu: Remove NVGPU_IOCTL_GET_BUFFER_INFO

The IOCTL was introduced for making efficient query of buffer
identity and size. It was never taken into use, and it adds a
dependency to Tegra specific dma_buf API, so remove it.

JIRA NVGPU-4

Change-Id: I194d7bb1f54997900a3be8d39c93331befa225c7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648001
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-01-24 13:06:37 -08:00
committed by mobile promotions
parent f229149f97
commit 8ca1a765ee
4 changed files with 3 additions and 53 deletions

View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -140,7 +140,6 @@ int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev)
{ {
struct gk20a *g = gk20a_get_platform(dev)->g; struct gk20a *g = gk20a_get_platform(dev)->g;
struct gk20a_dmabuf_priv *priv; struct gk20a_dmabuf_priv *priv;
static u64 priv_count = 0;
priv = dma_buf_get_drvdata(dmabuf, dev); priv = dma_buf_get_drvdata(dmabuf, dev);
if (likely(priv)) if (likely(priv))
@@ -159,7 +158,6 @@ int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev)
nvgpu_mutex_init(&priv->lock); nvgpu_mutex_init(&priv->lock);
nvgpu_init_list_node(&priv->states); nvgpu_init_list_node(&priv->states);
priv->buffer_id = ++priv_count;
priv->g = g; priv->g = g;
dma_buf_set_drvdata(dmabuf, dev, priv, gk20a_mm_delete_priv); dma_buf_set_drvdata(dmabuf, dev, priv, gk20a_mm_delete_priv);
@@ -214,34 +212,3 @@ out:
*state = s; *state = s;
return err; return err;
} }
int gk20a_mm_get_buffer_info(struct device *dev, int dmabuf_fd,
u64 *buffer_id, u64 *buffer_len)
{
struct dma_buf *dmabuf;
struct gk20a_dmabuf_priv *priv;
int err = 0;
dmabuf = dma_buf_get(dmabuf_fd);
if (IS_ERR(dmabuf)) {
dev_warn(dev, "%s: fd %d is not a dmabuf", __func__, dmabuf_fd);
return PTR_ERR(dmabuf);
}
err = gk20a_dmabuf_alloc_drvdata(dmabuf, dev);
if (err) {
dev_warn(dev, "Failed to allocate dmabuf drvdata (err = %d)",
err);
goto clean_up;
}
priv = dma_buf_get_drvdata(dmabuf, dev);
if (likely(priv)) {
*buffer_id = priv->buffer_id;
*buffer_len = dmabuf->size;
}
clean_up:
dma_buf_put(dmabuf);
return err;
}

View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -57,7 +57,4 @@ int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev);
int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g, int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g,
u64 offset, struct gk20a_buffer_state **state); u64 offset, struct gk20a_buffer_state **state);
int gk20a_mm_get_buffer_info(struct device *dev, int dmabuf_fd,
u64 *buffer_id, u64 *buffer_len);
#endif #endif

View File

@@ -753,13 +753,6 @@ static int gk20a_ctrl_vsm_mapping(struct gk20a *g,
return err; return err;
} }
static int gk20a_ctrl_get_buffer_info(
struct gk20a *g, struct nvgpu_gpu_get_buffer_info_args *args)
{
return gk20a_mm_get_buffer_info(dev_from_gk20a(g), args->in.dmabuf_fd,
&args->out.id, &args->out.length);
}
static int nvgpu_gpu_get_cpu_time_correlation_info( static int nvgpu_gpu_get_cpu_time_correlation_info(
struct gk20a *g, struct gk20a *g,
struct nvgpu_gpu_get_cpu_time_correlation_info_args *args) struct nvgpu_gpu_get_cpu_time_correlation_info_args *args)
@@ -1757,11 +1750,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
(struct nvgpu_gpu_vsms_mapping *)buf); (struct nvgpu_gpu_vsms_mapping *)buf);
break; break;
case NVGPU_GPU_IOCTL_GET_BUFFER_INFO:
err = gk20a_ctrl_get_buffer_info(g,
(struct nvgpu_gpu_get_buffer_info_args *)buf);
break;
case NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO: case NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO:
err = nvgpu_gpu_get_cpu_time_correlation_info(g, err = nvgpu_gpu_get_cpu_time_correlation_info(g,
(struct nvgpu_gpu_get_cpu_time_correlation_info_args *)buf); (struct nvgpu_gpu_get_cpu_time_correlation_info_args *)buf);

View File

@@ -1,7 +1,7 @@
/* /*
* NVGPU Public Interface Header * NVGPU Public Interface Header
* *
* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -892,8 +892,6 @@ struct nvgpu_gpu_set_deterministic_opts_args {
_IOWR(NVGPU_GPU_IOCTL_MAGIC, 18, struct nvgpu_gpu_num_vsms) _IOWR(NVGPU_GPU_IOCTL_MAGIC, 18, struct nvgpu_gpu_num_vsms)
#define NVGPU_GPU_IOCTL_VSMS_MAPPING \ #define NVGPU_GPU_IOCTL_VSMS_MAPPING \
_IOWR(NVGPU_GPU_IOCTL_MAGIC, 19, struct nvgpu_gpu_vsms_mapping) _IOWR(NVGPU_GPU_IOCTL_MAGIC, 19, struct nvgpu_gpu_vsms_mapping)
#define NVGPU_GPU_IOCTL_GET_BUFFER_INFO \
_IOWR(NVGPU_GPU_IOCTL_MAGIC, 20, struct nvgpu_gpu_get_buffer_info_args)
#define NVGPU_GPU_IOCTL_RESUME_FROM_PAUSE \ #define NVGPU_GPU_IOCTL_RESUME_FROM_PAUSE \
_IO(NVGPU_GPU_IOCTL_MAGIC, 21) _IO(NVGPU_GPU_IOCTL_MAGIC, 21)
#define NVGPU_GPU_IOCTL_TRIGGER_SUSPEND \ #define NVGPU_GPU_IOCTL_TRIGGER_SUSPEND \