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gpu: nvgpu: Remove NVGPU_IOCTL_GET_BUFFER_INFO
The IOCTL was introduced for making efficient query of buffer identity and size. It was never taken into use, and it adds a dependency to Tegra specific dma_buf API, so remove it. JIRA NVGPU-4 Change-Id: I194d7bb1f54997900a3be8d39c93331befa225c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1648001 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -140,7 +140,6 @@ int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev)
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{
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{
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struct gk20a *g = gk20a_get_platform(dev)->g;
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struct gk20a *g = gk20a_get_platform(dev)->g;
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struct gk20a_dmabuf_priv *priv;
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struct gk20a_dmabuf_priv *priv;
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static u64 priv_count = 0;
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priv = dma_buf_get_drvdata(dmabuf, dev);
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priv = dma_buf_get_drvdata(dmabuf, dev);
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if (likely(priv))
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if (likely(priv))
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@@ -159,7 +158,6 @@ int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev)
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nvgpu_mutex_init(&priv->lock);
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nvgpu_mutex_init(&priv->lock);
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nvgpu_init_list_node(&priv->states);
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nvgpu_init_list_node(&priv->states);
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priv->buffer_id = ++priv_count;
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priv->g = g;
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priv->g = g;
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dma_buf_set_drvdata(dmabuf, dev, priv, gk20a_mm_delete_priv);
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dma_buf_set_drvdata(dmabuf, dev, priv, gk20a_mm_delete_priv);
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@@ -214,34 +212,3 @@ out:
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*state = s;
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*state = s;
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return err;
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return err;
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}
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}
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int gk20a_mm_get_buffer_info(struct device *dev, int dmabuf_fd,
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u64 *buffer_id, u64 *buffer_len)
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{
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struct dma_buf *dmabuf;
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struct gk20a_dmabuf_priv *priv;
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int err = 0;
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dmabuf = dma_buf_get(dmabuf_fd);
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if (IS_ERR(dmabuf)) {
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dev_warn(dev, "%s: fd %d is not a dmabuf", __func__, dmabuf_fd);
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return PTR_ERR(dmabuf);
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}
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err = gk20a_dmabuf_alloc_drvdata(dmabuf, dev);
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if (err) {
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dev_warn(dev, "Failed to allocate dmabuf drvdata (err = %d)",
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err);
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goto clean_up;
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}
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priv = dma_buf_get_drvdata(dmabuf, dev);
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if (likely(priv)) {
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*buffer_id = priv->buffer_id;
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*buffer_len = dmabuf->size;
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}
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clean_up:
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dma_buf_put(dmabuf);
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return err;
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}
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -57,7 +57,4 @@ int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev);
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int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g,
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int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g,
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u64 offset, struct gk20a_buffer_state **state);
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u64 offset, struct gk20a_buffer_state **state);
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int gk20a_mm_get_buffer_info(struct device *dev, int dmabuf_fd,
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u64 *buffer_id, u64 *buffer_len);
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#endif
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#endif
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@@ -753,13 +753,6 @@ static int gk20a_ctrl_vsm_mapping(struct gk20a *g,
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return err;
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return err;
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}
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}
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static int gk20a_ctrl_get_buffer_info(
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struct gk20a *g, struct nvgpu_gpu_get_buffer_info_args *args)
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{
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return gk20a_mm_get_buffer_info(dev_from_gk20a(g), args->in.dmabuf_fd,
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&args->out.id, &args->out.length);
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}
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static int nvgpu_gpu_get_cpu_time_correlation_info(
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static int nvgpu_gpu_get_cpu_time_correlation_info(
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struct gk20a *g,
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struct gk20a *g,
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struct nvgpu_gpu_get_cpu_time_correlation_info_args *args)
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struct nvgpu_gpu_get_cpu_time_correlation_info_args *args)
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@@ -1757,11 +1750,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
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(struct nvgpu_gpu_vsms_mapping *)buf);
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(struct nvgpu_gpu_vsms_mapping *)buf);
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break;
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break;
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case NVGPU_GPU_IOCTL_GET_BUFFER_INFO:
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err = gk20a_ctrl_get_buffer_info(g,
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(struct nvgpu_gpu_get_buffer_info_args *)buf);
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break;
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case NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO:
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case NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO:
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err = nvgpu_gpu_get_cpu_time_correlation_info(g,
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err = nvgpu_gpu_get_cpu_time_correlation_info(g,
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(struct nvgpu_gpu_get_cpu_time_correlation_info_args *)buf);
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(struct nvgpu_gpu_get_cpu_time_correlation_info_args *)buf);
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@@ -1,7 +1,7 @@
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/*
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/*
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* NVGPU Public Interface Header
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* NVGPU Public Interface Header
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*
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*
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* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -892,8 +892,6 @@ struct nvgpu_gpu_set_deterministic_opts_args {
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_IOWR(NVGPU_GPU_IOCTL_MAGIC, 18, struct nvgpu_gpu_num_vsms)
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_IOWR(NVGPU_GPU_IOCTL_MAGIC, 18, struct nvgpu_gpu_num_vsms)
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#define NVGPU_GPU_IOCTL_VSMS_MAPPING \
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#define NVGPU_GPU_IOCTL_VSMS_MAPPING \
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_IOWR(NVGPU_GPU_IOCTL_MAGIC, 19, struct nvgpu_gpu_vsms_mapping)
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_IOWR(NVGPU_GPU_IOCTL_MAGIC, 19, struct nvgpu_gpu_vsms_mapping)
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#define NVGPU_GPU_IOCTL_GET_BUFFER_INFO \
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_IOWR(NVGPU_GPU_IOCTL_MAGIC, 20, struct nvgpu_gpu_get_buffer_info_args)
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#define NVGPU_GPU_IOCTL_RESUME_FROM_PAUSE \
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#define NVGPU_GPU_IOCTL_RESUME_FROM_PAUSE \
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_IO(NVGPU_GPU_IOCTL_MAGIC, 21)
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_IO(NVGPU_GPU_IOCTL_MAGIC, 21)
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#define NVGPU_GPU_IOCTL_TRIGGER_SUSPEND \
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#define NVGPU_GPU_IOCTL_TRIGGER_SUSPEND \
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