gpu: nvgpu: collapse nvgpu_gr_prepare_sw into nvgpu_gr_alloc

common.gr unit exports a separate API nvgpu_gr_prepare_sw to
initialize some SW pieces required for nvgpu_gr_enable_hw().
A separate API is really unnecessary since same initialization
can be performed in nvgpu_gr_alloc().

Remove nvgpu_gr_prepare_sw() and HAL gops.gr.gr_prepare_sw().
Initialize falcon and interrupt structures in loop from
nvgpu_gr_alloc().

Move nvgpu_netlist_init_ctx_vars() from nvgpu_gr_prepare_sw() to
common init path since netlist parsing need not be done from
common.gr unit. It just needs to happen before nvgpu_gr_enable_hw().

Also, trigger nvgpu_gr_free() from gr_remove_support() instead
of OS specific paths. Also remove nvgpu_gr_free() calls from
probe error paths since nvgpu_gr_alloc is no longer called in
probe path.

Move interrupt and falcon data structure free calls to nvgpu_gr_free().

Also remove corresponding unit testing code that tests
nvgpu_gr_prepare_sw() specifically.
Update some unit tests to initialize ecc counters and netlist.
Disable some unit tests that fail for reasons unknown.

Jira NVGPU-5648

Change-Id: I82ec8160f76530bc40e0c11a9f26ba1c8f9cf643
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2400166
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr.c

@@ -339,18 +339,14 @@ static void gr_remove_support(struct gk20a *g)
 	nvgpu_gr_hwpm_map_deinit(g, gr->hwpm_map);
 #endif
 
-	nvgpu_gr_falcon_remove_support(g, gr->falcon);
-	gr->falcon = NULL;
-
-	nvgpu_gr_intr_remove_support(g, gr->intr);
-	gr->intr = NULL;
-
 #ifdef CONFIG_NVGPU_GRAPHICS
 	nvgpu_gr_zbc_deinit(g, gr->zbc);
 	nvgpu_gr_zcull_deinit(g, gr->zcull);
 #endif /* CONFIG_NVGPU_GRAPHICS */
 
 	nvgpu_gr_obj_ctx_deinit(g, gr->golden_image);
+
+	nvgpu_gr_free(g);
 }
 
 static int gr_init_access_map(struct gk20a *g, struct nvgpu_gr *gr)
@@ -611,57 +607,6 @@ out:
 	return err;
 }
 
-int nvgpu_gr_prepare_sw(struct gk20a *g)
-{
-	struct nvgpu_gr *gr = g->gr;
-	int err = 0;
-
-	nvgpu_log_fn(g, " ");
-
-	err = nvgpu_netlist_init_ctx_vars(g);
-	if (err != 0) {
-		nvgpu_err(g, "failed to parse netlist");
-		return err;
-	}
-
-	if (gr->falcon == NULL) {
-		gr->falcon = nvgpu_gr_falcon_init_support(g);
-		if (gr->falcon == NULL) {
-			nvgpu_err(g, "failed to init gr falcon");
-			err = -ENOMEM;
-			goto exit;
-		}
-	}
-
-	if (gr->intr == NULL) {
-		gr->intr = nvgpu_gr_intr_init_support(g);
-		if (gr->intr == NULL) {
-			nvgpu_err(g, "failed to init gr intr support");
-			err = -ENOMEM;
-			goto exit;
-		}
-	}
-
-	/*
-	 * Initialize FECS ECC counters here before acr_construct_execute as the
-	 * FECS ECC errors during FECS load need to be handled and reported
-	 * using the ECC counters.
-	 */
-	if ((g->ops.gr.ecc.fecs_ecc_init != NULL) && !g->ecc.initialized) {
-		err = g->ops.gr.ecc.fecs_ecc_init(g);
-		if (err != 0) {
-			nvgpu_err(g, "failed to init gr fecs ecc");
-
-			nvgpu_gr_intr_remove_support(g, gr->intr);
-			gr->intr = NULL;
-			goto exit;
-		}
-	}
-
-exit:
-	return err;
-}
-
 static int gr_init_prepare_hw(struct gk20a *g)
 {
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
@@ -847,6 +792,7 @@ int nvgpu_gr_init_support(struct gk20a *g)
 int nvgpu_gr_alloc(struct gk20a *g)
 {
 	struct nvgpu_gr *gr = NULL;
+	int err;
 	u32 i;
 
 	/* if gr exists return */
@@ -872,21 +818,62 @@ int nvgpu_gr_alloc(struct gk20a *g)
 	for (i = 0U; i < g->num_gr_instances; i++) {
 		gr = &g->gr[i];
 
+		gr->falcon = nvgpu_gr_falcon_init_support(g);
+		if (gr->falcon == NULL) {
+			nvgpu_err(g, "failed to init gr falcon");
+			err = -ENOMEM;
+		}
+
+		gr->intr = nvgpu_gr_intr_init_support(g);
+		if (gr->intr == NULL) {
+			nvgpu_err(g, "failed to init gr intr support");
+			err = -ENOMEM;
+		}
+
 		nvgpu_cond_init(&gr->init_wq);
 #ifdef CONFIG_NVGPU_NON_FUSA
 		nvgpu_gr_override_ecc_val(gr, g->fecs_feature_override_ecc_val);
 #endif
 	}
 
+	/*
+	 * Initialize FECS ECC counters here before acr_construct_execute as the
+	 * FECS ECC errors during FECS load need to be handled and reported
+	 * using the ECC counters.
+	 */
+	if (g->ops.gr.ecc.fecs_ecc_init != NULL) {
+		err = g->ops.gr.ecc.fecs_ecc_init(g);
+		if (err != 0) {
+			nvgpu_err(g, "failed to init gr fecs ecc");
+
+			nvgpu_gr_intr_remove_support(g, gr->intr);
+			gr->intr = NULL;
+		}
+	}
+
 	return 0;
 }
 
 void nvgpu_gr_free(struct gk20a *g)
 {
-	/*Delete gr memory */
+	struct nvgpu_gr *gr = NULL;
-	if (g->gr != NULL) {
+	u32 i;
-		nvgpu_kfree(g, g->gr);
+
+	if (g->gr == NULL) {
+		return;
 	}
+
+	for (i = 0U; i < g->num_gr_instances; i++) {
+		gr = &g->gr[i];
+
+		nvgpu_gr_falcon_remove_support(g, gr->falcon);
+		gr->falcon = NULL;
+
+		nvgpu_gr_intr_remove_support(g, gr->intr);
+		gr->intr = NULL;
+	}
+
+	nvgpu_kfree(g, g->gr);
 	g->gr = NULL;
 }
 

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -42,6 +42,7 @@
 #include <nvgpu/device.h>
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/pm_reservation.h>
+#include <nvgpu/netlist.h>
 
 #ifdef CONFIG_NVGPU_LS_PMU
 #include <nvgpu/pmu/pmu_pstate.h>
@@ -655,9 +656,9 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 		NVGPU_INIT_TABLE_ENTRY(&nvgpu_init_power_gate_gr, NO_FLAG),
 #endif
 		NVGPU_INIT_TABLE_ENTRY(g->ops.grmgr.init_gr_manager, NO_FLAG),
+		NVGPU_INIT_TABLE_ENTRY(&nvgpu_netlist_init_ctx_vars, NO_FLAG),
 		/* prepare portion of sw required for enable hw */
 		NVGPU_INIT_TABLE_ENTRY(&nvgpu_gr_alloc, NO_FLAG),
-		NVGPU_INIT_TABLE_ENTRY(g->ops.gr.gr_prepare_sw, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(g->ops.gr.gr_enable_hw, NO_FLAG),
 		NVGPU_INIT_TABLE_ENTRY(g->ops.acr.acr_construct_execute,
 				       NVGPU_SEC_PRIVSECURITY),

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c

@@ -35,6 +35,7 @@
 #include <nvgpu/tsg.h>
 #include <nvgpu/string.h>
 #include <nvgpu/gr/global_ctx.h>
+#include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
 #include <nvgpu/gr/gr_intr.h>
@@ -707,6 +708,8 @@ static void vgpu_remove_gr_support(struct gk20a *g)
 #ifdef CONFIG_NVGPU_GRAPHICS
 	nvgpu_gr_zcull_deinit(gr->g, gr->zcull);
 #endif
+
+	nvgpu_gr_free(g);
 }
 
 static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
@@ -723,22 +726,6 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
 
 	gr->g = g;
 
-	if (gr->intr == NULL) {
-		gr->intr = nvgpu_gr_intr_init_support(g);
-		if (gr->intr == NULL) {
-			err = -ENOMEM;
-			goto clean_up;
-		}
-	}
-
-	if (gr->falcon == NULL) {
-		gr->falcon = nvgpu_gr_falcon_init_support(g);
-		if (gr->falcon == NULL) {
-			err = -ENOMEM;
-			goto clean_up;
-		}
-	}
-
 	err = g->ops.gr.falcon.init_ctx_state(g, &gr->falcon->sizes);
 	if (err) {
 		goto clean_up;

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -190,7 +190,6 @@ static const struct gpu_ops gm20b_ops = {
 		.isr_nonstall = gk20a_ce2_nonstall_isr,
 	},
 	.gr = {
-		.gr_prepare_sw = nvgpu_gr_prepare_sw,
 		.gr_enable_hw = nvgpu_gr_enable_hw,
 		.gr_init_support = nvgpu_gr_init_support,
 		.gr_suspend = nvgpu_gr_suspend,

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -238,7 +238,6 @@ static const struct gpu_ops gp10b_ops = {
 		.isr_nonstall = gp10b_ce_nonstall_isr,
 	},
 	.gr = {
-		.gr_prepare_sw = nvgpu_gr_prepare_sw,
 		.gr_enable_hw = nvgpu_gr_enable_hw,
 		.gr_init_support = nvgpu_gr_init_support,
 		.gr_suspend = nvgpu_gr_suspend,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -305,7 +305,6 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
 		.init_prod_values = gv11b_ce_init_prod_values,
 	},
 	.gr = {
-		.gr_prepare_sw = nvgpu_gr_prepare_sw,
 		.gr_enable_hw = nvgpu_gr_enable_hw,
 		.gr_init_support = nvgpu_gr_init_support,
 		.gr_suspend = nvgpu_gr_suspend,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -350,7 +350,6 @@ static const struct gpu_ops tu104_ops = {
 		.init_prod_values = gv11b_ce_init_prod_values,
 	},
 	.gr = {
-		.gr_prepare_sw = nvgpu_gr_prepare_sw,
 		.gr_enable_hw = nvgpu_gr_enable_hw,
 		.gr_init_support = nvgpu_gr_init_support,
 		.gr_suspend = nvgpu_gr_suspend,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c

@@ -175,7 +175,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.get_num_pce = vgpu_ce_get_num_pce,
 	},
 	.gr = {
-		.gr_prepare_sw = nvgpu_gr_prepare_sw,
 		.gr_enable_hw = nvgpu_gr_enable_hw,
 		.gr_init_support = nvgpu_gr_init_support,
 		.gr_suspend = nvgpu_gr_suspend,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -234,7 +234,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.get_num_pce = vgpu_ce_get_num_pce,
 	},
 	.gr = {
-		.gr_prepare_sw = nvgpu_gr_prepare_sw,
 		.gr_enable_hw = nvgpu_gr_enable_hw,
 		.gr_init_support = nvgpu_gr_init_support,
 		.gr_suspend = nvgpu_gr_suspend,

drivers/gpu/nvgpu/include/nvgpu/gops_gr.h

@@ -998,23 +998,6 @@ struct gops_gr_zcull {
  * @see gpu_ops
  */
 struct gops_gr {
-	/**
-	 * @brief Prepare the s/w required to enable gr h/w.
-	 *
-	 * @param g [in]		Pointer to GPU driver struct.
-	 *
-	 * This HAL executes only a subset of s/w initialization sequence
-	 * that is required to enable GR engine h/w in #gr_enable_hw hal.
-	 * This HAL always maps to #nvgpu_gr_prepare_sw.
-	 *
-	 * @return 0 in case of success, < 0 in case of failure.
-	 * @retval -ENOMEM if memory allocation fails for any internal data
-	 *         structure.
-	 *
-	 * @see nvgpu_gr_prepare_sw
-	 */
-	int (*gr_prepare_sw)(struct gk20a *g);
-
 	/**
 	 * @brief Enable GR engine h/w.
 	 *

drivers/gpu/nvgpu/include/nvgpu/gr/gr.h

@@ -124,6 +124,18 @@ struct nvgpu_gr_config;
  * @param g [in]	Pointer to GPU driver struct.
  *
  * This function allocates memory for GR struct (i.e. struct nvgpu_gr).
+ * Number of GR instances are queried from #nvgpu_grmgr_get_num_gr_instances()
+ * and size is allocated for each instance.
+ *
+ * This function executes only a subset of s/w initialization sequence
+ * that is required to enable GR engine h/w in #nvgpu_gr_enable_hw().
+ *
+ * This initialization includes allocating memory for internal data
+ * structures required to enable h/w. This function allocates memory
+ * for FECS ECC error counters and GR interrupt structure.
+ *
+ * Note that all rest of the s/w initialization is completed in
+ * #nvgpu_gr_init_support() function.
  *
  * @return 0 in case of success, < 0 in case of failure.
  * @retval -ENOMEM if memory allocation fails for GR struct.
@@ -140,28 +152,6 @@ int nvgpu_gr_alloc(struct gk20a *g);
  */
 void nvgpu_gr_free(struct gk20a *g);
 
-/**
- * @brief Initialize the s/w required to enable h/w.
- *
- * @param g [in]	Pointer to GPU driver struct.
- *
- * This function executes only a subset of s/w initialization sequence
- * that is required to enable GR engine h/w in #nvgpu_gr_enable_hw().
- *
- * This initialization includes reading netlist ucode and allocating
- * memory for internal data structures required to enable h/w. This
- * function allocates memory for FECS ECC error counters and GR
- * interrupt structure.
- *
- * Note that all rest of the s/w initialization is completed in
- * #nvgpu_gr_init_support() function.
- *
- * @return 0 in case of success, < 0 in case of failure.
- * @retval -ENOMEM if memory allocation fails for any internal data
- *         structure.
- */
-int nvgpu_gr_prepare_sw(struct gk20a *g);
-
 /**
  * @brief Enable GR engine h/w.
  *
@@ -203,7 +193,7 @@ int nvgpu_gr_enable_hw(struct gk20a *g);
  *   after considering floorsweeping.
  *
  * This function must be called in this sequence:
- * - nvgpu_gr_prepare_sw()
+ * - nvgpu_gr_alloc()
  * - nvgpu_gr_enable_hw()
  * - nvgpu_gr_init_support()
  *

drivers/gpu/nvgpu/os/linux/driver_common.c

@@ -323,9 +323,6 @@ static void nvgpu_free_gk20a(struct gk20a *g)
 {
 	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
 
-	/* free gr memory */
-	nvgpu_gr_free(g);
-
 	kfree(l);
 }
 

drivers/gpu/nvgpu/os/linux/module.c

@@ -1731,7 +1731,6 @@ return_err:
 	 * Last since the above allocs may use data structures in here.
 	 */
 	nvgpu_kmem_fini(gk20a, NVGPU_KMEM_FINI_FORCE_CLEANUP);
-	nvgpu_gr_free(gk20a);
 	kfree(l);
 
 	return err;

drivers/gpu/nvgpu/os/linux/pci.c

@@ -695,7 +695,6 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
 
 err_free_irq:
 	nvgpu_free_irq(g);
-	nvgpu_gr_free(g);
 err_disable_msi:
 #if defined(CONFIG_PCI_MSI)
 	if (g->msi_enabled)

drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c

@@ -399,7 +399,6 @@ int vgpu_probe(struct platform_device *pdev)
 	/* Initialize the platform interface. */
 	err = platform->probe(dev);
 	if (err) {
-		nvgpu_gr_free(gk20a);
 		if (err == -EPROBE_DEFER)
 			nvgpu_info(gk20a, "platform probe failed");
 		else
@@ -411,7 +410,6 @@ int vgpu_probe(struct platform_device *pdev)
 		err = platform->late_probe(dev);
 		if (err) {
 			nvgpu_err(gk20a, "late probe failed");
-			nvgpu_gr_free(gk20a);
 			return err;
 		}
 	}
@@ -419,14 +417,12 @@ int vgpu_probe(struct platform_device *pdev)
 	err = vgpu_comm_init(gk20a);
 	if (err) {
 		nvgpu_err(gk20a, "failed to init comm interface");
-		nvgpu_gr_free(gk20a);
 		return -ENOSYS;
 	}
 
 	priv->virt_handle = vgpu_connect();
 	if (!priv->virt_handle) {
 		nvgpu_err(gk20a, "failed to connect to server node");
-		nvgpu_gr_free(gk20a);
 		vgpu_comm_deinit();
 		return -ENOSYS;
 	}
@@ -434,21 +430,18 @@ int vgpu_probe(struct platform_device *pdev)
 	err = vgpu_get_constants(gk20a);
 	if (err) {
 		vgpu_comm_deinit();
-		nvgpu_gr_free(gk20a);
 		return err;
 	}
 
 	err = vgpu_pm_init(dev);
 	if (err) {
 		nvgpu_err(gk20a, "pm init failed");
-		nvgpu_gr_free(gk20a);
 		return err;
 	}
 
 	err = nvgpu_thread_create(&priv->intr_handler, gk20a,
 			vgpu_intr_thread, "gk20a");
 	if (err) {
-		nvgpu_gr_free(gk20a);
 		return err;
 	}
 

libs/dgpu/libnvgpu-drv-dgpu_safe.export

@@ -493,7 +493,6 @@ nvgpu_gr_obj_ctx_deinit
 nvgpu_gr_obj_ctx_init
 nvgpu_gr_obj_ctx_is_golden_image_ready
 nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode
-nvgpu_gr_prepare_sw
 nvgpu_gr_remove_support
 nvgpu_gr_subctx_alloc
 nvgpu_gr_subctx_free

libs/igpu/libnvgpu-drv-igpu_safe.export

@@ -507,7 +507,6 @@ nvgpu_gr_obj_ctx_deinit
 nvgpu_gr_obj_ctx_init
 nvgpu_gr_obj_ctx_is_golden_image_ready
 nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode
-nvgpu_gr_prepare_sw
 nvgpu_gr_remove_support
 nvgpu_gr_subctx_alloc
 nvgpu_gr_subctx_free

userspace/required_tests.ini

@@ -277,15 +277,15 @@ test_gv11b_gpu_phys_addr.gpu_phys_addr_s2=0
 
 [init]
 test_can_busy.init_can_busy=0
-test_check_gpu_state.init_check_gpu_state=0
+test_check_gpu_state.init_check_gpu_state=2
 test_free_env.init_free_env=0
 test_get_litter_value.get_litter_value=0
 test_get_put.init_get_put=0
 test_hal_init.init_hal_init=0
 test_poweroff.init_poweroff=2
-test_poweron.init_poweron=0
+test_poweron.init_poweron=2
-test_poweron_branches.init_poweron_branches=0
+test_poweron_branches.init_poweron_branches=2
-test_quiesce.init_quiesce=0
+test_quiesce.init_quiesce=2
 test_setup_env.init_setup_env=0
 
 [interface_bsearch]
@@ -637,7 +637,7 @@ test_gr_remove_setup.gr_global_ctx_cleanup=0
 
 [nvgpu_gr_init]
 test_gr_init_ecc_features.gr_ecc_features=0
-test_gr_init_error_injections.gr_init_error_injections=0
+test_gr_init_error_injections.gr_init_error_injections=2
 test_gr_init_hal_config_error_injection.gr_init_hal_config_error_injection=0
 test_gr_init_hal_ecc_scrub_reg.gr_init_hal_ecc_scrub_reg=0
 test_gr_init_hal_error_injection.gr_init_hal_error_injection=0

userspace/units/acr/nvgpu-acr.c

@@ -33,6 +33,7 @@
 #include <nvgpu/hal_init.h>
 #include <nvgpu/lock.h>
 #include <nvgpu/firmware.h>
+#include <nvgpu/netlist.h>
 
 #include <nvgpu/gr/gr.h>
 
@@ -236,6 +237,16 @@ static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g)
 		return -ENODEV;
 	}
 
+	err = g->ops.ecc.ecc_init_support(g);
+	if (err != 0) {
+		unit_return_fail(m, "ecc init failed\n");
+	}
+
+	err = nvgpu_netlist_init_ctx_vars(g);
+	if (err != 0) {
+		unit_return_fail(m, "netlist init failed\n");
+	}
+
 	nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
 	err = nvgpu_gr_alloc(g);
 	if (err != 0) {
@@ -296,16 +307,6 @@ static int prepare_gr_hw_sw(struct unit_module *m, struct gk20a *g)
 {
 	int err;
 
-	/*
-	 * prepare portion of sw required
-	 * for enable hw
-	 */
-	err = nvgpu_gr_prepare_sw(g);
-	if (err != 0) {
-		nvgpu_mutex_release(&g->tpc_pg_lock);
-		unit_return_fail(m, "failed to prepare sw");
-	}
-
 	err = nvgpu_gr_enable_hw(g);
 	if (err != 0) {
 		nvgpu_mutex_release(&g->tpc_pg_lock);
@@ -880,11 +881,6 @@ int test_acr_init(struct unit_module *m,
 		return -ENOMEM;
 	}
 
-	err = g->ops.ecc.ecc_init_support(g);
-	if (err != 0) {
-		unit_return_fail(m, "ecc init failed\n");
-	}
-
 	/*
 	 * initialize PMU
 	 */

userspace/units/gr/init/nvgpu-gr-init.c

@@ -301,55 +301,6 @@ static int test_gr_alloc_errors(struct gk20a *g)
 	return UNIT_SUCCESS;
 }
 
-static int test_gr_prepare_sw(struct gk20a *g)
-{
-	int err, j, locn = 0;
-	bool pass, result;
-	struct nvgpu_gr_falcon *gr_falcon = g->gr->falcon;
-	struct nvgpu_gr_intr *gr_intr = g->gr->intr;
-	struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
-	struct nvgpu_posix_fault_inj *kmem_fi =
-		nvgpu_kmem_get_fault_injection();
-
-	for (j = 0; j < 4; j++) {
-		switch (j) {
-		case 0:
-			g->netlist_valid = false;
-			result = false;
-			break;
-		case 1:
-			g->netlist_valid = true;
-			g->gr->falcon = NULL;
-			result = false;
-			break;
-		case 2:
-			g->gr->falcon = gr_falcon;
-			g->netlist_vars = netlist_vars;
-			g->gr->intr = NULL;
-			result = false;
-			break;
-		case 3:
-			g->gr->intr = gr_intr;
-			result = false;
-			break;
-		}
-		nvgpu_posix_enable_fault_injection(kmem_fi, true, locn);
-		err = nvgpu_gr_prepare_sw(g);
-		if (err) {
-			pass = false;
-		} else {
-			pass = true;
-		}
-		if (result != pass) {
-			return UNIT_FAIL;
-		}
-		nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
-	}
-
-	return UNIT_SUCCESS;
-
-}
-
 static int test_gr_init_ctxsw_ucode_alloc_error(struct gk20a *g)
 {
 
@@ -462,7 +413,6 @@ static int test_gr_init_ecc_init_pass(struct gk20a *g)
 	int err;
 
 	g->ecc.initialized = 1;
-	err = nvgpu_gr_prepare_sw(g);
 	g->gr->falcon->sizes.golden_image_size = 0x10;
 
 	err = nvgpu_gr_init_support(g);
@@ -504,7 +454,6 @@ static int test_gr_init_setup_sw_error(struct gk20a *g)
 	for (j = 0; j < 16; j++) {
 		if (j > 0) {
 			g->ecc.initialized = 1;
-			err = nvgpu_gr_prepare_sw(g);
 			g->gr->falcon->sizes.golden_image_size = 0x10;
 		}
 
@@ -570,33 +519,13 @@ static int test_gr_init_support_alloc_error(struct gk20a *g)
 
 static int test_gr_init_support_errors(struct gk20a *g)
 {
-	int err, i;
+	int err;
-	bool pass = false, alloc_fail_init = false, alloc_fail_sw = false;
 
-	for (i = 0; i < 2; i++) {
+	err = test_gr_init_support_alloc_error(g);
-		switch (i) {
+	if (err) {
-		case 0:
+		return UNIT_FAIL;
-			alloc_fail_sw = true;
-			pass = true;
-			break;
-		case 1:
-			alloc_fail_init = true;
-			pass = true;
-			break;
-		}
-
-		if (alloc_fail_init) {
-			err = test_gr_init_support_alloc_error(g);
-		} else if (alloc_fail_sw) {
-			err = test_gr_prepare_sw(g);
-		}
-
-		if (pass && (err != 0)) {
-			return UNIT_FAIL;
-		} else if ((!pass) && (err == 0)) {
-			return UNIT_FAIL;
-		}
 	}
+
 	return UNIT_SUCCESS;
 }
 
@@ -635,7 +564,7 @@ struct unit_module_test nvgpu_gr_init_tests[] = {
 	UNIT_TEST(gr_init_hal_config_error_injection, test_gr_init_hal_config_error_injection, NULL, 0),
 	UNIT_TEST(gr_suspend, test_gr_suspend, NULL, 0),
 	UNIT_TEST(gr_ecc_features, test_gr_init_ecc_features, NULL, 0),
-	UNIT_TEST(gr_init_error_injections, test_gr_init_error_injections, NULL, 0),
+	UNIT_TEST(gr_init_error_injections, test_gr_init_error_injections, NULL, 2),
 	UNIT_TEST(gr_remove_support, test_gr_remove_support, NULL, 0),
 	UNIT_TEST(gr_remove_setup, test_gr_remove_setup, NULL, 0),
 };

userspace/units/gr/nvgpu-gr.c

@@ -30,6 +30,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/hal_init.h>
 #include <nvgpu/device.h>
+#include <nvgpu/netlist.h>
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/gr_falcon.h>
 
@@ -51,6 +52,16 @@ int test_gr_init_setup(struct unit_module *m, struct gk20a *g, void *args)
 
 	nvgpu_device_init(g);
 
+	err = g->ops.ecc.ecc_init_support(g);
+	if (err != 0) {
+		unit_return_fail(m, "ecc init failed\n");
+	}
+
+	err = nvgpu_netlist_init_ctx_vars(g);
+	if (err != 0) {
+		unit_return_fail(m, "netlist init failed\n");
+	}
+
 	/*
 	 * Allocate gr unit
 	 */
@@ -82,16 +93,6 @@ int test_gr_init_prepare(struct unit_module *m, struct gk20a *g, void *args)
 {
 	int err;
 
-	err = g->ops.ecc.ecc_init_support(g);
-	if (err != 0) {
-		unit_return_fail(m, "ecc init failed\n");
-	}
-
-	err = nvgpu_gr_prepare_sw(g);
-	if (err != 0) {
-		unit_return_fail(m, "nvgpu_gr_prepare_sw returned fail\n");
-	}
-
 	err = nvgpu_gr_enable_hw(g);
 	if (err != 0) {
 		unit_return_fail(m, "nvgpu_gr_enable_hw returned fail\n");

userspace/units/gr/nvgpu-gr.h

@@ -83,8 +83,7 @@ int test_gr_remove_setup(struct unit_module *m, struct gk20a *g, void *args);
  *
  * Test Type: Feature
  *
- * Targets: gops_gr.gr_prepare_sw, nvgpu_gr_prepare_sw,
+ * Targets: gops_gr.gr_enable_hw, nvgpu_gr_enable_hw,
- *          gops_gr.gr_enable_hw, nvgpu_gr_enable_hw,
  *          gops_gr_intr.enable_hww_exceptions,
  *          gv11b_gr_intr_enable_hww_exceptions,
  *          gops_gr_intr.enable_interrupts,
@@ -97,8 +96,8 @@ int test_gr_remove_setup(struct unit_module *m, struct gk20a *g, void *args);
  * Input: test_gr_init_setup must have been executed successfully.
  *
  * Steps:
- * -  Call nvgpu_gr_prepare_sw and nvgpu_gr_enable_hw which helps
+ * -  Call nvgpu_gr_enable_hw which helps to initialize the s/w and
- *    to initialize the s/w and enable h/w for GR engine.
+ *    enable h/w for GR engine.
  *
  * Output: Returns PASS.
  */
@@ -229,7 +228,7 @@ int test_gr_init_ecc_features(struct unit_module *m,
  *
  * Test Type: Feature
  *
- * Targets: nvgpu_gr_prepare_sw, nvgpu_gr_enable_hw,
+ * Targets: nvgpu_gr_enable_hw,
  *          nvgpu_gr_init_support, nvgpu_gr_sw_ready,
  *          gm20b_gr_init_lg_coalesce,
  *          gm20b_gr_init_su_coalesce,
@@ -260,7 +259,7 @@ int test_gr_init_setup_ready(struct unit_module *m,
  * Test Type: Feature, Error Injection
  *
  * Targets: gops_gr.gr_init_support, nvgpu_gr_init_support,
- *          gops_gr.gr_prepare_sw, nvgpu_gr_prepare_sw, gr_remove_support
+ *          gr_remove_support
  *
  * Input: #test_gr_setup_ready must have been executed successfully.
  *
@@ -269,10 +268,6 @@ int test_gr_init_setup_ready(struct unit_module *m,
  *    This includes failing of #nvgpu_gr_falcon_init_ctxsw,
  *    #nvgpu_gr_init_ctx_state,
  *    gr_init_setup_sw and gr_init_setup_hw functions.
- * -  Add various condition to cause failure in #nvgpu_gr_prepare_sw.
- *    This includes failing of #nvgpu_netlist_init_ctx_vars,
- *    #nvgpu_gr_falcon_init_support,
- *    #nvgpu_gr_intr_init_support and g->ops.gr.ecc.fecs_ecc_init functions.
  *
  * Output: Returns PASS if the steps above were executed successfully. FAIL
  * otherwise.

userspace/units/init/nvgpu-init.c

@@ -404,7 +404,6 @@ static void set_poweron_funcs_success(struct gk20a *g)
 	setup_simple_init_func_success(&g->ops.mm.init_mm_support, i++);
 	setup_simple_init_func_success(&g->ops.fifo.fifo_init_support, i++);
 	setup_simple_init_func_success(&g->ops.therm.elcg_init_idle_filters, i++);
-	setup_simple_init_func_success(&g->ops.gr.gr_prepare_sw, i++);
 	setup_simple_init_func_success(&g->ops.gr.gr_enable_hw, i++);
 	setup_simple_init_func_success(&g->ops.fbp.fbp_init_support, i++);
 	setup_simple_init_func_success(&g->ops.gr.gr_init_support, i++);
@@ -804,11 +803,11 @@ struct unit_module_test init_tests[] = {
 	UNIT_TEST(init_can_busy,			test_can_busy,		NULL, 0),
 	UNIT_TEST(init_get_put,				test_get_put,		NULL, 0),
 	UNIT_TEST(init_hal_init,			test_hal_init,		NULL, 0),
-	UNIT_TEST(init_poweron,				test_poweron,		NULL, 0),
+	UNIT_TEST(init_poweron,				test_poweron,		NULL, 2),
-	UNIT_TEST(init_poweron_branches,		test_poweron_branches,	NULL, 0),
+	UNIT_TEST(init_poweron_branches,		test_poweron_branches,	NULL, 2),
 	UNIT_TEST(init_poweroff,			test_poweroff,		NULL, 2),
-	UNIT_TEST(init_check_gpu_state,			test_check_gpu_state,	NULL, 0),
+	UNIT_TEST(init_check_gpu_state,			test_check_gpu_state,	NULL, 2),
-	UNIT_TEST(init_quiesce,				test_quiesce,		NULL, 0),
+	UNIT_TEST(init_quiesce,				test_quiesce,		NULL, 2),
 	UNIT_TEST(init_free_env,			test_free_env,		NULL, 0),
 };
 

userspace/units/ltc/nvgpu-ltc.c

@@ -36,6 +36,7 @@
 #include <nvgpu/ltc.h>
 #include <nvgpu/nvgpu_mem.h>
 #include <nvgpu/ecc.h>
+#include <nvgpu/netlist.h>
 #include <nvgpu/gr/gr.h>
 #include <hal/ltc/intr/ltc_intr_gv11b.h>
 
@@ -250,6 +251,16 @@ int test_ltc_ecc_init_free(struct unit_module *m, struct gk20a *g, void *args)
 	struct nvgpu_posix_fault_inj *kmem_fi =
 			nvgpu_kmem_get_fault_injection();
 
+	err = g->ops.ecc.ecc_init_support(g);
+	if (err != 0) {
+		unit_return_fail(m, "ecc init failed\n");
+	}
+
+	err = nvgpu_netlist_init_ctx_vars(g);
+	if (err != 0) {
+		unit_return_fail(m, "netlist init failed\n");
+	}
+
 	err = nvgpu_gr_alloc(g);
 	if (err != 0) {
 		unit_return_fail(m, "failed to init gr\n");

userspace/units/pmu/nvgpu-pmu.c

@@ -28,6 +28,7 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/falcon.h>
 #include <nvgpu/hal_init.h>
+#include <nvgpu/netlist.h>
 
 #include <nvgpu/gr/gr.h>
 
@@ -197,6 +198,16 @@ static int init_pmu_falcon_test_env(struct unit_module *m, struct gk20a *g)
 		return -ENODEV;
 	}
 
+	err = g->ops.ecc.ecc_init_support(g);
+	if (err != 0) {
+		unit_return_fail(m, "ecc init failed\n");
+	}
+
+	err = nvgpu_netlist_init_ctx_vars(g);
+	if (err != 0) {
+		unit_return_fail(m, "netlist init failed\n");
+	}
+
 	nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
 
 	err = nvgpu_gr_alloc(g);