diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 84cb31a3e..3773d4fc8 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -74,7 +74,6 @@ nvgpu-y += common/bus/bus_gk20a.o \ common/netlist/netlist.o \ common/netlist/netlist_sim.o \ common/netlist/netlist_gm20b.o \ - common/netlist/netlist_gp106.o \ common/netlist/netlist_gp10b.o \ common/netlist/netlist_gv100.o \ common/netlist/netlist_gv11b.o \ @@ -87,7 +86,6 @@ nvgpu-y += \ os/linux/os_ops.o \ os/linux/os_ops_gm20b.o \ os/linux/os_ops_gp10b.o \ - os/linux/os_ops_gp106.o \ os/linux/os_ops_gv100.o \ os/linux/os_ops_gv11b.o \ os/linux/kmem.o \ @@ -334,12 +332,9 @@ nvgpu-y += \ gp10b/fecs_trace_gp10b.o \ gp10b/gp10b.o \ gp10b/ecc_gp10b.o \ - gp106/hal_gp106.o \ gp106/mclk_gp106.o \ gp106/gr_gp106.o \ gp106/sec2_gp106.o \ - gp106/fifo_gp106.o \ - gp106/regops_gp106.o \ gp106/bios_gp106.o \ gv11b/gv11b.o \ gv11b/hal_gv11b.o \ @@ -385,7 +380,6 @@ nvgpu-y += \ pmu_perf/change_seq.o \ clk/clk.o \ gp106/clk_gp106.o \ - gp106/clk_arb_gp106.o \ pmgr/pwrdev.o \ pmgr/pmgr.o \ pmgr/pmgrpmu.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 96f4e1ab3..954489fb7 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -112,7 +112,6 @@ srcs := os/posix/nvgpu.c \ common/netlist/netlist.c \ common/netlist/netlist_sim.c \ common/netlist/netlist_gm20b.c \ - common/netlist/netlist_gp106.c \ common/netlist/netlist_gp10b.c \ common/netlist/netlist_gv100.c \ common/netlist/netlist_gv11b.c \ @@ -221,15 +220,11 @@ srcs := os/posix/nvgpu.c \ gv11b/subctx_gv11b.c \ gv11b/regops_gv11b.c \ gv11b/ecc_gv11b.c \ - gp106/hal_gp106.c \ gp106/mclk_gp106.c \ gp106/gr_gp106.c \ gp106/sec2_gp106.c \ - gp106/fifo_gp106.c \ - gp106/regops_gp106.c \ gp106/bios_gp106.c \ gp106/clk_gp106.c \ - gp106/clk_arb_gp106.c \ gv100/mm_gv100.c \ gv100/bios_gv100.c \ gv100/fifo_gv100.c \ diff --git a/drivers/gpu/nvgpu/common/init/hal_init.c b/drivers/gpu/nvgpu/common/init/hal_init.c index a60fc839f..b963ba70b 100644 --- a/drivers/gpu/nvgpu/common/init/hal_init.c +++ b/drivers/gpu/nvgpu/common/init/hal_init.c @@ -30,7 +30,6 @@ #include "gm20b/hal_gm20b.h" #include "gp10b/hal_gp10b.h" -#include "gp106/hal_gp106.h" #include "gv100/hal_gv100.h" #include "gv11b/hal_gv11b.h" #include "tu104/hal_tu104.h" @@ -58,16 +57,6 @@ int nvgpu_init_hal(struct gk20a *g) return -ENODEV; } break; - case NVGPU_GPUID_GP104: - if (gp106_init_hal(g) != 0) { - return -ENODEV; - } - break; - case NVGPU_GPUID_GP106: - if (gp106_init_hal(g) != 0) { - return -ENODEV; - } - break; case NVGPU_GPUID_GV11B: if (gv11b_init_hal(g) != 0) { return -ENODEV; diff --git a/drivers/gpu/nvgpu/common/netlist/netlist_gp106.c b/drivers/gpu/nvgpu/common/netlist/netlist_gp106.c deleted file mode 100644 index df2c2033e..000000000 --- a/drivers/gpu/nvgpu/common/netlist/netlist_gp106.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include "netlist_gp106.h" - -int gp106_netlist_get_name(struct gk20a *g, int index, char *name) -{ - u32 ver = g->params.gpu_arch + g->params.gpu_impl; - - switch (ver) { - case NVGPU_GPUID_GP104: - (void) sprintf(name, "%s/%s", "gp104", - GP104_NETLIST_IMAGE_FW_NAME); - break; - case NVGPU_GPUID_GP106: - (void) sprintf(name, "%s/%s", "gp106", - GP106_NETLIST_IMAGE_FW_NAME); - break; - default: - nvgpu_err(g, "no support for GPUID %x", ver); - } - - return 0; -} - -bool gp106_netlist_is_firmware_defined(void) -{ - return true; -} diff --git a/drivers/gpu/nvgpu/common/netlist/netlist_gp106.h b/drivers/gpu/nvgpu/common/netlist/netlist_gp106.h deleted file mode 100644 index 59d222c23..000000000 --- a/drivers/gpu/nvgpu/common/netlist/netlist_gp106.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_NETLIST_GP106_H -#define NVGPU_NETLIST_GP106_H - -#include - -/* production netlist, one and only one from below */ -#define GP106_NETLIST_IMAGE_FW_NAME NVGPU_NETLIST_IMAGE_C -#define GP104_NETLIST_IMAGE_FW_NAME NVGPU_NETLIST_IMAGE_D - -int gp106_netlist_get_name(struct gk20a *g, int index, char *name); -bool gp106_netlist_is_firmware_defined(void); - -#endif /* NVGPU_NETLIST_GP106_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gp106.c b/drivers/gpu/nvgpu/common/pmu/acr_gp106.c index efd418d57..fd0468d1d 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/acr_gp106.c @@ -194,16 +194,6 @@ int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) int err; switch (ver) { - case NVGPU_GPUID_GP104: - fecs_sig = nvgpu_request_firmware(g, - GP104_FECS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); - break; - case NVGPU_GPUID_GP106: - fecs_sig = nvgpu_request_firmware(g, - GP106_FECS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); - break; case NVGPU_GPUID_GV11B: fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, 0); @@ -296,16 +286,6 @@ int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) } switch (ver) { - case NVGPU_GPUID_GP104: - gpccs_sig = nvgpu_request_firmware(g, - GP104_GPCCS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); - break; - case NVGPU_GPUID_GP106: - gpccs_sig = nvgpu_request_firmware(g, - GP106_GPCCS_UCODE_SIG, - NVGPU_REQUEST_FIRMWARE_NO_SOC); - break; case NVGPU_GPUID_GV11B: gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gp106.h b/drivers/gpu/nvgpu/common/pmu/acr_gp106.h index dcdb40ca0..2b3925cdf 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gp106.h +++ b/drivers/gpu/nvgpu/common/pmu/acr_gp106.h @@ -23,12 +23,6 @@ #ifndef NVGPU_ACR_GP106_H #define NVGPU_ACR_GP106_H -#define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin" -#define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin" -#define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin" -#define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" - - int gp106_bootstrap_hs_flcn(struct gk20a *g); int gp106_prepare_ucode_blob(struct gk20a *g); int gp106_alloc_blob_space(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index c0e67c621..742d6b426 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c @@ -40,10 +40,6 @@ static u8 get_perfmon_id(struct nvgpu_pmu *pmu) unit_id = PMU_UNIT_PERFMON; break; case NVGPU_GPUID_GP10B: - case NVGPU_GPUID_GP104: - case NVGPU_GPUID_GP106: - unit_id = PMU_UNIT_PERFMON_T18X; - break; case NVGPU_GPUID_GV11B: unit_id = PMU_UNIT_PERFMON_T18X; break; diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c deleted file mode 100644 index 141d2a165..000000000 --- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c +++ /dev/null @@ -1,792 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include "clk_arb_gp106.h" - -u32 gp106_get_arbiter_clk_domains(struct gk20a *g) -{ - (void)g; - return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK); -} - -int gp106_get_arbiter_f_points(struct gk20a *g,u32 api_domain, - u32 *num_points, u16 *freqs_in_mhz) -{ - return g->ops.clk.clk_domain_get_f_points(g, - api_domain, num_points, freqs_in_mhz); -} - -int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, - u16 *min_mhz, u16 *max_mhz) -{ - u32 clkwhich; - struct clk_set_info *p0_info; - struct clk_set_info *p5_info; - struct avfsfllobjs *pfllobjs = &(g->clk_pmu->avfs_fllobjs); - - u16 limit_min_mhz; - - switch (api_domain) { - case CTRL_CLK_DOMAIN_MCLK: - clkwhich = CLKWHICH_MCLK; - break; - - case CTRL_CLK_DOMAIN_GPC2CLK: - clkwhich = CLKWHICH_GPC2CLK; - break; - - default: - return -EINVAL; - } - - p5_info = pstate_get_clk_set_info(g, - CTRL_PERF_PSTATE_P5, clkwhich); - if (p5_info == NULL) { - return -EINVAL; - } - - p0_info = pstate_get_clk_set_info(g, - CTRL_PERF_PSTATE_P0, clkwhich); - if (p0_info == NULL) { - return -EINVAL; - } - - limit_min_mhz = p5_info->min_mhz; - /* WAR for DVCO min */ - if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK) { - if ((pfllobjs->max_min_freq_mhz != 0U) && - (pfllobjs->max_min_freq_mhz >= limit_min_mhz)) { - limit_min_mhz = pfllobjs->max_min_freq_mhz + 1U; - } - } - - *min_mhz = limit_min_mhz; - *max_mhz = p0_info->max_mhz; - - return 0; -} - -int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, - u16 *default_mhz) -{ - u32 clkwhich; - struct clk_set_info *p0_info; - - switch (api_domain) { - case CTRL_CLK_DOMAIN_MCLK: - clkwhich = CLKWHICH_MCLK; - break; - - case CTRL_CLK_DOMAIN_GPC2CLK: - clkwhich = CLKWHICH_GPC2CLK; - break; - - default: - return -EINVAL; - } - - p0_info = pstate_get_clk_set_info(g, - CTRL_PERF_PSTATE_P0, clkwhich); - if (p0_info == NULL) { - return -EINVAL; - } - - *default_mhz = p0_info->max_mhz; - - return 0; -} - -int gp106_init_clk_arbiter(struct gk20a *g) -{ - struct nvgpu_clk_arb *arb; - u16 default_mhz; - int err; - int index; - struct nvgpu_clk_vf_table *table; - - clk_arb_dbg(g, " "); - - if (g->clk_arb != NULL) { - return 0; - } - - arb = nvgpu_kzalloc(g, sizeof(struct nvgpu_clk_arb)); - if (arb == NULL) { - return -ENOMEM; - } - - err = nvgpu_mutex_init(&arb->pstate_lock); - if (err != 0) { - goto mutex_fail; - } - nvgpu_spinlock_init(&arb->sessions_lock); - nvgpu_spinlock_init(&arb->users_lock); - nvgpu_spinlock_init(&arb->requests_lock); - - arb->mclk_f_points = nvgpu_kcalloc(g, MAX_F_POINTS, sizeof(u16)); - if (arb->mclk_f_points == NULL) { - err = -ENOMEM; - goto init_fail; - } - - arb->gpc2clk_f_points = nvgpu_kcalloc(g, MAX_F_POINTS, sizeof(u16)); - if (arb->gpc2clk_f_points == NULL) { - err = -ENOMEM; - goto init_fail; - } - - for (index = 0; index < 2; index++) { - table = &arb->vf_table_pool[index]; - table->gpc2clk_num_points = MAX_F_POINTS; - table->mclk_num_points = MAX_F_POINTS; - - table->gpc2clk_points = nvgpu_kcalloc(g, MAX_F_POINTS, - sizeof(struct nvgpu_clk_vf_point)); - if (table->gpc2clk_points == NULL) { - err = -ENOMEM; - goto init_fail; - } - - - table->mclk_points = nvgpu_kcalloc(g, MAX_F_POINTS, - sizeof(struct nvgpu_clk_vf_point)); - if (table->mclk_points == NULL) { - err = -ENOMEM; - goto init_fail; - } - } - - g->clk_arb = arb; - arb->g = g; - - err = g->ops.clk_arb.get_arbiter_clk_default(g, - CTRL_CLK_DOMAIN_MCLK, &default_mhz); - if (err < 0) { - err = -EINVAL; - goto init_fail; - } - - arb->mclk_default_mhz = default_mhz; - - err = g->ops.clk_arb.get_arbiter_clk_default(g, - CTRL_CLK_DOMAIN_GPC2CLK, &default_mhz); - if (err < 0) { - err = -EINVAL; - goto init_fail; - } - - arb->gpc2clk_default_mhz = default_mhz; - - arb->actual = &arb->actual_pool[0]; - - nvgpu_atomic_set(&arb->req_nr, 0); - - nvgpu_atomic64_set(&arb->alarm_mask, 0); - err = nvgpu_clk_notification_queue_alloc(g, &arb->notification_queue, - DEFAULT_EVENT_NUMBER); - if (err < 0) { - goto init_fail; - } - - nvgpu_init_list_node(&arb->users); - nvgpu_init_list_node(&arb->sessions); - nvgpu_init_list_node(&arb->requests); - - nvgpu_cond_init(&arb->request_wq); - - nvgpu_init_list_node(&arb->update_vf_table_work_item.worker_item); - nvgpu_init_list_node(&arb->update_arb_work_item.worker_item); - arb->update_vf_table_work_item.arb = arb; - arb->update_arb_work_item.arb = arb; - arb->update_vf_table_work_item.item_type = CLK_ARB_WORK_UPDATE_VF_TABLE; - arb->update_arb_work_item.item_type = CLK_ARB_WORK_UPDATE_ARB; - - err = nvgpu_clk_arb_worker_init(g); - if (err < 0) { - goto init_fail; - } - -#ifdef CONFIG_DEBUG_FS - arb->debug = &arb->debug_pool[0]; - - if (!arb->debugfs_set) { - if (nvgpu_clk_arb_debugfs_init(g)) - arb->debugfs_set = true; - } -#endif - err = clk_vf_point_cache(g); - if (err < 0) { - goto init_fail; - } - - err = nvgpu_clk_arb_update_vf_table(arb); - if (err < 0) { - goto init_fail; - } - do { - /* Check that first run is completed */ - nvgpu_smp_mb(); - NVGPU_COND_WAIT_INTERRUPTIBLE(&arb->request_wq, - nvgpu_atomic_read(&arb->req_nr), 0); - } while (nvgpu_atomic_read(&arb->req_nr) == 0); - - - return arb->status; - -init_fail: - nvgpu_kfree(g, arb->gpc2clk_f_points); - nvgpu_kfree(g, arb->mclk_f_points); - - for (index = 0; index < 2; index++) { - nvgpu_kfree(g, arb->vf_table_pool[index].gpc2clk_points); - nvgpu_kfree(g, arb->vf_table_pool[index].mclk_points); - } - - nvgpu_mutex_destroy(&arb->pstate_lock); - -mutex_fail: - nvgpu_kfree(g, arb); - - return err; -} - -static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb, - u16 *gpc2clk, u16 *sys2clk, u16 *xbar2clk, u16 *mclk, - u32 *voltuv, u32 *voltuv_sram, u32 *nuvmin, u32 *nuvmin_sram) -{ - u16 gpc2clk_target, mclk_target; - u32 gpc2clk_voltuv, gpc2clk_voltuv_sram; - u32 mclk_voltuv, mclk_voltuv_sram; - u32 pstate = VF_POINT_INVALID_PSTATE; - struct nvgpu_clk_vf_table *table; - u32 index, index_mclk; - struct nvgpu_clk_vf_point *mclk_vf = NULL; - - do { - gpc2clk_target = *gpc2clk; - mclk_target = *mclk; - gpc2clk_voltuv = 0; - gpc2clk_voltuv_sram = 0; - mclk_voltuv = 0; - mclk_voltuv_sram = 0; - - table = NV_ACCESS_ONCE(arb->current_vf_table); - /* pointer to table can be updated by callback */ - nvgpu_smp_rmb(); - - if (table == NULL) { - continue; - } - if ((table->gpc2clk_num_points == 0U) || - (table->mclk_num_points == 0U)) { - nvgpu_err(arb->g, "found empty table"); - goto find_exit; - } - /* First we check MCLK to find out which PSTATE we are - * are requesting, and from there try to find the minimum - * GPC2CLK on the same PSTATE that satisfies the request. - * If no GPC2CLK can be found, then we need to up the PSTATE - */ - -recalculate_vf_point: - for (index = 0; index < table->mclk_num_points; index++) { - if (table->mclk_points[index].mem_mhz >= mclk_target) { - mclk_vf = &table->mclk_points[index]; - break; - } - } - if (index == table->mclk_num_points) { - mclk_vf = &table->mclk_points[index-1U]; - index = table->mclk_num_points - 1U; - } - index_mclk = index; - - /* round up the freq requests */ - for (index = 0; index < table->gpc2clk_num_points; index++) { - pstate = VF_POINT_COMMON_PSTATE( - &table->gpc2clk_points[index], mclk_vf); - - if ((table->gpc2clk_points[index].gpc_mhz >= - gpc2clk_target) && - (pstate != VF_POINT_INVALID_PSTATE)) { - gpc2clk_target = - table->gpc2clk_points[index].gpc_mhz; - *sys2clk = - table->gpc2clk_points[index].sys_mhz; - *xbar2clk = - table->gpc2clk_points[index].xbar_mhz; - - gpc2clk_voltuv = - table->gpc2clk_points[index].uvolt; - gpc2clk_voltuv_sram = - table->gpc2clk_points[index].uvolt_sram; - break; - } - } - - if (index == table->gpc2clk_num_points) { - pstate = VF_POINT_COMMON_PSTATE( - &table->gpc2clk_points[index-1U], mclk_vf); - if (pstate != VF_POINT_INVALID_PSTATE) { - gpc2clk_target = - table->gpc2clk_points[index-1U].gpc_mhz; - *sys2clk = - table->gpc2clk_points[index-1U].sys_mhz; - *xbar2clk = - table->gpc2clk_points[index-1U].xbar_mhz; - - gpc2clk_voltuv = - table->gpc2clk_points[index-1U].uvolt; - gpc2clk_voltuv_sram = - table->gpc2clk_points[index-1U]. - uvolt_sram; - } else if (index_mclk >= table->mclk_num_points - 1U) { - /* There is no available combination of MCLK - * and GPC2CLK, we need to fail this - */ - gpc2clk_target = 0; - mclk_target = 0; - pstate = VF_POINT_INVALID_PSTATE; - goto find_exit; - } else { - /* recalculate with higher PSTATE */ - gpc2clk_target = *gpc2clk; - mclk_target = table->mclk_points[index_mclk+1U]. - mem_mhz; - goto recalculate_vf_point; - } - } - - mclk_target = mclk_vf->mem_mhz; - mclk_voltuv = mclk_vf->uvolt; - mclk_voltuv_sram = mclk_vf->uvolt_sram; - - } while ((table == NULL) || - (NV_ACCESS_ONCE(arb->current_vf_table) != table)); - -find_exit: - *voltuv = gpc2clk_voltuv > mclk_voltuv ? gpc2clk_voltuv : mclk_voltuv; - *voltuv_sram = gpc2clk_voltuv_sram > mclk_voltuv_sram ? - gpc2clk_voltuv_sram : mclk_voltuv_sram; - /* noise unaware vmin */ - *nuvmin = mclk_voltuv; - *nuvmin_sram = mclk_voltuv_sram; - *gpc2clk = gpc2clk_target < *gpc2clk ? gpc2clk_target : *gpc2clk; - *mclk = mclk_target; - return pstate; -} - -static int nvgpu_clk_arb_change_vf_point(struct gk20a *g, u16 gpc2clk_target, - u16 sys2clk_target, u16 xbar2clk_target, u16 mclk_target, u32 voltuv, - u32 voltuv_sram) -{ - struct set_fll_clk fllclk; - struct nvgpu_clk_arb *arb = g->clk_arb; - int status; - - fllclk.gpc2clkmhz = gpc2clk_target; - fllclk.sys2clkmhz = sys2clk_target; - fllclk.xbar2clkmhz = xbar2clk_target; - - fllclk.voltuv = voltuv; - - /* if voltage ascends we do: - * (1) FLL change - * (2) Voltage change - * (3) MCLK change - * If it goes down - * (1) MCLK change - * (2) Voltage change - * (3) FLL change - */ - - /* descending */ - if (voltuv < arb->voltuv_actual) { - status = g->ops.clk.mclk_change(g, mclk_target); - if (status < 0) { - return status; - } - - status = volt_set_voltage(g, voltuv, voltuv_sram); - if (status < 0) { - return status; - } - - status = clk_set_fll_clks(g, &fllclk); - if (status < 0) { - return status; - } - } else { - status = clk_set_fll_clks(g, &fllclk); - if (status < 0) { - return status; - } - - status = volt_set_voltage(g, voltuv, voltuv_sram); - if (status < 0) { - return status; - } - - status = g->ops.clk.mclk_change(g, mclk_target); - if (status < 0) { - return status; - } - } - - return 0; -} - -void gp106_clk_arb_run_arbiter_cb(struct nvgpu_clk_arb *arb) -{ - struct nvgpu_clk_session *session; - struct nvgpu_clk_dev *dev; - struct nvgpu_clk_dev *tmp; - struct nvgpu_clk_arb_target *target, *actual; - struct gk20a *g = arb->g; - - u32 pstate = VF_POINT_INVALID_PSTATE; - u32 voltuv, voltuv_sram; - bool mclk_set, gpc2clk_set; - u32 nuvmin, nuvmin_sram; - - u32 alarms_notified = 0; - u32 current_alarm; - int status = 0; - - /* Temporary variables for checking target frequency */ - u16 gpc2clk_target, sys2clk_target, xbar2clk_target, mclk_target; - u16 gpc2clk_session_target, mclk_session_target; - -#ifdef CONFIG_DEBUG_FS - u64 t0, t1; - struct nvgpu_clk_arb_debug *debug; - -#endif - - clk_arb_dbg(g, " "); - - /* bail out if gpu is down */ - if ((unsigned long)nvgpu_atomic64_read(&arb->alarm_mask) & - EVENT(ALARM_GPU_LOST)) { - goto exit_arb; - } - -#ifdef CONFIG_DEBUG_FS - g->ops.ptimer.read_ptimer(g, &t0); -#endif - - /* Only one arbiter should be running */ - gpc2clk_target = 0; - mclk_target = 0; - - nvgpu_spinlock_acquire(&arb->sessions_lock); - nvgpu_list_for_each_entry(session, &arb->sessions, - nvgpu_clk_session, link) { - if (!session->zombie) { - mclk_set = false; - gpc2clk_set = false; - target = (session->target == &session->target_pool[0] ? - &session->target_pool[1] : - &session->target_pool[0]); - nvgpu_spinlock_acquire(&session->session_lock); - if (!nvgpu_list_empty(&session->targets)) { - /* Copy over state */ - target->mclk = session->target->mclk; - target->gpc2clk = session->target->gpc2clk; - /* Query the latest committed request */ - nvgpu_list_for_each_entry_safe(dev, tmp, - &session->targets, nvgpu_clk_dev, node) { - if (!mclk_set && - (dev->mclk_target_mhz != 0U)) { - target->mclk = - dev->mclk_target_mhz; - mclk_set = true; - } - if (!gpc2clk_set && - (dev->gpc2clk_target_mhz != 0U)) { - target->gpc2clk = - dev->gpc2clk_target_mhz; - gpc2clk_set = true; - } - nvgpu_ref_get(&dev->refcount); - nvgpu_list_del(&dev->node); - nvgpu_spinlock_acquire( - &arb->requests_lock); - nvgpu_list_add( - &dev->node, &arb->requests); - nvgpu_spinlock_release(&arb->requests_lock); - } - session->target = target; - } - nvgpu_spinlock_release( - &session->session_lock); - - mclk_target = mclk_target > session->target->mclk ? - mclk_target : session->target->mclk; - - gpc2clk_target = - gpc2clk_target > session->target->gpc2clk ? - gpc2clk_target : session->target->gpc2clk; - } - } - nvgpu_spinlock_release(&arb->sessions_lock); - - gpc2clk_target = (gpc2clk_target > 0U) ? gpc2clk_target : - arb->gpc2clk_default_mhz; - - if (gpc2clk_target < arb->gpc2clk_min) { - gpc2clk_target = arb->gpc2clk_min; - } - - if (gpc2clk_target > arb->gpc2clk_max) { - gpc2clk_target = arb->gpc2clk_max; - } - - mclk_target = (mclk_target > 0U) ? mclk_target : - arb->mclk_default_mhz; - - if (mclk_target < arb->mclk_min) { - mclk_target = arb->mclk_min; - } - - if (mclk_target > arb->mclk_max) { - mclk_target = arb->mclk_max; - } - - sys2clk_target = 0; - xbar2clk_target = 0; - - gpc2clk_session_target = gpc2clk_target; - mclk_session_target = mclk_target; - - /* Query the table for the closest vf point to program */ - pstate = nvgpu_clk_arb_find_vf_point(arb, &gpc2clk_target, - &sys2clk_target, &xbar2clk_target, &mclk_target, &voltuv, - &voltuv_sram, &nuvmin, &nuvmin_sram); - - if (pstate == VF_POINT_INVALID_PSTATE) { - arb->status = -EINVAL; - /* make status visible */ - nvgpu_smp_mb(); - goto exit_arb; - } - - if ((gpc2clk_target < gpc2clk_session_target) || - (mclk_target < mclk_session_target)) { - nvgpu_clk_arb_set_global_alarm(g, - EVENT(ALARM_TARGET_VF_NOT_POSSIBLE)); - } - - if ((arb->actual->gpc2clk == gpc2clk_target) && - (arb->actual->mclk == mclk_target) && - (arb->voltuv_actual == voltuv)) { - goto exit_arb; - } - - /* Program clocks */ - /* A change in both mclk of gpc2clk may require a change in voltage */ - - nvgpu_mutex_acquire(&arb->pstate_lock); - status = nvgpu_lpwr_disable_pg(g, false); - - status = clk_pmu_freq_controller_load(g, false, - CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL); - if (status < 0) { - arb->status = status; - nvgpu_mutex_release(&arb->pstate_lock); - - /* make status visible */ - nvgpu_smp_mb(); - goto exit_arb; - } - status = volt_set_noiseaware_vmin(g, nuvmin, nuvmin_sram); - if (status < 0) { - arb->status = status; - nvgpu_mutex_release(&arb->pstate_lock); - - /* make status visible */ - nvgpu_smp_mb(); - goto exit_arb; - } - - status = nvgpu_clk_arb_change_vf_point(g, gpc2clk_target, - sys2clk_target, xbar2clk_target, mclk_target, voltuv, - voltuv_sram); - if (status < 0) { - arb->status = status; - nvgpu_mutex_release(&arb->pstate_lock); - - /* make status visible */ - nvgpu_smp_mb(); - goto exit_arb; - } - - status = clk_pmu_freq_controller_load(g, true, - CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL); - if (status < 0) { - arb->status = status; - nvgpu_mutex_release(&arb->pstate_lock); - - /* make status visible */ - nvgpu_smp_mb(); - goto exit_arb; - } - - status = nvgpu_lwpr_mclk_change(g, pstate); - if (status < 0) { - arb->status = status; - nvgpu_mutex_release(&arb->pstate_lock); - - /* make status visible */ - nvgpu_smp_mb(); - goto exit_arb; - } - - actual = NV_ACCESS_ONCE(arb->actual) == &arb->actual_pool[0] ? - &arb->actual_pool[1] : &arb->actual_pool[0]; - - /* do not reorder this pointer */ - nvgpu_smp_rmb(); - actual->gpc2clk = gpc2clk_target; - actual->mclk = mclk_target; - arb->voltuv_actual = voltuv; - actual->pstate = pstate; - arb->status = status; - - /* Make changes visible to other threads */ - nvgpu_smp_wmb(); - arb->actual = actual; - - status = nvgpu_lpwr_enable_pg(g, false); - if (status < 0) { - arb->status = status; - nvgpu_mutex_release(&arb->pstate_lock); - - /* make status visible */ - nvgpu_smp_mb(); - goto exit_arb; - } - - /* status must be visible before atomic inc */ - nvgpu_smp_wmb(); - nvgpu_atomic_inc(&arb->req_nr); - - /* Unlock pstate change for PG */ - nvgpu_mutex_release(&arb->pstate_lock); - - /* VF Update complete */ - nvgpu_clk_arb_set_global_alarm(g, EVENT(VF_UPDATE)); - - nvgpu_cond_signal_interruptible(&arb->request_wq); - -#ifdef CONFIG_DEBUG_FS - g->ops.ptimer.read_ptimer(g, &t1); - - debug = arb->debug == &arb->debug_pool[0] ? - &arb->debug_pool[1] : &arb->debug_pool[0]; - - nvgpu_memcpy((u8 *)debug, (u8 *)arb->debug, sizeof(arb->debug_pool[0])); - debug->switch_num++; - - if (debug->switch_num == 1) { - debug->switch_max = debug->switch_min = - debug->switch_avg = (t1-t0)/1000; - debug->switch_std = 0; - } else { - s64 prev_avg; - s64 curr = (t1-t0)/1000; - - debug->switch_max = curr > debug->switch_max ? - curr : debug->switch_max; - debug->switch_min = debug->switch_min ? - (curr < debug->switch_min ? - curr : debug->switch_min) : curr; - prev_avg = debug->switch_avg; - debug->switch_avg = (curr + - (debug->switch_avg * (debug->switch_num-1))) / - debug->switch_num; - debug->switch_std += - (curr - debug->switch_avg) * (curr - prev_avg); - } - /* commit changes before exchanging debug pointer */ - nvgpu_smp_wmb(); - arb->debug = debug; -#endif - -exit_arb: - if (status < 0) { - nvgpu_err(g, "Error in arbiter update"); - nvgpu_clk_arb_set_global_alarm(g, - EVENT(ALARM_CLOCK_ARBITER_FAILED)); - } - - current_alarm = (u32) nvgpu_atomic64_read(&arb->alarm_mask); - /* notify completion for all requests */ - nvgpu_spinlock_acquire(&arb->requests_lock); - nvgpu_list_for_each_entry_safe(dev, tmp, &arb->requests, - nvgpu_clk_dev, node) { - nvgpu_atomic_set(&dev->poll_mask, - NVGPU_POLLIN | NVGPU_POLLRDNORM); - nvgpu_clk_arb_event_post_event(dev); - nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); - nvgpu_list_del(&dev->node); - } - nvgpu_spinlock_release(&arb->requests_lock); - - nvgpu_atomic_set(&arb->notification_queue.head, - nvgpu_atomic_read(&arb->notification_queue.tail)); - /* notify event for all users */ - nvgpu_spinlock_acquire(&arb->users_lock); - nvgpu_list_for_each_entry(dev, &arb->users, nvgpu_clk_dev, link) { - alarms_notified |= - nvgpu_clk_arb_notify(dev, arb->actual, current_alarm); - } - nvgpu_spinlock_release(&arb->users_lock); - - /* clear alarms */ - nvgpu_clk_arb_clear_global_alarm(g, alarms_notified & - ~EVENT(ALARM_GPU_LOST)); -} - -void gp106_clk_arb_cleanup(struct nvgpu_clk_arb *arb) -{ - struct gk20a *g = arb->g; - int index; - - nvgpu_kfree(g, arb->gpc2clk_f_points); - nvgpu_kfree(g, arb->mclk_f_points); - - for (index = 0; index < 2; index++) { - nvgpu_kfree(g, - arb->vf_table_pool[index].gpc2clk_points); - nvgpu_kfree(g, arb->vf_table_pool[index].mclk_points); - } - - nvgpu_mutex_destroy(&g->clk_arb->pstate_lock); - nvgpu_kfree(g, g->clk_arb); - - g->clk_arb = NULL; -} diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h deleted file mode 100644 index 4c1257e18..000000000 --- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef CLK_ARB_GP106_H -#define CLK_ARB_GP106_H - -struct nvgpu_clk_session; -struct nvgpu_clk_arb; - -u32 gp106_get_arbiter_clk_domains(struct gk20a *g); -int gp106_get_arbiter_f_points(struct gk20a *g,u32 api_domain, - u32 *num_points, u16 *freqs_in_mhz); -int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, - u16 *min_mhz, u16 *max_mhz); -int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, - u16 *default_mhz); -int gp106_init_clk_arbiter(struct gk20a *g); -void gp106_clk_arb_run_arbiter_cb(struct nvgpu_clk_arb *arb); -void gp106_clk_arb_cleanup(struct nvgpu_clk_arb *arb); - -#endif /* CLK_ARB_GP106_H */ diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.c b/drivers/gpu/nvgpu/gp106/fifo_gp106.c deleted file mode 100644 index 841238a92..000000000 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include - -#include "gp10b/fifo_gp10b.h" - -#include "fifo_gp106.h" - -#include -#include - -u32 gp106_fifo_get_num_fifos(struct gk20a *g) -{ - return ccsr_channel__size_1_v(); -} - -static const char * const gp106_hub_client_descs[] = { - "vip", "ce0", "ce1", "dniso", "fe", "fecs", "host", "host cpu", - "host cpu nb", "iso", "mmu", "mspdec", "msppp", "msvld", - "niso", "p2p", "pd", "perf", "pmu", "raster twod", "scc", - "scc nb", "sec", "ssync", "gr copy", "xv", "mmu nb", - "msenc", "d falcon", "sked", "a falcon", "n/a", - "hsce0", "hsce1", "hsce2", "hsce3", "hsce4", "hsce5", - "hsce6", "hsce7", "hsce8", "hsce9", "hshub", - "ptp x0", "ptp x1", "ptp x2", "ptp x3", "ptp x4", - "ptp x5", "ptp x6", "ptp x7", "vpr scrubber0", "vpr scrubber1", - "dwbif", "fbfalcon", -}; - -static const char * const gp106_gpc_client_descs[] = { - "l1 0", "t1 0", "pe 0", - "l1 1", "t1 1", "pe 1", - "l1 2", "t1 2", "pe 2", - "l1 3", "t1 3", "pe 3", - "rast", "gcc", "gpccs", - "prop 0", "prop 1", "prop 2", "prop 3", - "l1 4", "t1 4", "pe 4", - "l1 5", "t1 5", "pe 5", - "l1 6", "t1 6", "pe 6", - "l1 7", "t1 7", "pe 7", - "l1 9", "t1 9", "pe 9", - "l1 10", "t1 10", "pe 10", - "l1 11", "t1 11", "pe 11", - "unknown", "unknown", "unknown", "unknown", - "tpccs 0", "tpccs 1", "tpccs 2", - "tpccs 3", "tpccs 4", "tpccs 5", - "tpccs 6", "tpccs 7", "tpccs 8", - "tpccs 9", "tpccs 10", "tpccs 11", - "tpccs 12", "tpccs 13", "tpccs 14", - "tpccs 15", "tpccs 16", "tpccs 17", - "tpccs 18", "tpccs 19", "unknown", "unknown", - "unknown", "unknown", "unknown", "unknown", - "unknown", "unknown", "unknown", "unknown", - "unknown", "unknown", - "l1 12", "t1 12", "pe 12", - "l1 13", "t1 13", "pe 13", - "l1 14", "t1 14", "pe 14", - "l1 15", "t1 15", "pe 15", - "l1 16", "t1 16", "pe 16", - "l1 17", "t1 17", "pe 17", - "l1 18", "t1 18", "pe 18", - "l1 19", "t1 19", "pe 19", -}; - -void gp106_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault) -{ - if (mmfault->client_id >= ARRAY_SIZE(gp106_gpc_client_descs)) { - WARN_ON(mmfault->client_id >= - ARRAY_SIZE(gp106_gpc_client_descs)); - } else { - mmfault->client_id_desc = - gp106_gpc_client_descs[mmfault->client_id]; - } -} - -/* fill in mmu fault client description */ -void gp106_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault) -{ - if (mmfault->client_id >= ARRAY_SIZE(gp106_hub_client_descs)) { - WARN_ON(mmfault->client_id >= - ARRAY_SIZE(gp106_hub_client_descs)); - } else { - mmfault->client_id_desc = - gp106_hub_client_descs[mmfault->client_id]; - } -} diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.h b/drivers/gpu/nvgpu/gp106/fifo_gp106.h deleted file mode 100644 index a6436a1bd..000000000 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_FIFO_GP106_H -#define NVGPU_FIFO_GP106_H -struct gk20a; -struct mmu_fault_info; - -u32 gp106_fifo_get_num_fifos(struct gk20a *g); -void gp106_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault); -void gp106_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); -#endif diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c deleted file mode 100644 index 06c00602c..000000000 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ /dev/null @@ -1,1020 +0,0 @@ -/* - * GP106 HAL interface - * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "common/bus/bus_gk20a.h" -#include "common/clock_gating/gp106_gating_reglist.h" -#include "common/ptimer/ptimer_gk20a.h" -#include "common/bus/bus_gm20b.h" -#include "common/bus/bus_gp10b.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" -#include "common/fb/fb_gp10b.h" -#include "common/fb/fb_gm20b.h" -#include "common/fb/fb_gp106.h" -#include "common/netlist/netlist_gp106.h" -#include "common/gr/ctxsw_prog/ctxsw_prog_gm20b.h" -#include "common/gr/ctxsw_prog/ctxsw_prog_gp10b.h" -#include "common/xve/xve_gp106.h" -#include "common/therm/therm_gm20b.h" -#include "common/therm/therm_gp106.h" -#include "common/ltc/ltc_gm20b.h" -#include "common/ltc/ltc_gp10b.h" -#include "common/fuse/fuse_gm20b.h" -#include "common/fuse/fuse_gp10b.h" -#include "common/fuse/fuse_gp106.h" -#include "common/mc/mc_gm20b.h" -#include "common/mc/mc_gp10b.h" -#include "common/perf/perf_gm20b.h" -#include "common/pmu/pmu_gk20a.h" -#include "common/pmu/pmu_gm20b.h" -#include "common/pmu/pmu_gp10b.h" -#include "common/pmu/pmu_gp106.h" -#include "common/pmu/acr_gm20b.h" -#include "common/pmu/acr_gp106.h" -#include "common/falcon/falcon_gk20a.h" -#include "common/falcon/falcon_gp106.h" -#include "common/nvdec/nvdec_gp106.h" -#include "pmu_perf/pmu_perf.h" - -#include "gk20a/fifo_gk20a.h" -#include "gk20a/fecs_trace_gk20a.h" -#include "gk20a/mm_gk20a.h" -#include "gk20a/regops_gk20a.h" -#include "gk20a/gr_gk20a.h" - -#include "gp10b/gr_gp10b.h" -#include "gp10b/fecs_trace_gp10b.h" -#include "gp10b/mm_gp10b.h" -#include "gp10b/ce_gp10b.h" -#include "gp10b/regops_gp10b.h" -#include "gp10b/fifo_gp10b.h" -#include "gp10b/gr_gp10b.h" - -#include "gp106/fifo_gp106.h" -#include "gp106/regops_gp106.h" - -#include "gm20b/gr_gm20b.h" -#include "gm20b/fifo_gm20b.h" -#include "gm20b/mm_gm20b.h" -#include "gm20b/gr_gm20b.h" - -#include "gp106/sec2_gp106.h" -#include "gp106/clk_gp106.h" -#include "gp106/clk_arb_gp106.h" -#include "gp106/mclk_gp106.h" -#include "gp106/bios_gp106.h" -#include "gp106/fifo_gp106.h" -#include "gp106/clk_gp106.h" -#include "gp106/gr_gp106.h" - -#include "hal_gp106.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - - -static u32 gp106_get_litter_value(struct gk20a *g, int value) -{ - u32 ret = 0; - - switch (value) { - case GPU_LIT_NUM_GPCS: - ret = proj_scal_litter_num_gpcs_v(); - break; - case GPU_LIT_NUM_PES_PER_GPC: - ret = proj_scal_litter_num_pes_per_gpc_v(); - break; - case GPU_LIT_NUM_SM_PER_TPC: - ret = proj_scal_litter_num_sm_per_tpc_v(); - break; - case GPU_LIT_NUM_ZCULL_BANKS: - ret = proj_scal_litter_num_zcull_banks_v(); - break; - case GPU_LIT_NUM_TPC_PER_GPC: - ret = proj_scal_litter_num_tpc_per_gpc_v(); - break; - case GPU_LIT_NUM_FBPS: - ret = proj_scal_litter_num_fbps_v(); - break; - case GPU_LIT_GPC_BASE: - ret = proj_gpc_base_v(); - break; - case GPU_LIT_GPC_STRIDE: - ret = proj_gpc_stride_v(); - break; - case GPU_LIT_GPC_SHARED_BASE: - ret = proj_gpc_shared_base_v(); - break; - case GPU_LIT_TPC_IN_GPC_BASE: - ret = proj_tpc_in_gpc_base_v(); - break; - case GPU_LIT_TPC_IN_GPC_STRIDE: - ret = proj_tpc_in_gpc_stride_v(); - break; - case GPU_LIT_TPC_IN_GPC_SHARED_BASE: - ret = proj_tpc_in_gpc_shared_base_v(); - break; - case GPU_LIT_PPC_IN_GPC_BASE: - ret = proj_ppc_in_gpc_base_v(); - break; - case GPU_LIT_PPC_IN_GPC_STRIDE: - ret = proj_ppc_in_gpc_stride_v(); - break; - case GPU_LIT_PPC_IN_GPC_SHARED_BASE: - ret = proj_ppc_in_gpc_shared_base_v(); - break; - case GPU_LIT_ROP_BASE: - ret = proj_rop_base_v(); - break; - case GPU_LIT_ROP_STRIDE: - ret = proj_rop_stride_v(); - break; - case GPU_LIT_ROP_SHARED_BASE: - ret = proj_rop_shared_base_v(); - break; - case GPU_LIT_HOST_NUM_ENGINES: - ret = proj_host_num_engines_v(); - break; - case GPU_LIT_HOST_NUM_PBDMA: - ret = proj_host_num_pbdma_v(); - break; - case GPU_LIT_LTC_STRIDE: - ret = proj_ltc_stride_v(); - break; - case GPU_LIT_LTS_STRIDE: - ret = proj_lts_stride_v(); - break; - case GPU_LIT_NUM_FBPAS: - ret = proj_scal_litter_num_fbpas_v(); - break; - case GPU_LIT_FBPA_SHARED_BASE: - ret = proj_fbpa_shared_base_v(); - break; - case GPU_LIT_FBPA_BASE: - ret = proj_fbpa_base_v(); - break; - case GPU_LIT_FBPA_STRIDE: - ret = proj_fbpa_stride_v(); - break; - case GPU_LIT_TWOD_CLASS: - ret = FERMI_TWOD_A; - break; - case GPU_LIT_THREED_CLASS: - ret = PASCAL_B; - break; - case GPU_LIT_COMPUTE_CLASS: - ret = PASCAL_COMPUTE_B; - break; - case GPU_LIT_GPFIFO_CLASS: - ret = PASCAL_CHANNEL_GPFIFO_A; - break; - case GPU_LIT_I2M_CLASS: - ret = KEPLER_INLINE_TO_MEMORY_B; - break; - case GPU_LIT_DMA_COPY_CLASS: - ret = PASCAL_DMA_COPY_A; - break; - case GPU_LIT_GPC_PRIV_STRIDE: - ret = proj_gpc_priv_stride_v(); - break; - default: - nvgpu_err(g, "Missing definition %d", value); - BUG(); - break; - } - - return ret; -} - -static int gp106_init_gpu_characteristics(struct gk20a *g) -{ - int err; - - err = gk20a_init_gpu_characteristics(g); - if (err != 0) { - return err; - } - - __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE, true); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_CURRENT, true); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_POWER, true); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_DEVICE_EVENTS, true); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT, true); - - return 0; -} - -static const struct gpu_ops gp106_ops = { - .bios = { - .init = gp106_bios_init, - .preos_wait_for_halt = gp106_bios_preos_wait_for_halt, - .devinit = gp106_bios_devinit, - .preos = gp106_bios_preos, - .verify_devinit = NULL, - }, - .ltc = { - .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = NULL, - .init_fs_state = gm20b_ltc_init_fs_state, - .init_comptags = gp10b_ltc_init_comptags, - .cbc_ctrl = gp10b_ltc_cbc_ctrl, - .isr = gp10b_ltc_isr, - .cbc_fix_config = NULL, - .flush = gm20b_flush_ltc, - .set_enabled = gp10b_ltc_set_enabled, - .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr, - .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr, - .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr, - .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr, - .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr, - }, - .ce2 = { - .isr_stall = gp10b_ce_isr, - .isr_nonstall = gp10b_ce_nonstall_isr, - }, - .gr = { - .get_patch_slots = gr_gk20a_get_patch_slots, - .init_gpc_mmu = gr_gm20b_init_gpc_mmu, - .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, - .cb_size_default = gr_gp106_cb_size_default, - .calc_global_ctx_buffer_size = - gr_gp10b_calc_global_ctx_buffer_size, - .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb, - .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, - .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, - .commit_global_pagepool = gr_gp10b_commit_global_pagepool, - .handle_sw_method = gr_gp106_handle_sw_method, - .set_alpha_circular_buffer_size = - gr_gp10b_set_alpha_circular_buffer_size, - .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, - .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, - .is_valid_class = gr_gp106_is_valid_class, - .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, - .is_valid_compute_class = gr_gp10b_is_valid_compute_class, - .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, - .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, - .init_fs_state = gr_gp10b_init_fs_state, - .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, - .fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr, - .gpccs_falcon_base_addr = gr_gp106_gpccs_falcon_base_addr, - .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, - .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, - .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, - .get_gpc_mask = gr_gm20b_get_gpc_mask, - .alloc_obj_ctx = gk20a_alloc_obj_ctx, - .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, - .get_zcull_info = gr_gk20a_get_zcull_info, - .is_tpc_addr = gr_gm20b_is_tpc_addr, - .get_tpc_num = gr_gm20b_get_tpc_num, - .detect_sm_arch = gr_gm20b_detect_sm_arch, - .add_zbc_color = gr_gp10b_add_zbc_color, - .add_zbc_depth = gr_gp10b_add_zbc_depth, - .get_gpcs_swdx_dss_zbc_c_format_reg = - gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg, - .get_gpcs_swdx_dss_zbc_z_format_reg = - gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg, - .zbc_set_table = gk20a_gr_zbc_set_table, - .zbc_query_table = gr_gk20a_query_zbc, - .pmu_save_zbc = gk20a_pmu_save_zbc, - .add_zbc = gr_gk20a_add_zbc, - .pagepool_default_size = gr_gp106_pagepool_default_size, - .init_ctx_state = gr_gp10b_init_ctx_state, - .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, - .free_gr_ctx = gr_gk20a_free_gr_ctx, - .update_ctxsw_preemption_mode = - gr_gp10b_update_ctxsw_preemption_mode, - .dump_gr_regs = gr_gp10b_dump_gr_status_regs, - .update_pc_sampling = gr_gm20b_update_pc_sampling, - .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, - .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, - .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, - .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, - .get_max_fbps_count = gr_gm20b_get_max_fbps_count, - .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, - .wait_empty = gr_gp10b_wait_empty, - .init_cyclestats = gr_gm20b_init_cyclestats, - .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode, - .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, - .bpt_reg_info = gr_gm20b_bpt_reg_info, - .get_access_map = gr_gp10b_get_access_map, - .handle_fecs_error = gr_gp10b_handle_fecs_error, - .handle_sm_exception = gr_gp10b_handle_sm_exception, - .handle_tex_exception = gr_gp10b_handle_tex_exception, - .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, - .enable_exceptions = gk20a_gr_enable_exceptions, - .get_lrf_tex_ltc_dram_override = get_ecc_override_val, - .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, - .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, - .record_sm_error_state = gm20b_gr_record_sm_error_state, - .clear_sm_error_state = gm20b_gr_clear_sm_error_state, - .suspend_contexts = gr_gp10b_suspend_contexts, - .resume_contexts = gr_gk20a_resume_contexts, - .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, - .init_sm_id_table = gr_gk20a_init_sm_id_table, - .load_smid_config = gr_gp10b_load_smid_config, - .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, - .setup_rop_mapping = gr_gk20a_setup_rop_mapping, - .program_zcull_mapping = gr_gk20a_program_zcull_mapping, - .commit_global_timeslice = gr_gk20a_commit_global_timeslice, - .commit_inst = gr_gk20a_commit_inst, - .load_tpc_mask = gr_gm20b_load_tpc_mask, - .trigger_suspend = gr_gk20a_trigger_suspend, - .wait_for_pause = gr_gk20a_wait_for_pause, - .resume_from_pause = gr_gk20a_resume_from_pause, - .clear_sm_errors = gr_gk20a_clear_sm_errors, - .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, - .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, - .sm_debugger_attached = gk20a_gr_sm_debugger_attached, - .suspend_single_sm = gk20a_gr_suspend_single_sm, - .suspend_all_sms = gk20a_gr_suspend_all_sms, - .resume_single_sm = gk20a_gr_resume_single_sm, - .resume_all_sms = gk20a_gr_resume_all_sms, - .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr, - .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, - .get_sm_no_lock_down_hww_global_esr_mask = - gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, - .lock_down_sm = gk20a_gr_lock_down_sm, - .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, - .clear_sm_hww = gm20b_gr_clear_sm_hww, - .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, - .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, - .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, - .set_boosted_ctx = NULL, - .set_preemption_mode = gr_gp10b_set_preemption_mode, - .set_czf_bypass = gr_gp10b_set_czf_bypass, - .init_czf_bypass = gr_gp10b_init_czf_bypass, - .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, - .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, - .init_preemption_state = NULL, - .update_boosted_ctx = NULL, - .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, - .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, - .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode, - .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, - .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, - .handle_notify_pending = gk20a_gr_handle_notify_pending, - .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, - .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, - .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, - .decode_priv_addr = gr_gk20a_decode_priv_addr, - .create_priv_addr_table = gr_gk20a_create_priv_addr_table, - .get_pmm_per_chiplet_offset = - gr_gm20b_get_pmm_per_chiplet_offset, - .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr, - .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v, - .alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers, - .map_global_ctx_buffers = gr_gk20a_map_global_ctx_buffers, - .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, - .get_offset_in_gpccs_segment = - gr_gk20a_get_offset_in_gpccs_segment, - .set_debug_mode = gm20b_gr_set_debug_mode, - .dump_gr_falcon_stats = gk20a_fecs_dump_falcon_stats, - .get_fecs_ctx_state_store_major_rev_id = - gk20a_gr_get_fecs_ctx_state_store_major_rev_id, - .alloc_gfxp_rtv_cb = NULL, - .commit_gfxp_rtv_cb = NULL, - .ctxsw_prog = { - .hw_get_fecs_header_size = - gm20b_ctxsw_prog_hw_get_fecs_header_size, - .hw_get_gpccs_header_size = - gm20b_ctxsw_prog_hw_get_gpccs_header_size, - .hw_get_extended_buffer_segments_size_in_bytes = - gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, - .hw_extended_marker_size_in_bytes = - gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, - .hw_get_perf_counter_control_register_stride = - gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, - .get_main_image_ctx_id = - gm20b_ctxsw_prog_get_main_image_ctx_id, - .get_patch_count = gm20b_ctxsw_prog_get_patch_count, - .set_patch_count = gm20b_ctxsw_prog_set_patch_count, - .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, - .set_zcull = gm20b_ctxsw_prog_set_zcull, - .set_zcull_mode_no_ctxsw = - gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw, - .is_zcull_mode_separate_buffer = - gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, - .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, - .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, - .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, - .set_pm_mode_no_ctxsw = - gm20b_ctxsw_prog_set_pm_mode_no_ctxsw, - .set_pm_mode_ctxsw = gm20b_ctxsw_prog_set_pm_mode_ctxsw, - .hw_get_pm_mode_no_ctxsw = - gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw, - .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, - .set_compute_preemption_mode_cta = - gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_compute_preemption_mode_cilp = - gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, - .set_graphics_preemption_mode_gfxp = - gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, - .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, - .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, - .set_priv_access_map_config_mode = - gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = - gm20b_ctxsw_prog_set_priv_access_map_addr, - .disable_verif_features = - gm20b_ctxsw_prog_disable_verif_features, - .check_main_image_header_magic = - gm20b_ctxsw_prog_check_main_image_header_magic, - .check_local_header_magic = - gm20b_ctxsw_prog_check_local_header_magic, - .get_num_gpcs = gm20b_ctxsw_prog_get_num_gpcs, - .get_num_tpcs = gm20b_ctxsw_prog_get_num_tpcs, - .get_extended_buffer_size_offset = - gm20b_ctxsw_prog_get_extended_buffer_size_offset, - .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, - .get_local_priv_register_ctl_offset = - gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, - .hw_get_ts_tag_invalid_timestamp = - gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, - .hw_get_ts_tag = gm20b_ctxsw_prog_hw_get_ts_tag, - .hw_record_ts_timestamp = - gm20b_ctxsw_prog_hw_record_ts_timestamp, - .hw_get_ts_record_size_in_bytes = - gm20b_ctxsw_prog_hw_get_ts_record_size_in_bytes, - .is_ts_valid_record = gm20b_ctxsw_prog_is_ts_valid_record, - .get_ts_buffer_aperture_mask = - gm20b_ctxsw_prog_get_ts_buffer_aperture_mask, - .set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records, - .set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr, - .set_pmu_options_boost_clock_frequencies = - gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, - .set_full_preemption_ptr = - gp10b_ctxsw_prog_set_full_preemption_ptr, - .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, - } - }, - .fb = { - .init_hw = gm20b_fb_init_hw, - .init_fs_state = gp106_fb_init_fs_state, - .set_mmu_page_size = NULL, - .set_use_full_comp_tag_line = - gm20b_fb_set_use_full_comp_tag_line, - .mmu_ctrl = gm20b_fb_mmu_ctrl, - .mmu_debug_ctrl = gm20b_fb_mmu_debug_ctrl, - .mmu_debug_wr = gm20b_fb_mmu_debug_wr, - .mmu_debug_rd = gm20b_fb_mmu_debug_rd, - .compression_page_size = gp10b_fb_compression_page_size, - .compressible_page_size = gp10b_fb_compressible_page_size, - .compression_align_mask = gm20b_fb_compression_align_mask, - .vpr_info_fetch = NULL, - .dump_vpr_info = NULL, - .dump_wpr_info = gm20b_fb_dump_wpr_info, - .read_wpr_info = gm20b_fb_read_wpr_info, - .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, - .set_debug_mode = gm20b_fb_set_debug_mode, - .tlb_invalidate = gm20b_fb_tlb_invalidate, - .mem_unlock = NULL, - .get_vidmem_size = gp106_fb_get_vidmem_size, - }, - .nvdec = { - .falcon_base_addr = gp106_nvdec_falcon_base_addr, - }, - .clock_gating = { - .slcg_bus_load_gating_prod = - gp106_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gp106_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gp106_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gp106_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gp106_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gp106_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gp106_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gp106_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gp106_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gp106_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gp106_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gp106_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gp106_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gp106_blcg_bus_load_gating_prod, - .blcg_ce_load_gating_prod = - gp106_blcg_ce_load_gating_prod, - .blcg_fb_load_gating_prod = - gp106_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gp106_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gp106_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gp106_blcg_ltc_load_gating_prod, - .blcg_pmu_load_gating_prod = - gp106_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gp106_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gp106_pg_gr_load_gating_prod, - }, - .fifo = { - .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, - .bind_channel = channel_gm20b_bind, - .unbind_channel = gk20a_fifo_channel_unbind, - .disable_channel = gk20a_fifo_disable_channel, - .enable_channel = gk20a_fifo_enable_channel, - .alloc_inst = gk20a_fifo_alloc_inst, - .free_inst = gk20a_fifo_free_inst, - .setup_ramfc = channel_gp10b_setup_ramfc, - .default_timeslice_us = gk20a_fifo_default_timeslice_us, - .setup_userd = gk20a_fifo_setup_userd, - .userd_gp_get = gk20a_fifo_userd_gp_get, - .userd_gp_put = gk20a_fifo_userd_gp_put, - .userd_pb_get = gk20a_fifo_userd_pb_get, - .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, - .preempt_channel = gk20a_fifo_preempt_channel, - .preempt_tsg = gk20a_fifo_preempt_tsg, - .enable_tsg = gk20a_enable_tsg, - .disable_tsg = gk20a_disable_tsg, - .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, - .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, - .update_runlist = gk20a_fifo_update_runlist, - .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, - .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, - .get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc, - .get_mmu_fault_client_desc = gp106_fifo_get_mmu_fault_client_desc, - .get_mmu_fault_gpc_desc = gp106_fifo_get_mmu_fault_gpc_desc, - .wait_engine_idle = gk20a_fifo_wait_engine_idle, - .get_num_fifos = gp106_fifo_get_num_fifos, - .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, - .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, - .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, - .force_reset_ch = gk20a_fifo_force_reset_ch, - .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, - .device_info_data_parse = gp10b_device_info_data_parse, - .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, - .init_engine_info = gk20a_fifo_init_engine_info, - .runlist_entry_size = ram_rl_entry_size_v, - .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, - .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, - .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, - .dump_pbdma_status = gk20a_dump_pbdma_status, - .dump_eng_status = gk20a_dump_eng_status, - .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, - .capture_channel_ram_dump = gk20a_capture_channel_ram_dump, - .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, - .is_preempt_pending = gk20a_fifo_is_preempt_pending, - .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, - .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, - .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, - .handle_sched_error = gk20a_fifo_handle_sched_error, - .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, - .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, - .tsg_bind_channel = gk20a_tsg_bind_channel, - .tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel, - .post_event_id = gk20a_tsg_event_id_post_event, - .ch_abort_clean_up = gk20a_channel_abort_clean_up, - .check_tsg_ctxsw_timeout = gk20a_fifo_check_tsg_ctxsw_timeout, - .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, - .channel_suspend = gk20a_channel_suspend, - .channel_resume = gk20a_channel_resume, - .set_error_notifier = nvgpu_set_error_notifier, - .setup_sw = gk20a_init_fifo_setup_sw, -#ifdef CONFIG_TEGRA_GK20A_NVHOST - .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, - .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, - .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, - .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, - .get_syncpt_incr_per_release = - gk20a_fifo_get_syncpt_incr_per_release, - .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, - .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, - .get_sync_ro_map = NULL, -#endif - .resetup_ramfc = gp10b_fifo_resetup_ramfc, - .device_info_fault_id = top_device_info_data_fault_id_enum_v, - .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, - .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, - .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gk20a_fifo_add_sema_cmd, - .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, - .runlist_busy_engines = gk20a_fifo_runlist_busy_engines, - }, - .netlist = { - .get_netlist_name = gp106_netlist_get_name, - .is_fw_defined = gp106_netlist_is_firmware_defined, - }, -#ifdef CONFIG_GK20A_CTXSW_TRACE - .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = gk20a_fecs_trace_init, - .deinit = gk20a_fecs_trace_deinit, - .enable = gk20a_fecs_trace_enable, - .disable = gk20a_fecs_trace_disable, - .is_enabled = gk20a_fecs_trace_is_enabled, - .reset = gk20a_fecs_trace_reset, - .flush = gp10b_fecs_trace_flush, - .poll = gk20a_fecs_trace_poll, - .bind_channel = gk20a_fecs_trace_bind_channel, - .unbind_channel = gk20a_fecs_trace_unbind_channel, - .max_entries = gk20a_gr_max_entries, - }, -#endif /* CONFIG_GK20A_CTXSW_TRACE */ - .mm = { - .support_sparse = gm20b_mm_support_sparse, - .gmmu_map = gk20a_locked_gmmu_map, - .gmmu_unmap = gk20a_locked_gmmu_unmap, - .vm_bind_channel = gk20a_vm_bind_channel, - .fb_flush = gk20a_mm_fb_flush, - .l2_invalidate = gk20a_mm_l2_invalidate, - .l2_flush = gk20a_mm_l2_flush, - .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, - .get_big_page_sizes = gm20b_mm_get_big_page_sizes, - .get_default_big_page_size = gp10b_mm_get_default_big_page_size, - .gpu_phys_addr = gm20b_gpu_phys_addr, - .get_mmu_levels = gp10b_mm_get_mmu_levels, - .init_pdb = gp10b_mm_init_pdb, - .init_mm_setup_hw = gk20a_init_mm_setup_hw, - .is_bar1_supported = gm20b_mm_is_bar1_supported, - .alloc_inst_block = gk20a_alloc_inst_block, - .init_inst_block = gk20a_init_inst_block, - .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, - .init_bar2_vm = gp10b_init_bar2_vm, - .remove_bar2_vm = gp10b_remove_bar2_vm, - .get_kind_invalid = gm20b_get_kind_invalid, - .get_kind_pitch = gm20b_get_kind_pitch, - .bar1_map = gk20a_mm_bar1_map, - }, - .pramin = { - .data032_r = pram_data032_r, - }, - .therm = { - .init_elcg_mode = gm20b_therm_init_elcg_mode, - .init_blcg_mode = gm20b_therm_init_blcg_mode, - .elcg_init_idle_filters = gp106_elcg_init_idle_filters, - .get_internal_sensor_curr_temp = - gp106_get_internal_sensor_curr_temp, - .get_internal_sensor_limits = gp106_get_internal_sensor_limits, - .configure_therm_alert = gp106_configure_therm_alert, - }, - .pmu = { - .falcon_base_addr = gp106_pmu_falcon_base_addr, - .init_wpr_region = gm20b_pmu_init_acr, - .load_lsfalcon_ucode = gp106_load_falcon_ucode, - .is_lazy_bootstrap = gp106_is_lazy_bootstrap, - .is_priv_load = gp106_is_priv_load, - .prepare_ucode = gp106_prepare_ucode_blob, - .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, - .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, - .pmu_queue_tail = gk20a_pmu_queue_tail, - .pmu_get_queue_head = pwr_pmu_queue_head_r, - .pmu_mutex_release = gk20a_pmu_mutex_release, - .pmu_is_interrupted = gk20a_pmu_is_interrupted, - .pmu_isr = gk20a_pmu_isr, - .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, - .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, - .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, - .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, - .pmu_read_idle_intr_status = gk20a_pmu_read_idle_intr_status, - .pmu_clear_idle_intr_status = gk20a_pmu_clear_idle_intr_status, - .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, - .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, - .pmu_enable_irq = gk20a_pmu_enable_irq, - .is_pmu_supported = gp106_is_pmu_supported, - .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, - .pmu_elpg_statistics = gp106_pmu_elpg_statistics, - .pmu_init_perfmon = nvgpu_pmu_init_perfmon, - .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling, - .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling, - .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, - .pmu_is_lpwr_feature_supported = - gp106_pmu_is_lpwr_feature_supported, - .pmu_msgq_tail = gk20a_pmu_msgq_tail, - .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, - .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, - .pmu_queue_head = gk20a_pmu_queue_head, - .pmu_pg_param_post_init = nvgpu_lpwr_post_init, - .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, - .pmu_pg_init_param = gp106_pg_param_init, - .reset_engine = gp106_pmu_engine_reset, - .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, - .write_dmatrfbase = gp10b_write_dmatrfbase, - .pmu_mutex_size = pwr_pmu_mutex__size_1_v, - .is_engine_in_reset = gp106_pmu_is_engine_in_reset, - .pmu_get_queue_tail = pwr_pmu_queue_tail_r, - .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, - .get_irqdest = gk20a_pmu_get_irqdest, - .alloc_super_surface = NULL, - .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, - .update_lspmu_cmdline_args = - gp106_update_lspmu_cmdline_args, - .setup_apertures = gp106_pmu_setup_apertures, - .secured_pmu_start = gm20b_secured_pmu_start, - }, - .clk = { - .init_clk_support = gp106_init_clk_support, - .get_crystal_clk_hz = gp106_crystal_clk_hz, - .get_rate_cntr = gp106_get_rate_cntr, - .measure_freq = gp106_clk_measure_freq, - .suspend_clk_support = gp106_suspend_clk_support, - .clk_domain_get_f_points = gp106_clk_domain_get_f_points, - .mclk_init = gp106_mclk_init, - .mclk_change = gp106_mclk_change, - .mclk_deinit = gp106_mclk_deinit, - .perf_pmu_vfe_load = perf_pmu_vfe_load, - }, - .clk_arb = { - .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, - .get_arbiter_f_points = gp106_get_arbiter_f_points, - .get_arbiter_clk_range = gp106_get_arbiter_clk_range, - .get_arbiter_clk_default = gp106_get_arbiter_clk_default, - .get_current_pstate = nvgpu_clk_arb_get_current_pstate, - .arbiter_clk_init = gp106_init_clk_arbiter, - .clk_arb_run_arbiter_cb = gp106_clk_arb_run_arbiter_cb, - .clk_arb_cleanup = gp106_clk_arb_cleanup, - }, - .regops = { - .exec_regops = exec_regops_gk20a, - .get_global_whitelist_ranges = - gp106_get_global_whitelist_ranges, - .get_global_whitelist_ranges_count = - gp106_get_global_whitelist_ranges_count, - .get_context_whitelist_ranges = - gp106_get_context_whitelist_ranges, - .get_context_whitelist_ranges_count = - gp106_get_context_whitelist_ranges_count, - .get_runcontrol_whitelist = gp106_get_runcontrol_whitelist, - .get_runcontrol_whitelist_count = - gp106_get_runcontrol_whitelist_count, - .get_qctl_whitelist = gp106_get_qctl_whitelist, - .get_qctl_whitelist_count = gp106_get_qctl_whitelist_count, - }, - .mc = { - .intr_mask = mc_gp10b_intr_mask, - .intr_enable = mc_gp10b_intr_enable, - .intr_unit_config = mc_gp10b_intr_unit_config, - .isr_stall = mc_gp10b_isr_stall, - .intr_stall = mc_gp10b_intr_stall, - .intr_stall_pause = mc_gp10b_intr_stall_pause, - .intr_stall_resume = mc_gp10b_intr_stall_resume, - .intr_nonstall = mc_gp10b_intr_nonstall, - .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, - .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, - .isr_nonstall = gm20b_mc_isr_nonstall, - .enable = gm20b_mc_enable, - .disable = gm20b_mc_disable, - .reset = gm20b_mc_reset, - .is_intr1_pending = mc_gp10b_is_intr1_pending, - .log_pending_intrs = mc_gp10b_log_pending_intrs, - .reset_mask = gm20b_mc_reset_mask, - .is_enabled = gm20b_mc_is_enabled, - .fb_reset = NULL, - .ltc_isr = mc_gp10b_ltc_isr, - }, - .debug = { - .show_dump = gk20a_debug_show_dump, - }, - .debugger = { - .post_events = nvgpu_dbg_gpu_post_events, - .dbg_set_powergate = nvgpu_dbg_set_powergate, - .check_and_set_global_reservation = - nvgpu_check_and_set_global_reservation, - .check_and_set_context_reservation = - nvgpu_check_and_set_context_reservation, - .release_profiler_reservation = - nvgpu_release_profiler_reservation, - }, - .perf = { - .enable_membuf = gm20b_perf_enable_membuf, - .disable_membuf = gm20b_perf_disable_membuf, - .membuf_reset_streaming = gm20b_perf_membuf_reset_streaming, - .get_membuf_pending_bytes = gm20b_perf_get_membuf_pending_bytes, - .set_membuf_handled_bytes = gm20b_perf_set_membuf_handled_bytes, - .get_membuf_overflow_status = - gm20b_perf_get_membuf_overflow_status, - }, - .perfbuf = { - .perfbuf_enable = nvgpu_perfbuf_enable_locked, - .perfbuf_disable = nvgpu_perfbuf_disable_locked, - }, - .bus = { - .init_hw = gk20a_bus_init_hw, - .isr = gk20a_bus_isr, - .bar1_bind = gm20b_bus_bar1_bind, - .bar2_bind = gp10b_bus_bar2_bind, - .set_bar0_window = gk20a_bus_set_bar0_window, - }, - .ptimer = { - .isr = gk20a_ptimer_isr, - .read_ptimer = gk20a_read_ptimer, - .get_timestamps_zipper = nvgpu_get_timestamps_zipper, - }, -#if defined(CONFIG_GK20A_CYCLE_STATS) - .css = { - .enable_snapshot = nvgpu_css_enable_snapshot, - .disable_snapshot = nvgpu_css_disable_snapshot, - .check_data_available = nvgpu_css_check_data_available, - .set_handled_snapshots = nvgpu_css_set_handled_snapshots, - .allocate_perfmon_ids = nvgpu_css_allocate_perfmon_ids, - .release_perfmon_ids = nvgpu_css_release_perfmon_ids, - .get_overflow_status = nvgpu_css_get_overflow_status, - .get_pending_snapshots = nvgpu_css_get_pending_snapshots, - }, -#endif - .xve = { - .get_speed = xve_get_speed_gp106, - .set_speed = xve_set_speed_gp106, - .available_speeds = xve_available_speeds_gp106, - .xve_readl = xve_xve_readl_gp106, - .xve_writel = xve_xve_writel_gp106, - .disable_aspm = xve_disable_aspm_gp106, - .reset_gpu = xve_reset_gpu_gp106, -#if defined(CONFIG_PCI_MSI) - .rearm_msi = xve_rearm_msi_gp106, -#endif - .enable_shadow_rom = xve_enable_shadow_rom_gp106, - .disable_shadow_rom = xve_disable_shadow_rom_gp106, - .get_link_control_status = xve_get_link_control_status, - }, - .falcon = { - .falcon_hal_sw_init = gp106_falcon_hal_sw_init, - }, - .priv_ring = { - .enable_priv_ring = gm20b_priv_ring_enable, - .isr = gp10b_priv_ring_isr, - .decode_error_code = gp10b_priv_ring_decode_error_code, - .set_ppriv_timeout_settings = - gm20b_priv_set_timeout_settings, - .enum_ltc = gm20b_priv_ring_enum_ltc, - }, - .fuse = { - .check_priv_security = gp106_fuse_check_priv_security, - .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, - .is_opt_feature_override_disable = - gp10b_fuse_is_opt_feature_override_disable, - .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, - .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, - .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, - .fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc, - .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, - .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, - .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, - .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, - .read_vin_cal_fuse_rev = gp106_fuse_read_vin_cal_fuse_rev, - .read_vin_cal_slope_intercept_fuse = - gp106_fuse_read_vin_cal_slope_intercept_fuse, - .read_vin_cal_gain_offset_fuse = - gp106_fuse_read_vin_cal_gain_offset_fuse, - }, - .acr = { - .acr_sw_init = nvgpu_gp106_acr_sw_init, - }, - .sec2 = { - .falcon_base_addr = gp106_sec2_falcon_base_addr, - }, - .get_litter_value = gp106_get_litter_value, - .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, -}; - -int gp106_init_hal(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - - nvgpu_log_fn(g, " "); - - gops->bios = gp106_ops.bios; - gops->ltc = gp106_ops.ltc; - gops->ce2 = gp106_ops.ce2; - gops->gr = gp106_ops.gr; - gops->gr.ctxsw_prog = gp106_ops.gr.ctxsw_prog; - gops->fb = gp106_ops.fb; - gops->nvdec = gp106_ops.nvdec; - gops->clock_gating = gp106_ops.clock_gating; - gops->fifo = gp106_ops.fifo; - gops->netlist = gp106_ops.netlist; -#ifdef CONFIG_GK20A_CTXSW_TRACE - gops->fecs_trace = gp106_ops.fecs_trace; -#endif - gops->mm = gp106_ops.mm; - gops->pramin = gp106_ops.pramin; - gops->therm = gp106_ops.therm; - gops->pmu = gp106_ops.pmu; - /* - * clk must be assigned member by member - * since some clk ops are assigned during probe prior to HAL init - */ - gops->clk.init_clk_support = gp106_ops.clk.init_clk_support; - gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz; - gops->clk.get_rate_cntr = gp106_ops.clk.get_rate_cntr; - gops->clk.measure_freq = gp106_ops.clk.measure_freq; - gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support; - gops->clk.mclk_init = gp106_ops.clk.mclk_init; - gops->clk.mclk_change = gp106_ops.clk.mclk_change; - gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit; - gops->clk.clk_domain_get_f_points = gp106_ops.clk.clk_domain_get_f_points; - gops->clk.perf_pmu_vfe_load = gp106_ops.clk.perf_pmu_vfe_load; - - gops->clk_arb = gp106_ops.clk_arb; - gops->regops = gp106_ops.regops; - gops->mc = gp106_ops.mc; - gops->debug = gp106_ops.debug; - gops->debugger = gp106_ops.debugger; - gops->perf = gp106_ops.perf; - gops->perfbuf = gp106_ops.perfbuf; - gops->bus = gp106_ops.bus; - gops->ptimer = gp106_ops.ptimer; -#if defined(CONFIG_GK20A_CYCLE_STATS) - gops->css = gp106_ops.css; -#endif - gops->xve = gp106_ops.xve; - gops->falcon = gp106_ops.falcon; - gops->priv_ring = gp106_ops.priv_ring; - gops->fuse = gp106_ops.fuse; - gops->acr = gp106_ops.acr; - gops->sec2 = gp106_ops.sec2; - - /* Lone functions */ - gops->get_litter_value = gp106_ops.get_litter_value; - gops->chip_init_gpu_characteristics = - gp106_ops.chip_init_gpu_characteristics; - gops->semaphore_wakeup = gk20a_channel_semaphore_wakeup; - - __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); - __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); - __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); - __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); - __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); - - /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ - if (gops->fuse.check_priv_security(g) != 0) { - /* Do not boot gpu */ - return -EINVAL; - } - - g->pmu_lsf_pmu_wpr_init_done = 0; - gops->clk.split_rail_support = true; - gops->clk.support_clk_freq_controller = true; - gops->clk.support_pmgr_domain = true; - gops->clk.support_lpwr_pg = true; - gops->clk.lut_num_entries = CTRL_CLK_LUT_NUM_ENTRIES_GP10x; - gops->clk.support_clk_freq_domain = false; - gops->pmu_perf.support_changeseq = false; - gops->pmu_perf.support_vfe = true; - gops->clk.support_vf_point = true; - - g->name = "gp10x"; - - nvgpu_log_fn(g, "done"); - - return 0; -} diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.h b/drivers/gpu/nvgpu/gp106/hal_gp106.h deleted file mode 100644 index 856acf537..000000000 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * GP106 Tegra HAL interface - * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_HAL_GP106_H -#define NVGPU_HAL_GP106_H -struct gk20a; - -int gp106_init_hal(struct gk20a *g); -#endif /* NVGPU_HAL_GP106_H */ diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c deleted file mode 100644 index 303104864..000000000 --- a/drivers/gpu/nvgpu/gp106/regops_gp106.c +++ /dev/null @@ -1,1742 +0,0 @@ -/* - * Tegra GP106 GPU Debugger Driver Register Ops - * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "gk20a/regops_gk20a.h" -#include "regops_gp106.h" - -static const struct regop_offset_range gp106_global_whitelist_ranges[] = { - { 0x000004f0, 1}, - { 0x00001a00, 3}, - { 0x00002800, 128}, - { 0x00009400, 1}, - { 0x00009410, 1}, - { 0x00009480, 1}, - { 0x00020200, 24}, - { 0x00021c04, 3}, - { 0x00021c14, 3}, - { 0x00021c24, 71}, - { 0x00021d44, 1}, - { 0x00021d4c, 1}, - { 0x00021d54, 1}, - { 0x00021d5c, 1}, - { 0x00021d68, 19}, - { 0x00021dbc, 16}, - { 0x00022430, 7}, - { 0x00022450, 1}, - { 0x0002245c, 2}, - { 0x00070000, 5}, - { 0x000840a8, 1}, - { 0x00084b5c, 1}, - { 0x000870a8, 1}, - { 0x000884e0, 1}, - { 0x000884f4, 1}, - { 0x0008e00c, 1}, - { 0x00100c18, 3}, - { 0x00100c84, 1}, - { 0x0010a0a8, 1}, - { 0x0010a4f0, 1}, - { 0x0013c808, 2}, - { 0x0013cc14, 1}, - { 0x0013cc34, 1}, - { 0x0013cc54, 1}, - { 0x0013cc74, 1}, - { 0x0013cc94, 1}, - { 0x0013ccb4, 1}, - { 0x0013ec18, 1}, - { 0x00140028, 1}, - { 0x00140280, 1}, - { 0x001402a0, 1}, - { 0x00140350, 1}, - { 0x00140480, 1}, - { 0x001404a0, 1}, - { 0x00140550, 1}, - { 0x00140680, 1}, - { 0x001406a0, 1}, - { 0x00140750, 1}, - { 0x00142028, 1}, - { 0x00142280, 1}, - { 0x001422a0, 1}, - { 0x00142350, 1}, - { 0x00142480, 1}, - { 0x001424a0, 1}, - { 0x00142550, 1}, - { 0x00142680, 1}, - { 0x001426a0, 1}, - { 0x00142750, 1}, - { 0x00144028, 1}, - { 0x00144280, 1}, - { 0x00144350, 1}, - { 0x00144480, 1}, - { 0x00144550, 1}, - { 0x00144680, 1}, - { 0x00144750, 1}, - { 0x00146028, 1}, - { 0x00146280, 1}, - { 0x00146350, 1}, - { 0x00146480, 1}, - { 0x00146550, 1}, - { 0x00146680, 1}, - { 0x00146750, 1}, - { 0x00148028, 1}, - { 0x00148280, 1}, - { 0x00148350, 1}, - { 0x00148480, 1}, - { 0x00148550, 1}, - { 0x00148680, 1}, - { 0x00148750, 1}, - { 0x0014a028, 1}, - { 0x0014a280, 1}, - { 0x0014a350, 1}, - { 0x0014a480, 1}, - { 0x0014a550, 1}, - { 0x0014a680, 1}, - { 0x0014a750, 1}, - { 0x0014c028, 1}, - { 0x0014c280, 1}, - { 0x0014c350, 1}, - { 0x0014c480, 1}, - { 0x0014c550, 1}, - { 0x0014c680, 1}, - { 0x0014c750, 1}, - { 0x0014e028, 1}, - { 0x0014e280, 1}, - { 0x0014e350, 1}, - { 0x0014e480, 1}, - { 0x0014e550, 1}, - { 0x0014e680, 1}, - { 0x0014e750, 1}, - { 0x00150028, 1}, - { 0x00150280, 1}, - { 0x00150350, 1}, - { 0x00150480, 1}, - { 0x00150550, 1}, - { 0x00150680, 1}, - { 0x00150750, 1}, - { 0x00152028, 1}, - { 0x00152280, 1}, - { 0x00152350, 1}, - { 0x00152480, 1}, - { 0x00152550, 1}, - { 0x00152680, 1}, - { 0x00152750, 1}, - { 0x00154028, 1}, - { 0x00154280, 1}, - { 0x00154350, 1}, - { 0x00154480, 1}, - { 0x00154550, 1}, - { 0x00154680, 1}, - { 0x00154750, 1}, - { 0x00156028, 1}, - { 0x00156280, 1}, - { 0x00156350, 1}, - { 0x00156480, 1}, - { 0x00156550, 1}, - { 0x00156680, 1}, - { 0x00156750, 1}, - { 0x0017e028, 1}, - { 0x0017e280, 1}, - { 0x0017e294, 1}, - { 0x0017e29c, 2}, - { 0x0017e2ac, 1}, - { 0x0017e350, 1}, - { 0x0017e39c, 1}, - { 0x0017e480, 1}, - { 0x0017e4a0, 1}, - { 0x0017e550, 1}, - { 0x0017e680, 1}, - { 0x0017e6a0, 1}, - { 0x0017e750, 1}, - { 0x00180040, 41}, - { 0x001800ec, 1}, - { 0x001800f8, 7}, - { 0x00180240, 41}, - { 0x001802ec, 1}, - { 0x001802f8, 7}, - { 0x00180440, 41}, - { 0x001804ec, 1}, - { 0x001804f8, 7}, - { 0x00180640, 41}, - { 0x001806ec, 1}, - { 0x001806f8, 7}, - { 0x00180840, 41}, - { 0x001808ec, 1}, - { 0x001808f8, 7}, - { 0x00180a40, 41}, - { 0x00180aec, 1}, - { 0x00180af8, 7}, - { 0x00180c40, 41}, - { 0x00180cec, 1}, - { 0x00180cf8, 7}, - { 0x00180e40, 41}, - { 0x00180eec, 1}, - { 0x00180ef8, 7}, - { 0x00181040, 41}, - { 0x001810ec, 1}, - { 0x001810f8, 7}, - { 0x00181240, 41}, - { 0x001812ec, 1}, - { 0x001812f8, 7}, - { 0x00181440, 41}, - { 0x001814ec, 1}, - { 0x001814f8, 7}, - { 0x00181640, 41}, - { 0x001816ec, 1}, - { 0x001816f8, 7}, - { 0x00181840, 41}, - { 0x001818ec, 1}, - { 0x001818f8, 7}, - { 0x00181a40, 41}, - { 0x00181aec, 1}, - { 0x00181af8, 7}, - { 0x00181c40, 41}, - { 0x00181cec, 1}, - { 0x00181cf8, 7}, - { 0x00181e40, 41}, - { 0x00181eec, 1}, - { 0x00181ef8, 7}, - { 0x00182040, 41}, - { 0x001820ec, 1}, - { 0x001820f8, 7}, - { 0x00182240, 41}, - { 0x001822ec, 1}, - { 0x001822f8, 7}, - { 0x00182440, 41}, - { 0x001824ec, 1}, - { 0x001824f8, 7}, - { 0x00182640, 41}, - { 0x001826ec, 1}, - { 0x001826f8, 7}, - { 0x00182840, 41}, - { 0x001828ec, 1}, - { 0x001828f8, 7}, - { 0x00182a40, 41}, - { 0x00182aec, 1}, - { 0x00182af8, 7}, - { 0x00182c40, 41}, - { 0x00182cec, 1}, - { 0x00182cf8, 7}, - { 0x00182e40, 41}, - { 0x00182eec, 1}, - { 0x00182ef8, 7}, - { 0x00183040, 41}, - { 0x001830ec, 1}, - { 0x001830f8, 7}, - { 0x00183240, 41}, - { 0x001832ec, 1}, - { 0x001832f8, 7}, - { 0x00183440, 41}, - { 0x001834ec, 1}, - { 0x001834f8, 7}, - { 0x00183640, 41}, - { 0x001836ec, 1}, - { 0x001836f8, 7}, - { 0x00183840, 41}, - { 0x001838ec, 1}, - { 0x001838f8, 7}, - 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{ 0x00529ef0, 28}, - { 0x00529f70, 1}, - { 0x00529f78, 2}, - { 0x00529f98, 2}, - { 0x00529fdc, 1}, - { 0x0052a02c, 2}, - { 0x0052a0a0, 1}, - { 0x0052a0a8, 1}, - { 0x0052a890, 2}, - { 0x0052a8a0, 3}, - { 0x0052a8b0, 2}, - { 0x0052b014, 1}, - { 0x0052b0cc, 1}, - { 0x0052b1dc, 1}, - { 0x0052b214, 1}, - { 0x0052b2cc, 1}, - { 0x0052b3dc, 1}, - { 0x0052b414, 1}, - { 0x0052b4cc, 1}, - { 0x0052b5dc, 1}, - { 0x0052be14, 1}, - { 0x0052becc, 1}, - { 0x0052bfdc, 1}, - { 0x0052c054, 1}, - { 0x0052c2b0, 1}, - { 0x0052c2b8, 3}, - { 0x0052c40c, 1}, - { 0x0052c48c, 2}, - { 0x0052c500, 1}, - { 0x0052c508, 2}, - { 0x0052c600, 11}, - { 0x0052c634, 2}, - { 0x0052c644, 11}, - { 0x0052c674, 10}, - { 0x0052c6a4, 1}, - { 0x0052c6ac, 2}, - { 0x0052c6e8, 1}, - { 0x0052c6f0, 28}, - { 0x0052c770, 1}, - { 0x0052c778, 2}, - { 0x0052c798, 2}, - { 0x0052c7dc, 1}, - { 0x0052c854, 1}, - { 0x0052cab0, 1}, - { 0x0052cab8, 3}, - { 0x0052cc0c, 1}, - { 0x0052cc8c, 2}, - { 0x0052cd00, 1}, - { 0x0052cd08, 2}, - { 0x0052ce00, 11}, - { 0x0052ce34, 2}, - { 0x0052ce44, 11}, - { 0x0052ce74, 10}, - { 0x0052cea4, 1}, - { 0x0052ceac, 2}, - { 0x0052cee8, 1}, - { 0x0052cef0, 28}, - { 0x0052cf70, 1}, - { 0x0052cf78, 2}, - { 0x0052cf98, 2}, - { 0x0052cfdc, 1}, - { 0x0052d054, 1}, - { 0x0052d2b0, 1}, - { 0x0052d2b8, 3}, - { 0x0052d40c, 1}, - { 0x0052d48c, 2}, - { 0x0052d500, 1}, - { 0x0052d508, 2}, - { 0x0052d600, 11}, - { 0x0052d634, 2}, - { 0x0052d644, 11}, - { 0x0052d674, 10}, - { 0x0052d6a4, 1}, - { 0x0052d6ac, 2}, - { 0x0052d6e8, 1}, - { 0x0052d6f0, 28}, - { 0x0052d770, 1}, - { 0x0052d778, 2}, - { 0x0052d798, 2}, - { 0x0052d7dc, 1}, - { 0x0052d854, 1}, - { 0x0052dab0, 1}, - { 0x0052dab8, 3}, - { 0x0052dc0c, 1}, - { 0x0052dc8c, 2}, - { 0x0052dd00, 1}, - { 0x0052dd08, 2}, - { 0x0052de00, 11}, - { 0x0052de34, 2}, - { 0x0052de44, 11}, - { 0x0052de74, 10}, - { 0x0052dea4, 1}, - { 0x0052deac, 2}, - { 0x0052dee8, 1}, - { 0x0052def0, 28}, - { 0x0052df70, 1}, - { 0x0052df78, 2}, - { 0x0052df98, 2}, - { 0x0052dfdc, 1}, - { 0x0052e054, 1}, - { 0x0052e2b0, 1}, - { 0x0052e2b8, 3}, - { 0x0052e40c, 1}, - { 0x0052e48c, 2}, - { 0x0052e500, 1}, - { 0x0052e508, 2}, - { 0x0052e600, 11}, - { 0x0052e634, 2}, - { 0x0052e644, 11}, - { 0x0052e674, 10}, - { 0x0052e6a4, 1}, - { 0x0052e6ac, 2}, - { 0x0052e6e8, 1}, - { 0x0052e6f0, 28}, - { 0x0052e770, 1}, - { 0x0052e778, 2}, - { 0x0052e798, 2}, - { 0x0052e7dc, 1}, - { 0x00900100, 1}, - { 0x00904100, 1}, - { 0x00908100, 1}, - { 0x0090c100, 1}, - { 0x00910100, 1}, - { 0x00914100, 1}, - { 0x009a0100, 1}, -}; - - -static const u64 gp106_global_whitelist_ranges_count = - ARRAY_SIZE(gp106_global_whitelist_ranges); - -/* context */ - -/* runcontrol */ -static const u32 gp106_runcontrol_whitelist[] = { -}; -static const u64 gp106_runcontrol_whitelist_count = - ARRAY_SIZE(gp106_runcontrol_whitelist); - -/* quad ctl */ -static const u32 gp106_qctl_whitelist[] = { -}; -static const u64 gp106_qctl_whitelist_count = - ARRAY_SIZE(gp106_qctl_whitelist); - -const struct regop_offset_range *gp106_get_global_whitelist_ranges(void) -{ - return gp106_global_whitelist_ranges; -} - -u64 gp106_get_global_whitelist_ranges_count(void) -{ - return gp106_global_whitelist_ranges_count; -} - -const struct regop_offset_range *gp106_get_context_whitelist_ranges(void) -{ - return gp106_global_whitelist_ranges; -} - -u64 gp106_get_context_whitelist_ranges_count(void) -{ - return gp106_global_whitelist_ranges_count; -} - -const u32 *gp106_get_runcontrol_whitelist(void) -{ - return gp106_runcontrol_whitelist; -} - -u64 gp106_get_runcontrol_whitelist_count(void) -{ - return gp106_runcontrol_whitelist_count; -} - -const u32 *gp106_get_qctl_whitelist(void) -{ - return gp106_qctl_whitelist; -} - -u64 gp106_get_qctl_whitelist_count(void) -{ - return gp106_qctl_whitelist_count; -} diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.h b/drivers/gpu/nvgpu/gp106/regops_gp106.h deleted file mode 100644 index 3de27104f..000000000 --- a/drivers/gpu/nvgpu/gp106/regops_gp106.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * - * Tegra GP106 GPU Debugger Driver Register Ops - * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_REGOPS_GP106_H -#define NVGPU_REGOPS_GP106_H - -const struct regop_offset_range *gp106_get_global_whitelist_ranges(void); -u64 gp106_get_global_whitelist_ranges_count(void); -const struct regop_offset_range *gp106_get_context_whitelist_ranges(void); -u64 gp106_get_context_whitelist_ranges_count(void); -const u32 *gp106_get_runcontrol_whitelist(void); -u64 gp106_get_runcontrol_whitelist_count(void); -const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void); -u64 gp106_get_runcontrol_whitelist_ranges_count(void); -const u32 *gp106_get_qctl_whitelist(void); -u64 gp106_get_qctl_whitelist_count(void); -const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void); -u64 gp106_get_qctl_whitelist_ranges_count(void); -int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s); - -#endif /* NVGPU_REGOPS_GP106_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 4b3dac339..42fc42984 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1906,8 +1906,6 @@ int gk20a_wait_for_idle(struct gk20a *g); #define GK20A_GPUID_GM20B 0x0000012BU #define GK20A_GPUID_GM20B_B 0x0000012EU #define NVGPU_GPUID_GP10B 0x0000013BU -#define NVGPU_GPUID_GP104 0x00000134U -#define NVGPU_GPUID_GP106 0x00000136U #define NVGPU_GPUID_GV11B 0x0000015BU #define NVGPU_GPUID_GV100 0x00000140U #define NVGPU_GPUID_TU104 0x00000164U diff --git a/drivers/gpu/nvgpu/os/linux/os_ops.c b/drivers/gpu/nvgpu/os/linux/os_ops.c index 1ecda8f75..c7ada5107 100644 --- a/drivers/gpu/nvgpu/os/linux/os_ops.c +++ b/drivers/gpu/nvgpu/os/linux/os_ops.c @@ -18,7 +18,6 @@ #include "os_ops_gm20b.h" #include "os_ops_gp10b.h" -#include "os_ops_gp106.h" #include "os_ops_gv11b.h" #include "os_ops_gv100.h" #include "os_ops_tu104.h" @@ -36,9 +35,6 @@ int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l) case NVGPU_GPUID_GP10B: nvgpu_gp10b_init_os_ops(l); break; - case NVGPU_GPUID_GP106: - nvgpu_gp106_init_os_ops(l); - break; case NVGPU_GPUID_GV100: nvgpu_gv100_init_os_ops(l); break; diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_gp106.c b/drivers/gpu/nvgpu/os/linux/os_ops_gp106.c deleted file mode 100644 index 14f1b0044..000000000 --- a/drivers/gpu/nvgpu/os/linux/os_ops_gp106.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "os_linux.h" - -#include "debug_clk_gp106.h" -#include "debug_therm_gp106.h" -#include "debug_fecs_trace.h" - -static struct nvgpu_os_linux_ops gp106_os_linux_ops = { - .clk = { - .init_debugfs = gp106_clk_init_debugfs, - }, - .therm = { - .init_debugfs = gp106_therm_init_debugfs, - }, - .fecs_trace = { - .init_debugfs = nvgpu_fecs_trace_init_debugfs, - }, -}; - -void nvgpu_gp106_init_os_ops(struct nvgpu_os_linux *l) -{ - l->ops.clk = gp106_os_linux_ops.clk; - l->ops.therm = gp106_os_linux_ops.therm; - l->ops.fecs_trace = gp106_os_linux_ops.fecs_trace; -} diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_gp106.h b/drivers/gpu/nvgpu/os/linux/os_ops_gp106.h deleted file mode 100644 index 7d423d5d1..000000000 --- a/drivers/gpu/nvgpu/os/linux/os_ops_gp106.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __LINUX_OS_OPS_GP106_H -#define __LINUX_OS_OPS_GP106_H - -void nvgpu_gp106_init_os_ops(struct nvgpu_os_linux *l); - -#endif diff --git a/drivers/gpu/nvgpu/os/linux/pci.c b/drivers/gpu/nvgpu/os/linux/pci.c index 0f7be08b5..34ab4ec1e 100644 --- a/drivers/gpu/nvgpu/os/linux/pci.c +++ b/drivers/gpu/nvgpu/os/linux/pci.c @@ -73,154 +73,6 @@ static long nvgpu_pci_clk_round_rate(struct device *dev, unsigned long rate) } static struct gk20a_platform nvgpu_pci_device[] = { - { /* DEVICE=0x1c35 */ - /* ptimer src frequency in hz */ - .ptimer_src_freq = 31250000, - - .probe = nvgpu_pci_tegra_probe, - .remove = nvgpu_pci_tegra_remove, - - /* power management configuration */ - .railgate_delay_init = 500, - .can_railgate_init = false, - .can_elpg_init = true, - .enable_elpg = true, - .enable_elcg = false, - .enable_slcg = true, - .enable_blcg = true, - .enable_mscg = true, - .can_slcg = true, - .can_blcg = true, - .can_elcg = true, - - .disable_aspm = true, - - /* power management callbacks */ - .is_railgated = nvgpu_pci_tegra_is_railgated, - .clk_round_rate = nvgpu_pci_clk_round_rate, - - .ch_wdt_timeout_ms = 7000, - - .unify_address_spaces = true, - .honors_aperture = true, - .dma_mask = DMA_BIT_MASK(40), - .vbios_min_version = 0x86063000, - .hardcode_sw_threshold = true, - .ina3221_dcb_index = 0, - .ina3221_i2c_address = 0x84, - .ina3221_i2c_port = 0x2, - }, - { /* DEVICE=0x1c36 */ - /* ptimer src frequency in hz */ - .ptimer_src_freq = 31250000, - - .probe = nvgpu_pci_tegra_probe, - .remove = nvgpu_pci_tegra_remove, - - /* power management configuration */ - .railgate_delay_init = 500, - .can_railgate_init = false, - .can_elpg_init = true, - .enable_elpg = true, - .enable_elcg = false, - .enable_slcg = true, - .enable_blcg = true, - .enable_mscg = true, - .can_slcg = true, - .can_blcg = true, - .can_elcg = true, - - .disable_aspm = true, - - /* power management callbacks */ - .is_railgated = nvgpu_pci_tegra_is_railgated, - .clk_round_rate = nvgpu_pci_clk_round_rate, - - .ch_wdt_timeout_ms = 7000, - - .unify_address_spaces = true, - .honors_aperture = true, - .dma_mask = DMA_BIT_MASK(40), - .vbios_min_version = 0x86062d00, - .hardcode_sw_threshold = true, - .ina3221_dcb_index = 0, - .ina3221_i2c_address = 0x84, - .ina3221_i2c_port = 0x2, - }, - { /* DEVICE=0x1c37 */ - /* ptimer src frequency in hz */ - .ptimer_src_freq = 31250000, - - .probe = nvgpu_pci_tegra_probe, - .remove = nvgpu_pci_tegra_remove, - - /* power management configuration */ - .railgate_delay_init = 500, - .can_railgate_init = false, - .can_elpg_init = true, - .enable_elpg = true, - .enable_elcg = false, - .enable_slcg = true, - .enable_blcg = true, - .enable_mscg = true, - .can_slcg = true, - .can_blcg = true, - .can_elcg = true, - - .disable_aspm = true, - - /* power management callbacks */ - .is_railgated = nvgpu_pci_tegra_is_railgated, - .clk_round_rate = nvgpu_pci_clk_round_rate, - - .ch_wdt_timeout_ms = 7000, - - .unify_address_spaces = true, - .honors_aperture = true, - .dma_mask = DMA_BIT_MASK(40), - .vbios_min_version = 0x86063000, - .hardcode_sw_threshold = true, - .ina3221_dcb_index = 0, - .ina3221_i2c_address = 0x84, - .ina3221_i2c_port = 0x2, - }, - { /* DEVICE=0x1c75 */ - /* ptimer src frequency in hz */ - .ptimer_src_freq = 31250000, - - .probe = nvgpu_pci_tegra_probe, - .remove = nvgpu_pci_tegra_remove, - - /* power management configuration */ - .railgate_delay_init = 500, - .can_railgate_init = false, - .can_elpg_init = true, - .enable_elpg = true, - .enable_elcg = false, - .enable_slcg = true, - .enable_blcg = true, - .enable_mscg = true, - .can_slcg = true, - .can_blcg = true, - .can_elcg = true, - - .disable_aspm = true, - - /* power management callbacks */ - .is_railgated = nvgpu_pci_tegra_is_railgated, - .clk_round_rate = nvgpu_pci_clk_round_rate, - - .ch_wdt_timeout_ms = 7000, - - .unify_address_spaces = true, - .honors_aperture = true, - .dma_mask = DMA_BIT_MASK(40), - .vbios_min_version = 0x86065300, - .hardcode_sw_threshold = false, - .ina3221_dcb_index = 1, - .ina3221_i2c_address = 0x80, - .ina3221_i2c_port = 0x1, - }, { /* DEVICE=PG503 SKU 201 */ /* ptimer src frequency in hz */ .ptimer_src_freq = 31250000, @@ -440,70 +292,46 @@ static struct gk20a_platform nvgpu_pci_device[] = { static struct pci_device_id nvgpu_pci_table[] = { { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c35), + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1db1), .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, .driver_data = 0, }, { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c36), + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1db0), .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, .driver_data = 1, }, { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c37), + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1dbe), .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, .driver_data = 2, }, { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c75), + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1df1), .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, .driver_data = 3, }, { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1db1), + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1e3f), .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, .driver_data = 4, }, { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1db0), + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1eba), .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, .driver_data = 5, }, - { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1dbe), - .class = PCI_BASE_CLASS_DISPLAY << 16, - .class_mask = 0xff << 16, - .driver_data = 6, - }, - { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1df1), - .class = PCI_BASE_CLASS_DISPLAY << 16, - .class_mask = 0xff << 16, - .driver_data = 7, - }, - { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1e3f), - .class = PCI_BASE_CLASS_DISPLAY << 16, - .class_mask = 0xff << 16, - .driver_data = 8, - }, - { - PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1eba), - .class = PCI_BASE_CLASS_DISPLAY << 16, - .class_mask = 0xff << 16, - .driver_data = 9, - }, { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1efa), .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, - .driver_data = 9, + .driver_data = 5, }, {} };