From 8d55f14fc919cf8c51c76b45d40651c227c70cf4 Mon Sep 17 00:00:00 2001 From: prsethi Date: Thu, 4 Feb 2021 07:54:58 +0000 Subject: [PATCH] gpu: nvgpu: doxygen update for unit os_utils Add range value details for various os_utils functions. Jira NVGPU-6258 Change-Id: Ib930a24d2a4b8e98520d87fcc2f48bef81d26fbd Signed-off-by: prsethi Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480205 (cherry picked from commit 210e1dd5360d29cad1a432e8de48669d51de134c) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483388 Reviewed-by: Alex Waterman Reviewed-by: Ankur Kishore Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/include/nvgpu/io.h | 8 +++++++- drivers/gpu/nvgpu/include/nvgpu/timers.h | 3 ++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/io.h b/drivers/gpu/nvgpu/include/nvgpu/io.h index c5cef7c07..e9cda7e82 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/io.h +++ b/drivers/gpu/nvgpu/include/nvgpu/io.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -46,6 +46,7 @@ struct gk20a; * * @param g [in] GPU super structure. * @param r [in] Register offset in GPU IO space. + * Range: 0 - TEGRA_GK20A_BAR0_SIZE. * @param v [in] Value to write at the offset. * * Write a 32-bit value to register offset in GPU IO space with an @@ -77,6 +78,7 @@ void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v); * * @param g [in] GPU super structure. * @param r [in] Register offset in GPU IO space. + * Range: 0 - TEGRA_GK20A_BAR0_SIZE. * * Read a 32-bit value from register offset in GPU IO space. If all * the bits are set in the value read then check for gpu state validity. @@ -91,6 +93,7 @@ u32 nvgpu_readl(struct gk20a *g, u32 r); * * @param g [in] GPU super structure. * @param r [in] Register offset in GPU IO space. + * Range: 0 - TEGRA_GK20A_BAR0_SIZE. * * Read a 32-bit to register offset from a GPU IO space. nvgpu_readl() is * called from this function. This function is implemented by the OS layer. @@ -135,6 +138,7 @@ void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v); * * @param g [in] GPU super structure. * @param r [in] Register offset in io-region. + * Range: 0 - TEGRA_GK20A_BAR1_SIZE. * @param v [in] Value to write at the offset. * * - Write a 32-bit value to register offset of region bar1. @@ -148,6 +152,7 @@ void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v); * * @param g [in] GPU super structure. * @param b [in] Register offset in io-region. + * Range: 0 - TEGRA_GK20A_BAR1_SIZE. * * - Read a 32-bit value from a region bar1. * @@ -171,6 +176,7 @@ bool nvgpu_io_exists(struct gk20a *g); * * @param g [in] GPU super structure. * @param r [in] Register offset in io-region. + * Range: 0 - TEGRA_GK20A_BAR0_SIZE. * * - BAR0 Offset is valid if it falls into BAR0 range. * diff --git a/drivers/gpu/nvgpu/include/nvgpu/timers.h b/drivers/gpu/nvgpu/include/nvgpu/timers.h index 2ede3f51c..a32456932 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/timers.h +++ b/drivers/gpu/nvgpu/include/nvgpu/timers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -269,6 +269,7 @@ u64 nvgpu_hr_timestamp(void); * @brief OS specific implementation to provide precise microsecond delay * * @param usecs [in] Delay in microseconds. + * Range: 0 - 500ms. * * - Wait using nanospin_ns until usecs expires. Log error if API returns non * zero value once wait time expires.