diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c
index 3cee9386f..0c203f224 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c
@@ -29,7 +29,7 @@
 #include <nvgpu/pmuif/ctrlperf.h>
 #include <nvgpu/pmu/pstate.h>
 #include <nvgpu/pmu/volt.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "clk.h"
 #include <nvgpu/timers.h>
@@ -200,7 +200,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
 	struct nv_pmu_clk_rpc rpccall;
 	struct clkrpc_pmucmdhandler_params handler;
 	struct nv_pmu_clk_load *clkload;
-	struct clk_freq_controllers *pclk_freq_controllers;
+	struct nvgpu_clk_freq_controllers *pclk_freq_controllers;
 	struct ctrl_boardobjgrp_mask_e32 *load_mask;
 	struct boardobjgrpmask_e32 isolate_cfc_mask;
 
@@ -297,7 +297,7 @@ done:
 	return status;
 }
 
-int clk_pmu_vin_load(struct gk20a *g)
+int nvgpu_clk_pmu_vin_load(struct gk20a *g)
 {
 	struct pmu_cmd cmd;
 	struct pmu_payload payload;
@@ -361,7 +361,7 @@ done:
 	return status;
 }
 
-int clk_pmu_clk_domains_load(struct gk20a *g)
+int nvgpu_clk_pmu_clk_domains_load(struct gk20a *g)
 {
 	struct pmu_cmd cmd;
 	struct pmu_payload payload;
@@ -426,7 +426,7 @@ done:
 
 u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
 	struct nv_pmu_clk_rpc *rpccall,
-	struct set_fll_clk *setfllclk)
+	struct nvgpu_set_fll_clk *setfllclk)
 {
 	struct nv_pmu_clk_vf_change_inject *vfchange;
 
@@ -468,7 +468,7 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
 
 u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
 	struct nv_pmu_clk_rpc *rpccall,
-	struct set_fll_clk *setfllclk)
+	struct nvgpu_set_fll_clk *setfllclk)
 {
 	struct nv_pmu_clk_vf_change_inject_v1 *vfchange;
 
@@ -499,7 +499,8 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
 	return 0;
 }
 
-static int clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
+static int clk_pmu_vf_inject(struct gk20a *g,
+		struct nvgpu_set_fll_clk *setfllclk)
 {
 	struct pmu_cmd cmd;
 	struct pmu_payload payload;
@@ -577,7 +578,7 @@ static u8 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz)
 {
 	struct fll_device *pflldev;
 	u8 j;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
 		struct fll_device *, pflldev, j) {
@@ -597,7 +598,7 @@ static int set_regime_id(struct gk20a *g, u32 domain, u8 regimeid)
 {
 	struct fll_device *pflldev;
 	u8 j;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
 		struct fll_device *, pflldev, j) {
@@ -613,7 +614,7 @@ static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid)
 {
 	struct fll_device *pflldev;
 	u8 j;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->avfs_fllobjs.super.super),
 		struct fll_device *, pflldev, j) {
@@ -625,7 +626,7 @@ static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid)
 	return -EINVAL;
 }
 
-int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk)
+int clk_set_fll_clks(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk)
 {
 	int status = -EINVAL;
 
@@ -685,12 +686,12 @@ done:
 	return status;
 }
 
-int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk)
+int clk_get_fll_clks(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk)
 {
 	int status = -EINVAL;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	u8 i;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 	u16 clkmhz = 0;
 	struct clk_domain_35_master *p35master;
 	struct clk_domain_35_slave *p35slave;
@@ -701,7 +702,7 @@ int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk)
 	}
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
-			struct clk_domain *, pdomain, i) {
+			struct nvgpu_clk_domain *, pdomain, i) {
 
 		if (pdomain->api_domain == CTRL_CLK_DOMAIN_GPCCLK) {
 			if (!pdomain->super.implements(g, &pdomain->super,
@@ -717,10 +718,8 @@ int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk)
 
 				clkmhz = 0;
 				status = p35slave->slave.clkdomainclkgetslaveclk(g,
-						pclk,
-						(struct clk_domain *)(void *)p35slave,
-						&clkmhz,
-						setfllclk->gpc2clkmhz);
+					pclk, (struct nvgpu_clk_domain *)(void *)p35slave,
+					&clkmhz, setfllclk->gpc2clkmhz);
 				if (status != 0) {
 					status = -EINVAL;
 					goto done;
@@ -751,14 +750,14 @@ done:
 int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain)
 {
 	int status = -EINVAL;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	u8 i;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 	u16 clkmhz = 0;
 	u32 volt = 0;
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
-			struct clk_domain *, pdomain, i) {
+			struct nvgpu_clk_domain *, pdomain, i) {
 		if (pdomain->api_domain == clkapidomain) {
 			status = pdomain->clkdomainclkvfsearch(g, pclk,
 				pdomain, &clkmhz, &volt,
@@ -774,14 +773,14 @@ int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain)
 static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk)
 {
 	int status = -EINVAL;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	u8 i;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 	u16 clkmhz = 0;
 	struct clk_domain_3x_master *p3xmaster;
 	struct clk_domain_3x_slave *p3xslave;
 	unsigned long slaveidxmask;
-	struct set_fll_clk setfllclk;
+	struct nvgpu_set_fll_clk setfllclk;
 
 	if (fllclk->api_clk_domain != CTRL_CLK_DOMAIN_GPCCLK) {
 		return -EINVAL;
@@ -797,7 +796,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk)
 	setfllclk.gpc2clkmhz = fllclk->clkmhz;
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
-			struct clk_domain *, pdomain, i) {
+			struct nvgpu_clk_domain *, pdomain, i) {
 
 		if (pdomain->api_domain == fllclk->api_clk_domain) {
 
@@ -820,7 +819,7 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk)
 				clkmhz = 0;
 				status = p3xslave->clkdomainclkgetslaveclk(g,
 						pclk,
-						(struct clk_domain *)p3xslave,
+						(struct nvgpu_clk_domain *)p3xslave,
 						&clkmhz,
 						fllclk->clkmhz);
 				if (status != 0) {
@@ -986,7 +985,7 @@ int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
 	struct nv_pmu_rpc_perf_change_seq_queue_change rpc;
 	struct ctrl_perf_change_seq_change_input change_input;
 	struct clk_set_info *p0_clk_set_info;
-	struct clk_domain *pclk_domain;
+	struct nvgpu_clk_domain *pclk_domain;
 	int status = 0;
 	u8 i = 0, gpcclk_domain=0;
 	u32 gpcclk_clkmhz=0, gpcclk_voltuv=0;
@@ -996,7 +995,7 @@ int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g)
 		sizeof(struct ctrl_perf_change_seq_change_input));
 
 	BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs.super.super),
-		struct clk_domain *, pclk_domain, i) {
+		struct nvgpu_clk_domain *, pclk_domain, i) {
 
 		p0_clk_set_info = pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0,
 				pclk_domain->domain);
@@ -1109,9 +1108,9 @@ int clk_domain_get_f_or_v(struct gk20a *g, u32 clkapidomain,
 	u16 *pclkmhz, u32 *pvoltuv, u8 railidx)
 {
 	int status = -EINVAL;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	u8 i;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 	u8 rail;
 
 	if ((pclkmhz == NULL) || (pvoltuv == NULL)) {
@@ -1127,7 +1126,7 @@ int clk_domain_get_f_or_v(struct gk20a *g, u32 clkapidomain,
 	}
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
-			struct clk_domain *, pdomain, i) {
+			struct nvgpu_clk_domain *, pdomain, i) {
 		if (pdomain->api_domain == clkapidomain) {
 			status = pdomain->clkdomainclkvfsearch(g, pclk,
 				pdomain, pclkmhz, pvoltuv, rail);
@@ -1137,7 +1136,7 @@ int clk_domain_get_f_or_v(struct gk20a *g, u32 clkapidomain,
 	return status;
 }
 
-int clk_init_pmupstate(struct gk20a *g)
+int nvgpu_clk_init_pmupstate(struct gk20a *g)
 {
 	/* If already allocated, do not re-allocate */
 	if (g->clk_pmu != NULL) {
@@ -1152,7 +1151,7 @@ int clk_init_pmupstate(struct gk20a *g)
 	return 0;
 }
 
-void clk_free_pmupstate(struct gk20a *g)
+void nvgpu_clk_free_pmupstate(struct gk20a *g)
 {
 	nvgpu_kfree(g, g->clk_pmu);
 	g->clk_pmu = NULL;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.h b/drivers/gpu/nvgpu/common/pmu/clk/clk.h
index df0d5429c..bfd3e5ace 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.h
@@ -96,7 +96,7 @@ struct vbios_clocks_table_1x_hal_clock_entry {
 #define PERF_CLK_PCIEGENCLK     12U
 #define PERF_CLK_NUM            13U
 
-struct set_fll_clk;
+struct nvgpu_set_fll_clk;
 
 int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
 int clk_domain_get_f_or_v(struct gk20a *g, u32 clkapidomain,
@@ -105,8 +105,8 @@ int clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx,
 	u32 *pclkmhz, u32 *pvoltuv, u8 railidx);
 int clk_domain_volt_to_freq( struct gk20a *g, u8 clkdomain_idx,
 	u32 *pclkmhz, u32 *pvoltuv, u8 railidx);
-int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk);
-int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk);
+int clk_get_fll_clks(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk);
+int clk_set_fll_clks(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk);
 int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx);
 int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload);
 int clk_freq_effective_avg(struct gk20a *g, u32 *freqkHz, u32  clkDomainMask);
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_arb.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_arb.c
index 868247ca3..ac4d0db30 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_arb.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_arb.c
@@ -36,7 +36,7 @@
 #include <nvgpu/pmu/pstate.h>
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/lpwr.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "clk.h"
 #include "clk_vf_point.h"
@@ -172,7 +172,7 @@ int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
 	 */
 	for (i = 0, j = 0, num_points = 0, clk_cur = 0;
 			i < table->gpc2clk_num_points; i++) {
-		struct set_fll_clk setfllclk;
+		struct nvgpu_set_fll_clk setfllclk;
 
 		if ((arb->gpc2clk_f_points[i] >= arb->gpc2clk_min) &&
 			(arb->gpc2clk_f_points[i] <= arb->gpc2clk_max) &&
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
index 51fa4cacc..e2b83a986 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
@@ -32,10 +32,11 @@
 #include "clk_fll.h"
 #include "clk_domain.h"
 
-static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs);
+static struct nvgpu_clk_domain *construct_clk_domain(struct gk20a *g,
+		void *pargs);
 
 static int devinit_get_clocks_table(struct gk20a *g,
-	struct clk_domains *pclkdomainobjs);
+	struct nvgpu_clk_domains *pclkdomainobjs);
 
 static int clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj
 	*board_obj_ptr,	struct nv_pmu_boardobj *ppmudata);
@@ -128,7 +129,8 @@ static int _clk_domains_pmudatainit_3x(struct gk20a *g,
 	struct nv_pmu_clk_clk_domain_boardobjgrp_set_header *pset =
 		(struct nv_pmu_clk_clk_domain_boardobjgrp_set_header *)
 		pboardobjgrppmu;
-	struct clk_domains *pdomains = (struct clk_domains *)pboardobjgrp;
+	struct nvgpu_clk_domains *pdomains =
+		(struct nvgpu_clk_domains *)pboardobjgrp;
 	int status = 0;
 
 	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
@@ -190,12 +192,12 @@ static int _clk_domains_pmudata_instget(struct gk20a *g,
 	return 0;
 }
 
-int clk_domain_sw_setup(struct gk20a *g)
+int nvgpu_clk_domain_sw_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
-	struct clk_domains *pclkdomainobjs;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domains *pclkdomainobjs;
+	struct nvgpu_clk_domain *pdomain;
 	struct clk_domain_3x_master *pdomain_master;
 	struct clk_domain_3x_slave *pdomain_slave;
 	struct clk_domain_35_master *pdomain_master_35;
@@ -250,7 +252,7 @@ int clk_domain_sw_setup(struct gk20a *g)
 	}
 
 	BOARDOBJGRP_FOR_EACH(&(pclkdomainobjs->super.super),
-			     struct clk_domain *, pdomain, i) {
+			     struct nvgpu_clk_domain *, pdomain, i) {
 		pdomain_master = NULL;
 		pdomain_master_35 = NULL;
 		if (pdomain->super.implements(g, &pdomain->super,
@@ -332,7 +334,7 @@ done:
 	return status;
 }
 
-int clk_domain_pmu_setup(struct gk20a *g)
+int nvgpu_clk_domain_pmu_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
@@ -352,7 +354,7 @@ int clk_domain_pmu_setup(struct gk20a *g)
 }
 
 static int devinit_get_clocks_table_35(struct gk20a *g,
-				    struct clk_domains *pclkdomainobjs, u8 *clocks_table_ptr)
+			struct nvgpu_clk_domains *pclkdomainobjs, u8 *clocks_table_ptr)
 {
 	int status = 0;
 	struct vbios_clocks_table_35_header clocks_table_header = { 0 };
@@ -361,10 +363,10 @@ static int devinit_get_clocks_table_35(struct gk20a *g,
 	u8 *clocks_tbl_entry_ptr = NULL;
 	u32 index = 0;
 	bool done = false;
-	struct clk_domain *pclkdomain_dev;
+	struct nvgpu_clk_domain *pclkdomain_dev;
 	union {
 		struct boardobj boardobj;
-		struct clk_domain clk_domain;
+		struct nvgpu_clk_domain clk_domain;
 		struct clk_domain_3x v3x;
 		struct clk_domain_3x_fixed v3x_fixed;
 		struct clk_domain_35_prog v35_prog;
@@ -574,7 +576,7 @@ done:
 }
 
 static int devinit_get_clocks_table_1x(struct gk20a *g,
-				    struct clk_domains *pclkdomainobjs, u8 *clocks_table_ptr)
+			struct nvgpu_clk_domains *pclkdomainobjs, u8 *clocks_table_ptr)
 {
 	int status = 0;
 	struct vbios_clocks_table_1x_header clocks_table_header = { 0 };
@@ -582,11 +584,11 @@ static int devinit_get_clocks_table_1x(struct gk20a *g,
 	struct vbios_clocks_table_1x_hal_clock_entry *vbiosclktbl1xhalentry;
 	u8 *clocks_tbl_entry_ptr = NULL;
 	u32 index = 0;
-	struct clk_domain *pclkdomain_dev;
+	struct nvgpu_clk_domain *pclkdomain_dev;
 	bool done = false;
 	union {
 		struct boardobj boardobj;
-		struct clk_domain clk_domain;
+		struct nvgpu_clk_domain clk_domain;
 		struct clk_domain_3x v3x;
 		struct clk_domain_3x_fixed v3x_fixed;
 		struct clk_domain_3x_prog v3x_prog;
@@ -784,7 +786,7 @@ done:
 }
 
 static int devinit_get_clocks_table(struct gk20a *g,
-	    struct clk_domains *pclkdomainobjs)
+	    struct nvgpu_clk_domains *pclkdomainobjs)
 {
 	int status = 0;
 	u8 *clocks_table_ptr = NULL;
@@ -811,8 +813,8 @@ static int devinit_get_clocks_table(struct gk20a *g,
 }
 
 static int clkdomainclkproglink_not_supported(struct gk20a *g,
-					      struct clk_pmupstate *pclk,
-					      struct clk_domain *pdomain)
+					      struct nvgpu_clk_pmupstate *pclk,
+					      struct nvgpu_clk_domain *pdomain)
 {
 	nvgpu_log_info(g, " ");
 	return -EINVAL;
@@ -820,8 +822,8 @@ static int clkdomainclkproglink_not_supported(struct gk20a *g,
 
 static int clkdomainvfsearch_stub(
 	struct gk20a *g,
-	struct clk_pmupstate *pclk,
-	struct clk_domain *pdomain,
+	struct nvgpu_clk_pmupstate *pclk,
+	struct nvgpu_clk_domain *pdomain,
 	u16 *clkmhz,
 	u32 *voltuv,
 	u8 rail)
@@ -833,8 +835,8 @@ static int clkdomainvfsearch_stub(
 
 static int clkdomaingetfpoints_stub(
 	struct gk20a *g,
-	struct clk_pmupstate *pclk,
-	struct clk_domain *pdomain,
+	struct nvgpu_clk_pmupstate *pclk,
+	struct nvgpu_clk_domain *pdomain,
 	u32 *pfpointscount,
 	u16 *pfreqpointsinmhz,
 	u8 rail)
@@ -848,8 +850,8 @@ static int clk_domain_construct_super(struct gk20a *g,
 				      struct boardobj **ppboardobj,
 				      size_t size, void *pargs)
 {
-	struct clk_domain *pdomain;
-	struct clk_domain *ptmpdomain = (struct clk_domain *)pargs;
+	struct nvgpu_clk_domain *pdomain;
+	struct nvgpu_clk_domain *ptmpdomain = (struct nvgpu_clk_domain *)pargs;
 	int status = 0;
 
 	status = boardobj_construct_super(g, ppboardobj,
@@ -859,7 +861,7 @@ static int clk_domain_construct_super(struct gk20a *g,
 		return -EINVAL;
 	}
 
-	pdomain = (struct clk_domain *)*ppboardobj;
+	pdomain = (struct nvgpu_clk_domain *)*ppboardobj;
 
 	pdomain->super.pmudatainit =
 			clk_domain_pmudatainit_super;
@@ -933,8 +935,8 @@ static int clk_domain_construct_3x(struct gk20a *g,
 }
 
 static int clkdomainclkproglink_3x_prog(struct gk20a *g,
-					struct clk_pmupstate *pclk,
-					struct clk_domain *pdomain)
+					struct nvgpu_clk_pmupstate *pclk,
+					struct nvgpu_clk_domain *pdomain)
 {
 	int status = 0;
 	struct clk_domain_3x_prog *p3xprog =
@@ -956,8 +958,8 @@ static int clkdomainclkproglink_3x_prog(struct gk20a *g,
 }
 
 static int clkdomaingetslaveclk(struct gk20a *g,
-				struct clk_pmupstate *pclk,
-				struct clk_domain *pdomain,
+				struct nvgpu_clk_pmupstate *pclk,
+				struct nvgpu_clk_domain *pdomain,
 				u16 *pclkmhz,
 				u16 masterclkmhz)
 {
@@ -1006,8 +1008,8 @@ static int clkdomaingetslaveclk(struct gk20a *g,
 }
 
 static int clkdomainvfsearch(struct gk20a *g,
-				struct clk_pmupstate *pclk,
-				struct clk_domain *pdomain,
+				struct nvgpu_clk_pmupstate *pclk,
+				struct nvgpu_clk_domain *pdomain,
 				u16 *pclkmhz,
 				u32 *pvoltuv,
 				u8 rail)
@@ -1096,8 +1098,8 @@ done:
 static int clkdomaingetfpoints
 (
 	struct gk20a *g,
-	struct clk_pmupstate *pclk,
-	struct clk_domain *pdomain,
+	struct nvgpu_clk_pmupstate *pclk,
+	struct nvgpu_clk_domain *pdomain,
 	u32 *pfpointscount,
 	u16 *pfreqpointsinmhz,
 	u8 rail
@@ -1169,7 +1171,7 @@ static int clk_domain_pmudatainit_35_prog(struct gk20a *g,
 	struct clk_domain_35_prog *pclk_domain_35_prog;
 	struct clk_domain_3x_prog *pclk_domain_3x_prog;
 	struct nv_pmu_clk_clk_domain_35_prog_boardobj_set *pset;
-	struct clk_domains *pdomains = &(g->clk_pmu->clk_domainobjs);
+	struct nvgpu_clk_domains *pdomains = &(g->clk_pmu->clk_domainobjs);
 
 	nvgpu_log_info(g, " ");
 
@@ -1208,7 +1210,7 @@ static int _clk_domain_pmudatainit_3x_prog(struct gk20a *g,
 	int status = 0;
 	struct clk_domain_3x_prog *pclk_domain_3x_prog;
 	struct nv_pmu_clk_clk_domain_30_prog_boardobj_set *pset;
-	struct clk_domains *pdomains = &(g->clk_pmu->clk_domainobjs);
+	struct nvgpu_clk_domains *pdomains = &(g->clk_pmu->clk_domainobjs);
 
 	nvgpu_log_info(g, " ");
 
@@ -1454,8 +1456,8 @@ static int clk_domain_construct_3x_slave(struct gk20a *g,
 }
 
 static int clkdomainclkproglink_3x_master(struct gk20a *g,
-					  struct clk_pmupstate *pclk,
-					  struct clk_domain *pdomain)
+					  struct nvgpu_clk_pmupstate *pclk,
+					  struct nvgpu_clk_domain *pdomain)
 {
 	int status = 0;
 	struct clk_domain_3x_master *p3xmaster  =
@@ -1617,8 +1619,8 @@ static int clk_domain_construct_3x_master(struct gk20a *g,
 }
 
 static int clkdomainclkproglink_fixed(struct gk20a *g,
-				      struct clk_pmupstate *pclk,
-				      struct clk_domain *pdomain)
+				      struct nvgpu_clk_pmupstate *pclk,
+				      struct nvgpu_clk_domain *pdomain)
 {
 	nvgpu_log_info(g, " ");
 	return 0;
@@ -1682,7 +1684,7 @@ static int clk_domain_construct_3x_fixed(struct gk20a *g,
 	return status;
 }
 
-static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs)
+static struct nvgpu_clk_domain *construct_clk_domain(struct gk20a *g, void *pargs)
 {
 	struct boardobj *board_obj_ptr = NULL;
 	int status;
@@ -1725,7 +1727,7 @@ static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs)
 
 	nvgpu_log_info(g, " Done");
 
-	return (struct clk_domain *)board_obj_ptr;
+	return (struct nvgpu_clk_domain *)board_obj_ptr;
 }
 
 static int clk_domain_pmudatainit_super(struct gk20a *g,
@@ -1733,7 +1735,7 @@ static int clk_domain_pmudatainit_super(struct gk20a *g,
 					struct nv_pmu_boardobj *ppmudata)
 {
 	int status = 0;
-	struct clk_domain *pclk_domain;
+	struct nvgpu_clk_domain *pclk_domain;
 	struct nv_pmu_clk_clk_domain_boardobj_set *pset;
 
 	nvgpu_log_info(g, " ");
@@ -1743,7 +1745,7 @@ static int clk_domain_pmudatainit_super(struct gk20a *g,
 		return status;
 	}
 
-	pclk_domain = (struct clk_domain *)board_obj_ptr;
+	pclk_domain = (struct nvgpu_clk_domain *)board_obj_ptr;
 
 	pset = (struct nv_pmu_clk_clk_domain_boardobj_set *)ppmudata;
 
@@ -1754,15 +1756,15 @@ static int clk_domain_pmudatainit_super(struct gk20a *g,
 	return status;
 }
 
-int clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk)
+int clk_domain_clk_prog_link(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk)
 {
 	int status = 0;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	u8 i;
 
 	/* Iterate over all CLK_DOMAINs and flatten their VF curves.*/
 	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
-			struct clk_domain *, pdomain, i) {
+			struct nvgpu_clk_domain *, pdomain, i) {
 		status = pdomain->clkdomainclkproglink(g, pclk, pdomain);
 		if (status != 0) {
 			nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h
index a0beaea8f..7cb09dc47 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h
@@ -28,7 +28,8 @@
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/boardobjgrpmask.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
+#include <nvgpu/pmu/clk/clk_domain.h>
 
 #define CLK_DOMAIN_BOARDOBJGRP_VERSION 0x30
 #define CLK_DOMAIN_BOARDOBJGRP_VERSION_35 0x35
@@ -36,15 +37,15 @@
 #define CLK_TABLE_HAL_ENTRY_GP 0x02
 #define CLK_TABLE_HAL_ENTRY_GV 0x03
 
-struct clk_domains;
-struct clk_domain;
+struct nvgpu_clk_domains;
+struct nvgpu_clk_domain;
 
-typedef int clkgetslaveclk(struct gk20a *g, struct clk_pmupstate *pclk,
-			struct clk_domain *pdomain, u16 *clkmhz,
+typedef int clkgetslaveclk(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
+			struct nvgpu_clk_domain *pdomain, u16 *clkmhz,
 			u16 masterclkmhz);
 
 struct clk_domain_3x {
-	struct clk_domain super;
+	struct nvgpu_clk_domain super;
 	bool b_noise_aware_capable;
 };
 
@@ -102,10 +103,10 @@ struct clk_domain_35_slave {
 	struct clk_domain_30_slave slave;
 };
 
-int clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk);
+int clk_domain_clk_prog_link(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk);
 
 #define CLK_CLK_DOMAIN_GET(pclk, idx)                                   \
-	((struct clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(		\
+	((struct nvgpu_clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(		\
 		&pclk->clk_domainobjs.super.super, (u8)(idx)))
 
 #endif /* NVGPU_CLK_DOMAIN_H */
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
index 76b91558c..6d1e483f6 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
@@ -33,7 +33,7 @@
 #include "clk_domain.h"
 
 static int devinit_get_fll_device_table(struct gk20a *g,
-				   struct avfsfllobjs *pfllobjs);
+				   struct nvgpu_avfsfllobjs *pfllobjs);
 static struct fll_device *construct_fll_device(struct gk20a *g,
 		void *pargs);
 static int fll_device_init_pmudata_super(struct gk20a *g,
@@ -47,7 +47,7 @@ static int _clk_fll_devgrp_pmudatainit_super(struct gk20a *g,
 	struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header *pset =
 		(struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header *)
 		pboardobjgrppmu;
-	struct avfsfllobjs *pfll_objs = (struct avfsfllobjs *)
+	struct nvgpu_avfsfllobjs *pfll_objs = (struct nvgpu_avfsfllobjs *)
 		pboardobjgrp;
 	int status = 0;
 
@@ -115,11 +115,11 @@ static int _clk_fll_devgrp_pmustatus_instget(struct gk20a *g,
 	return 0;
 }
 
-int clk_fll_sw_setup(struct gk20a *g)
+int nvgpu_clk_fll_sw_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
-	struct avfsfllobjs *pfllobjs;
+	struct nvgpu_avfsfllobjs *pfllobjs;
 	struct fll_device *pfll;
 	struct fll_device *pfll_master;
 	struct fll_device *pfll_local;
@@ -151,7 +151,7 @@ int clk_fll_sw_setup(struct gk20a *g)
 	pboardobjgrp->pmudatainit  = _clk_fll_devgrp_pmudatainit_super;
 	pboardobjgrp->pmudatainstget  = _clk_fll_devgrp_pmudata_instget;
 	pboardobjgrp->pmustatusinstget  = _clk_fll_devgrp_pmustatus_instget;
-	pfllobjs = (struct avfsfllobjs *)pboardobjgrp;
+	pfllobjs = (struct nvgpu_avfsfllobjs *)pboardobjgrp;
 	pfllobjs->lut_num_entries = g->ops.clk.lut_num_entries;
 	pfllobjs->lut_step_size_uv = CTRL_CLK_VIN_STEP_SIZE_UV;
 	pfllobjs->lut_min_voltage_uv = CTRL_CLK_LUT_MIN_VOLTAGE_UV;
@@ -210,7 +210,7 @@ done:
 	return status;
 }
 
-int clk_fll_pmu_setup(struct gk20a *g)
+int nvgpu_clk_fll_pmu_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
@@ -230,7 +230,7 @@ int clk_fll_pmu_setup(struct gk20a *g)
 }
 
 static int devinit_get_fll_device_table(struct gk20a *g,
-				   struct avfsfllobjs *pfllobjs)
+				   struct nvgpu_avfsfllobjs *pfllobjs)
 {
 	int status = 0;
 	u8 *fll_table_ptr = NULL;
@@ -244,7 +244,7 @@ static int devinit_get_fll_device_table(struct gk20a *g,
 	struct vin_device *pvin_dev;
 	u32 desctablesize;
 	u32 vbios_domain = NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP;
-	struct avfsvinobjs *pvinobjs = &g->clk_pmu->avfs_vinobjs;
+	struct nvgpu_avfsvinobjs *pvinobjs = &g->clk_pmu->avfs_vinobjs;
 
 	nvgpu_log_info(g, " ");
 
@@ -407,7 +407,7 @@ u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain)
 }
 
 static int lutbroadcastslaveregister(struct gk20a *g,
-				     struct avfsfllobjs *pfllobjs,
+				     struct nvgpu_avfsfllobjs *pfllobjs,
 				     struct fll_device *pfll,
 				     struct fll_device *pfll_slave)
 {
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h
index 2576eca76..1d4e35561 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h
@@ -28,10 +28,10 @@
 #include <nvgpu/boardobjgrpmask.h>
 
 struct fll_device;
-struct avfsfllobjs;
+struct nvgpu_avfsfllobjs;
 
 typedef int fll_lut_broadcast_slave_register(struct gk20a *g,
-	struct avfsfllobjs *pfllobjs,
+	struct nvgpu_avfsfllobjs *pfllobjs,
 	struct fll_device *pfll,
 	struct fll_device *pfll_slave);
 
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
index a7171789b..0a10f2713 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
@@ -179,7 +179,7 @@ static struct clk_freq_controller *clk_clk_freq_controller_construct(
 
 
 static int clk_get_freq_controller_table(struct gk20a *g,
-		struct clk_freq_controllers *pclk_freq_controllers)
+		struct nvgpu_clk_freq_controllers *pclk_freq_controllers)
 {
 	int status = 0;
 	u8 *pfreq_controller_table_ptr = NULL;
@@ -190,7 +190,7 @@ static int clk_get_freq_controller_table(struct gk20a *g,
 	struct clk_freq_controller *pclk_freq_cntr = NULL;
 	struct clk_freq_controller *ptmp_freq_cntr = NULL;
 	struct clk_freq_controller_pi *ptmp_freq_cntr_pi = NULL;
-	struct clk_domain *pclk_domain;
+	struct nvgpu_clk_domain *pclk_domain;
 
 	struct freq_controller_data_type {
 		union {
@@ -325,7 +325,7 @@ done:
 	return status;
 }
 
-int clk_freq_controller_pmu_setup(struct gk20a *g)
+int nvgpu_clk_freq_controller_pmu_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
@@ -374,8 +374,8 @@ static int _clk_freq_controllers_pmudatainit(struct gk20a *g,
 	struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header *pset =
 		(struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header *)
 		pboardobjgrppmu;
-	struct clk_freq_controllers *pcntrs =
-		(struct clk_freq_controllers *)pboardobjgrp;
+	struct nvgpu_clk_freq_controllers *pcntrs =
+		(struct nvgpu_clk_freq_controllers *)pboardobjgrp;
 	int status = 0;
 
 	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
@@ -392,12 +392,12 @@ done:
 	return status;
 }
 
-int clk_freq_controller_sw_setup(struct gk20a *g)
+int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g)
 {
 	int status = 0;
 	struct boardobjgrp *pboardobjgrp = NULL;
-	struct clk_freq_controllers *pclk_freq_controllers;
-	struct avfsfllobjs *pfllobjs = &(g->clk_pmu->avfs_fllobjs);
+	struct nvgpu_clk_freq_controllers *pclk_freq_controllers;
+	struct nvgpu_avfsfllobjs *pfllobjs = &(g->clk_pmu->avfs_fllobjs);
 	struct fll_device *pfll;
 	struct clk_freq_controller *pclkfreqctrl;
 	u8 i;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
index da0c425bc..d0f2f1492 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
@@ -36,26 +36,26 @@
 
 static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs);
 static int devinit_get_clk_prog_table(struct gk20a *g,
-	struct clk_progs *pprogobjs);
+	struct nvgpu_clk_progs *pprogobjs);
 static int vfflatten_prog_1x_master(struct gk20a *g,
-				    struct clk_pmupstate *pclk,
+				    struct nvgpu_clk_pmupstate *pclk,
 				    struct clk_prog_1x_master *p1xmaster,
 				    u8 clk_domain_idx, u16 *pfreqmaxlastmhz);
 static int vflookup_prog_1x_master(struct gk20a *g,
-				   struct clk_pmupstate *pclk,
+				   struct nvgpu_clk_pmupstate *pclk,
 				   struct clk_prog_1x_master *p1xmaster,
 				   u8 *slave_clk_domain,
 				   u16 *pclkmhz,
 				   u32 *pvoltuv,
 				   u8 rail);
 static int getfpoints_prog_1x_master(struct gk20a *g,
-				     struct clk_pmupstate *pclk,
+				     struct nvgpu_clk_pmupstate *pclk,
 				     struct clk_prog_1x_master *p1xmaster,
 				     u32 *pfpointscount,
 				     u16 **ppfreqpointsinmhz,
 				     u8 rail);
 static int getslaveclk_prog_1x_master(struct gk20a *g,
-				      struct clk_pmupstate *pclk,
+				      struct nvgpu_clk_pmupstate *pclk,
 				      struct clk_prog_1x_master *p1xmaster,
 				      u8 slave_clk_domain,
 				      u16 *pclkmhz,
@@ -68,7 +68,7 @@ static int _clk_progs_pmudatainit(struct gk20a *g,
 	struct nv_pmu_clk_clk_prog_boardobjgrp_set_header *pset =
 		(struct nv_pmu_clk_clk_prog_boardobjgrp_set_header *)
 		pboardobjgrppmu;
-	struct clk_progs *pprogs = (struct clk_progs *)pboardobjgrp;
+	struct nvgpu_clk_progs *pprogs = (struct nvgpu_clk_progs *)pboardobjgrp;
 	int status = 0;
 
 	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
@@ -107,11 +107,11 @@ static int _clk_progs_pmudata_instget(struct gk20a *g,
 	return 0;
 }
 
-int clk_prog_sw_setup(struct gk20a *g)
+int nvgpu_clk_prog_sw_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
-	struct clk_progs *pclkprogobjs;
+	struct nvgpu_clk_progs *pclkprogobjs;
 
 	nvgpu_log_info(g, " ");
 
@@ -157,7 +157,7 @@ done:
 	return status;
 }
 
-int clk_prog_pmu_setup(struct gk20a *g)
+int nvgpu_clk_prog_pmu_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
@@ -177,7 +177,7 @@ int clk_prog_pmu_setup(struct gk20a *g)
 }
 
 static int devinit_get_clk_prog_table_35(struct gk20a *g,
-					struct clk_progs *pclkprogobjs,
+					struct nvgpu_clk_progs *pclkprogobjs,
 					u8 *clkprogs_tbl_ptr)
 {
 	int status = 0;
@@ -444,7 +444,7 @@ done:
 }
 
 static int devinit_get_clk_prog_table_1x(struct gk20a *g,
-					struct clk_progs *pclkprogobjs,
+					struct nvgpu_clk_progs *pclkprogobjs,
 					u8 *clkprogs_tbl_ptr)
 {
 	int status = 0;
@@ -661,7 +661,7 @@ done:
 }
 
 static int devinit_get_clk_prog_table(struct gk20a *g,
-					struct clk_progs *pprogobjs)
+					struct nvgpu_clk_progs *pprogobjs)
 {
 	int status = 0;
 	u8 *clkprogs_tbl_ptr = NULL;
@@ -912,11 +912,11 @@ static int clk_prog_pmudatainit_35_master_table(struct gk20a *g,
 }
 
 static int _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g,
-						       struct clk_pmupstate *pclk,
-						       struct clk_prog_1x_master *p1xmaster,
-						       struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_rail,
-						       struct clk_vf_point *p_vf_point_tmp,
-						       u8 *p_vf_point_idx)
+			struct nvgpu_clk_pmupstate *pclk,
+			struct clk_prog_1x_master *p1xmaster,
+			struct ctrl_clk_clk_prog_1x_master_vf_entry *p_vf_rail,
+			struct clk_vf_point *p_vf_point_tmp,
+			u8 *p_vf_point_idx)
 {
 	struct clk_vf_point *p_vf_point;
 	int status;
@@ -1362,7 +1362,7 @@ static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs)
 }
 
 static int vfflatten_prog_1x_master(struct gk20a *g,
-				    struct clk_pmupstate *pclk,
+				    struct nvgpu_clk_pmupstate *pclk,
 				    struct clk_prog_1x_master *p1xmaster,
 				    u8 clk_domain_idx, u16 *pfreqmaxlastmhz)
 {
@@ -1478,7 +1478,7 @@ done:
 static int vflookup_prog_1x_master
 (
 	struct gk20a *g,
-	struct clk_pmupstate *pclk,
+	struct nvgpu_clk_pmupstate *pclk,
 	struct clk_prog_1x_master *p1xmaster,
 	u8 *slave_clk_domain,
 	u16 *pclkmhz,
@@ -1490,7 +1490,7 @@ static int vflookup_prog_1x_master
 	struct ctrl_clk_clk_prog_1x_master_vf_entry
 		*pvfentry;
 	struct clk_vf_point *pvfpoint;
-	struct clk_progs *pclkprogobjs;
+	struct nvgpu_clk_progs *pclkprogobjs;
 	struct clk_prog_1x_master_ratio *p1xmasterratio;
 	u16 clkmhz;
 	u32 voltuv;
@@ -1639,7 +1639,7 @@ static int vflookup_prog_1x_master
 static int getfpoints_prog_1x_master
 (
 	struct gk20a *g,
-	struct clk_pmupstate *pclk,
+	struct nvgpu_clk_pmupstate *pclk,
 	struct clk_prog_1x_master *p1xmaster,
 	u32 *pfpointscount,
 	u16 **ppfreqpointsinmhz,
@@ -1650,7 +1650,7 @@ static int getfpoints_prog_1x_master
 	struct ctrl_clk_clk_prog_1x_master_vf_entry
 		*pvfentry;
 	struct clk_vf_point *pvfpoint;
-	struct clk_progs *pclkprogobjs;
+	struct nvgpu_clk_progs *pclkprogobjs;
 	u8 j;
 	u32 fpointscount = 0;
 
@@ -1699,14 +1699,14 @@ done:
 }
 
 static int getslaveclk_prog_1x_master(struct gk20a *g,
-				struct clk_pmupstate *pclk,
+				struct nvgpu_clk_pmupstate *pclk,
 				struct clk_prog_1x_master *p1xmaster,
 				u8 slave_clk_domain,
 				u16 *pclkmhz,
 				u16 masterclkmhz
 )
 {
-	struct clk_progs *pclkprogobjs;
+	struct nvgpu_clk_progs *pclkprogobjs;
 	struct clk_prog_1x_master_ratio *p1xmasterratio;
 	struct clk_prog_35_master_ratio *p35masterratio;
 	u8 slaveentrycount;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h
index 3033449b2..02c3b7a34 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h
@@ -32,21 +32,21 @@
 
 struct clk_prog_1x_master;
 
-typedef int vf_flatten(struct gk20a *g, struct clk_pmupstate *pclk,
+typedef int vf_flatten(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
 			struct clk_prog_1x_master *p1xmaster,
 			u8 clk_domain_idx, u16 *pfreqmaxlastmhz);
 
-typedef int vf_lookup(struct gk20a *g, struct clk_pmupstate *pclk,
+typedef int vf_lookup(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
 			struct clk_prog_1x_master *p1xmaster,
 			u8 *slave_clk_domain_idx, u16 *pclkmhz,
 			u32 *pvoltuv, u8 rail);
 
-typedef int get_slaveclk(struct gk20a *g, struct clk_pmupstate *pclk,
+typedef int get_slaveclk(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
 			struct clk_prog_1x_master *p1xmaster,
 			u8 slave_clk_domain_idx, u16 *pclkmhz,
 			u16 masterclkmhz);
 
-typedef int get_fpoints(struct gk20a *g, struct clk_pmupstate *pclk,
+typedef int get_fpoints(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
 			struct clk_prog_1x_master *p1xmaster,
 			u32 *pfpointscount,
 			u16 **ppfreqpointsinmhz, u8 rail);
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
index 04243c309..8bf8f3cdd 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
@@ -95,7 +95,7 @@ static int _clk_vf_points_pmustatus_instget(struct gk20a *g,
 	return 0;
 }
 
-int clk_vf_point_sw_setup(struct gk20a *g)
+int nvgpu_clk_vf_point_sw_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
@@ -142,7 +142,7 @@ done:
 	return status;
 }
 
-int clk_vf_point_pmu_setup(struct gk20a *g)
+int nvgpu_clk_vf_point_pmu_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
@@ -468,7 +468,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
 	struct nvgpu_pmu *pmu = &g->pmu;
 	struct nv_pmu_rpc_perf_change_seq_queue_change rpc;
 	struct ctrl_perf_change_seq_change_input change_input;
-	struct clk_domain *pclk_domain;
+	struct nvgpu_clk_domain *pclk_domain;
 	int status = 0;
 	u8 i = 0, gpcclk_domain=0;
 	u32 gpcclk_voltuv=0,gpcclk_clkmhz=0;
@@ -480,7 +480,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
 	(void) memset(&change_input, 0,
 		sizeof(struct ctrl_perf_change_seq_change_input));
 	BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs.super.super),
-		struct clk_domain *, pclk_domain, i) {
+		struct nvgpu_clk_domain *, pclk_domain, i) {
 
 		switch (pclk_domain->api_domain) {
 		case CTRL_CLK_DOMAIN_GPCCLK:
@@ -696,7 +696,7 @@ int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq
 int clk_vf_point_cache(struct gk20a *g)
 {
 
-	struct clk_vf_points *pclk_vf_points;
+	struct nvgpu_clk_vf_points *pclk_vf_points;
 	struct boardobjgrp *pboardobjgrp;
 	struct boardobjgrpmask *pboardobjgrpmask;
 	struct nv_pmu_boardobjgrp_super *pboardobjgrppmu;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
index 8d2f04fa5..a21fddeb1 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
@@ -35,7 +35,7 @@
 #include "clk_vin.h"
 
 static int devinit_get_vin_device_table(struct gk20a *g,
-		struct avfsvinobjs *pvinobjs);
+		struct nvgpu_avfsvinobjs *pvinobjs);
 
 static int vin_device_construct_v10(struct gk20a *g,
 					struct boardobj **ppboardobj,
@@ -58,8 +58,8 @@ static int vin_device_init_pmudata_super(struct gk20a *g,
 				  struct boardobj *board_obj_ptr,
 				  struct nv_pmu_boardobj *ppmudata);
 
-int clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
-					struct avfsvinobjs *pvinobjs,
+int nvgpu_clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
+					struct nvgpu_avfsvinobjs *pvinobjs,
 					struct vin_device_v20 *pvindev)
 {
 	int status = 0;
@@ -87,8 +87,8 @@ int clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
 
 }
 
-int clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
-					struct avfsvinobjs *pvinobjs,
+int nvgpu_clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
+					struct nvgpu_avfsvinobjs *pvinobjs,
 					struct vin_device_v20 *pvindev)
 {
 	int status = 0;
@@ -123,7 +123,7 @@ static int _clk_vin_devgrp_pmudatainit_super(struct gk20a *g,
 	struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *pset =
 		(struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *)
 		pboardobjgrppmu;
-	struct avfsvinobjs *pvin_obbj = (struct avfsvinobjs *)pboardobjgrp;
+	struct nvgpu_avfsvinobjs *pvin_obbj = (struct nvgpu_avfsvinobjs *)pboardobjgrp;
 	int status = 0;
 
 	nvgpu_log_info(g, " ");
@@ -179,12 +179,12 @@ static int _clk_vin_devgrp_pmustatus_instget(struct gk20a *g,
 	return 0;
 }
 
-int clk_vin_sw_setup(struct gk20a *g)
+int nvgpu_clk_vin_sw_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
 	struct vin_device_v20 *pvindev = NULL;
-	struct avfsvinobjs *pvinobjs;
+	struct nvgpu_avfsvinobjs *pvinobjs;
 
 	nvgpu_log_info(g, " ");
 
@@ -237,7 +237,7 @@ done:
 	return status;
 }
 
-int clk_vin_pmu_setup(struct gk20a *g)
+int nvgpu_clk_vin_pmu_setup(struct gk20a *g)
 {
 	int status;
 	struct boardobjgrp *pboardobjgrp = NULL;
@@ -257,7 +257,7 @@ int clk_vin_pmu_setup(struct gk20a *g)
 }
 
 static int devinit_get_vin_device_table(struct gk20a *g,
-		struct avfsvinobjs *pvinobjs)
+		struct nvgpu_avfsvinobjs *pvinobjs)
 {
 	int status = 0;
 	u8 *vin_table_ptr = NULL;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h
index 430976ac5..037a32a20 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h
@@ -28,10 +28,10 @@
 #include <nvgpu/boardobjgrp_e32.h>
 
 struct vin_device;
-struct clk_pmupstate;
+struct nvgpu_clk_pmupstate;
 
 typedef u32 vin_device_state_load(struct gk20a *g,
-			struct clk_pmupstate *clk, struct vin_device *pdev);
+			struct nvgpu_clk_pmupstate *clk, struct vin_device *pdev);
 
 struct vin_device {
 	struct boardobj super;
@@ -63,6 +63,4 @@ int construct_vindevice(struct gk20a *g, struct boardobj **ppboardobj,
 int vindeviceinit_pmudata_super(struct gk20a *g, struct boardobj *pboardobj,
 			struct nv_pmu_boardobj *pmudata);
 
-struct avfsvinobjs;
-
 #endif /* NVGPU_CLK_VIN_H */
diff --git a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
index 4c890676d..37bf6d823 100644
--- a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
+++ b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
@@ -27,7 +27,7 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/pmuif/ctrlclk.h>
 #include <nvgpu/pmu/pstate.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 
 #include "pmu_perf.h"
@@ -106,7 +106,7 @@ static void build_change_seq_boot (struct gk20a *g)
 	struct nvgpu_pmu *pmu = &g->pmu;
 	struct change_seq_pmu *perf_change_seq_pmu =
 		&(g->perf_pmu->changeseq_pmu);
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	struct clk_set_info *p0_info;
 	struct change_seq_pmu_script *script_last =
 		&perf_change_seq_pmu->script_last;
@@ -128,7 +128,7 @@ static void build_change_seq_boot (struct gk20a *g)
 	script_last->buf.change.data.flags = CTRL_PERF_CHANGE_SEQ_CHANGE_NONE;
 
 	BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs.super.super),
-		struct clk_domain *, pdomain, i) {
+		struct nvgpu_clk_domain *, pdomain, i) {
 
 		p0_info = pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0,
 			pdomain->domain);
diff --git a/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c b/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c
index 453feb5bd..309fa3790 100644
--- a/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c
+++ b/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c
@@ -25,7 +25,7 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 
 #include "perf_gv100.h"
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index fb24eda35..477e62edb 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -32,7 +32,7 @@
 #include <nvgpu/boardobjgrp.h>
 #include <nvgpu/pmu/pstate.h>
 #include <nvgpu/pmu/volt.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 /* PMU NS UCODE IMG */
 #define NVGPU_PMU_NS_UCODE_IMAGE	"gpmu_ucode.bin"
@@ -1323,7 +1323,7 @@ static int init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu, u32 app_version)
 			g->ops.pmu_ver.clk.get_vbios_clk_domain =
 				nvgpu_clk_get_vbios_clk_domain_gv10x;
 			g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data =
-					clk_avfs_get_vin_cal_fuse_v20;
+					nvgpu_clk_avfs_get_vin_cal_fuse_v20;
 			g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill =
 					nvgpu_clk_vf_change_inject_data_fill_gv10x;
 			if (app_version == APP_VERSION_GV10X) {
@@ -1502,7 +1502,7 @@ static int init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu, u32 app_version)
 		g->ops.pmu_ver.clk.get_vbios_clk_domain =
 			nvgpu_clk_get_vbios_clk_domain_gp10x;
 		g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data =
-				clk_avfs_get_vin_cal_fuse_v10;
+				nvgpu_clk_avfs_get_vin_cal_fuse_v10;
 		g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill =
 				nvgpu_clk_vf_change_inject_data_fill_gp10x;
 		break;
diff --git a/drivers/gpu/nvgpu/common/pmu/pstate/pstate.c b/drivers/gpu/nvgpu/common/pmu/pstate/pstate.c
index fa1510300..b9ee383be 100644
--- a/drivers/gpu/nvgpu/common/pmu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/common/pmu/pstate/pstate.c
@@ -25,7 +25,7 @@
 #include <nvgpu/bios.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pmu.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/pmgr.h>
 #include <nvgpu/pmu/therm.h>
 #include <nvgpu/pmu/perf.h>
@@ -39,7 +39,7 @@ void gk20a_deinit_pstate_support(struct gk20a *g)
 	pmgr_pmu_free_pmupstate(g);
 	therm_pmu_free_pmupstate(g);
 	perf_pmu_free_pmupstate(g);
-	clk_free_pmupstate(g);
+	nvgpu_clk_free_pmupstate(g);
 
 	if (g->ops.clk.mclk_deinit != NULL) {
 		g->ops.clk.mclk_deinit(g);
@@ -59,7 +59,7 @@ int gk20a_init_pstate_support(struct gk20a *g)
 		return err;
 	}
 
-	err = clk_init_pmupstate(g);
+	err = nvgpu_clk_init_pmupstate(g);
 	if (err != 0) {
 		return err;
 	}
@@ -94,12 +94,12 @@ int gk20a_init_pstate_support(struct gk20a *g)
 		goto err_pmgr_pmu_init_pmupstate;
 	}
 
-	err = clk_vin_sw_setup(g);
+	err = nvgpu_clk_vin_sw_setup(g);
 	if (err != 0) {
 		goto err_pmgr_pmu_init_pmupstate;
 	}
 
-	err = clk_fll_sw_setup(g);
+	err = nvgpu_clk_fll_sw_setup(g);
 	if (err != 0) {
 		goto err_pmgr_pmu_init_pmupstate;
 	}
@@ -121,20 +121,20 @@ int gk20a_init_pstate_support(struct gk20a *g)
 		}
 	}
 
-	err = clk_domain_sw_setup(g);
+	err = nvgpu_clk_domain_sw_setup(g);
 	if (err != 0) {
 		goto err_pmgr_pmu_init_pmupstate;
 	}
 
 	if (g->ops.clk.support_vf_point &&
 		g->ops.pmu_perf.support_vfe) {
-		err = clk_vf_point_sw_setup(g);
+		err = nvgpu_clk_vf_point_sw_setup(g);
 		if (err != 0) {
 			goto err_pmgr_pmu_init_pmupstate;
 		}
 	}
 
-	err = clk_prog_sw_setup(g);
+	err = nvgpu_clk_prog_sw_setup(g);
 	if (err != 0) {
 		goto err_pmgr_pmu_init_pmupstate;
 	}
@@ -159,7 +159,7 @@ int gk20a_init_pstate_support(struct gk20a *g)
 	}
 
 	if (g->ops.clk.support_clk_freq_controller) {
-		err = clk_freq_controller_sw_setup(g);
+		err = nvgpu_clk_freq_controller_sw_setup(g);
 		if (err != 0) {
 			goto err_pmgr_pmu_init_pmupstate;
 		}
@@ -188,7 +188,7 @@ err_therm_pmu_init_pmupstate:
 err_perf_pmu_init_pmupstate:
 	perf_pmu_free_pmupstate(g);
 err_clk_init_pmupstate:
-	clk_free_pmupstate(g);
+	nvgpu_clk_free_pmupstate(g);
 
 	return err;
 }
@@ -248,17 +248,17 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
 		}
 	}
 
-	err = clk_domain_pmu_setup(g);
+	err = nvgpu_clk_domain_pmu_setup(g);
 	if (err != 0) {
 		return err;
 	}
 
-	err = clk_prog_pmu_setup(g);
+	err = nvgpu_clk_prog_pmu_setup(g);
 	if (err != 0) {
 		return err;
 	}
 
-	err = clk_vin_pmu_setup(g);
+	err = nvgpu_clk_vin_pmu_setup(g);
 	if (err != 0) {
 		return err;
 	}
@@ -270,13 +270,13 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
 		}
 	}
 
-	err = clk_fll_pmu_setup(g);
+	err = nvgpu_clk_fll_pmu_setup(g);
 	if (err != 0) {
 		return err;
 	}
 
 	if (g->ops.clk.support_clk_freq_controller) {
-		err = clk_freq_controller_pmu_setup(g);
+		err = nvgpu_clk_freq_controller_pmu_setup(g);
 		if (err != 0) {
 			return err;
 		}
@@ -284,19 +284,19 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
 
 	if (g->ops.clk.support_vf_point &&
 		g->ops.pmu_perf.support_vfe) {
-		err = clk_vf_point_pmu_setup(g);
+		err = nvgpu_clk_vf_point_pmu_setup(g);
 		if (err != 0) {
 			return err;
 		}
 	}
 
-	err = clk_pmu_vin_load(g);
+	err = nvgpu_clk_pmu_vin_load(g);
 	if (err != 0) {
 		return err;
 	}
 
 	if (g->ops.clk.support_clk_freq_domain) {
-		err = clk_pmu_clk_domains_load(g);
+		err = nvgpu_clk_pmu_clk_domains_load(g);
 		if (err != 0) {
 			return err;
 		}
@@ -406,9 +406,9 @@ static int parse_pstate_entry_5x(struct gk20a *g,
 	for (clkidx = 0; clkidx < hdr->clock_entry_count; clkidx++) {
 		struct clk_set_info *pclksetinfo;
 		struct vbios_pstate_entry_clock_5x *clk_entry;
-		struct clk_domain *clk_domain;
+		struct nvgpu_clk_domain *clk_domain;
 
-		clk_domain = (struct clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(
+		clk_domain = (struct nvgpu_clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(
 			    &g->clk_pmu->clk_domainobjs.super.super, clkidx);
 
 		pclksetinfo = &pstate->clklist.clksetinfo[clkidx];
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index 1db73c5b4..be576fe25 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -256,9 +256,9 @@ int gp106_clk_domain_get_f_points(
 	u16 *pfreqpointsinmhz)
 {
 	int status = -EINVAL;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	u8 i;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 
 	if (pfpointscount == NULL) {
 		return -EINVAL;
@@ -269,7 +269,7 @@ int gp106_clk_domain_get_f_points(
 	}
 
 	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
-			struct clk_domain *, pdomain, i) {
+			struct nvgpu_clk_domain *, pdomain, i) {
 		if (pdomain->api_domain == clkapidomain) {
 			status = pdomain->clkdomainclkgetfpoints(g, pclk,
 				pdomain, pfpointscount,
diff --git a/drivers/gpu/nvgpu/gv100/clk_arb_gv100.c b/drivers/gpu/nvgpu/gv100/clk_arb_gv100.c
index 491b2c722..0bf0212db 100644
--- a/drivers/gpu/nvgpu/gv100/clk_arb_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/clk_arb_gv100.c
@@ -22,7 +22,7 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/clk_arb.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/timers.h>
 
 #include "clk_arb_gv100.h"
@@ -57,7 +57,7 @@ int gv100_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
 {
 	u32 clkwhich;
 	struct clk_set_info *p0_info;
-	struct avfsfllobjs *pfllobjs =  &(g->clk_pmu->avfs_fllobjs);
+	struct nvgpu_avfsfllobjs *pfllobjs =  &(g->clk_pmu->avfs_fllobjs);
 	u16 limit_min_mhz;
 	bool error_status = false;
 
@@ -412,7 +412,7 @@ static int nvgpu_clk_arb_change_vf_point(struct gk20a *g, u16 gpc2clk_target,
 	u16 sys2clk_target, u16 xbar2clk_target, u16 mclk_target, u32 voltuv,
 	u32 voltuv_sram)
 {
-	struct set_fll_clk fllclk;
+	struct nvgpu_set_fll_clk fllclk;
 	struct nvgpu_clk_arb *arb = g->clk_arb;
 	int status;
 
diff --git a/drivers/gpu/nvgpu/gv100/clk_gv100.c b/drivers/gpu/nvgpu/gv100/clk_gv100.c
index 31d4f4e0e..2b1c838fd 100644
--- a/drivers/gpu/nvgpu/gv100/clk_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/clk_gv100.c
@@ -34,7 +34,7 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/clk.h>
-#include <nvgpu/pmu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "clk_gv100.h"
 
@@ -210,9 +210,9 @@ int gv100_clk_domain_get_f_points(
 	u16 *pfreqpointsinmhz)
 {
 	int status = -EINVAL;
-	struct clk_domain *pdomain;
+	struct nvgpu_clk_domain *pdomain;
 	u8 i;
-	struct clk_pmupstate *pclk = g->clk_pmu;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
 	if (pfpointscount == NULL) {
 		return -EINVAL;
 	}
@@ -221,7 +221,7 @@ int gv100_clk_domain_get_f_points(
 		return -EINVAL;
 	}
 	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super),
-			struct clk_domain *, pdomain, i) {
+			struct nvgpu_clk_domain *, pdomain, i) {
 		if (pdomain->api_domain == clkapidomain) {
 			status = pdomain->clkdomainclkgetfpoints(g, pclk,
 				pdomain, pfpointscount,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 2d9c2116e..83b39503d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -51,11 +51,11 @@ struct nvgpu_gpu_ctxsw_trace_filter;
 #endif
 struct priv_cmd_entry;
 struct nvgpu_setup_bind_args;
-struct clk_pmupstate;
+struct nvgpu_clk_pmupstate;
 struct perf_pmupstate;
 struct vin_device_v20;
-struct avfsvinobjs;
-struct set_fll_clk;
+struct nvgpu_avfsvinobjs;
+struct nvgpu_set_fll_clk;
 struct boardobjgrp;
 struct boardobjgrp_pmu_cmd;
 struct boardobjgrpmask;
@@ -1048,11 +1048,11 @@ struct gpu_ops {
 		struct {
 			u32 (*get_vbios_clk_domain)(u32 vbios_domain);
 			int (*clk_avfs_get_vin_cal_data)(struct gk20a *g,
-				struct avfsvinobjs *pvinobjs,
+				struct nvgpu_avfsvinobjs *pvinobjs,
 				struct vin_device_v20 *pvindev);
 			u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g,
 				struct nv_pmu_clk_rpc *rpccall,
-				struct set_fll_clk *setfllclk);
+				struct nvgpu_set_fll_clk *setfllclk);
 			int (*clk_set_boot_clk)(struct gk20a *g);
 		}clk;
 	} pmu_ver;
@@ -1704,7 +1704,7 @@ struct gk20a {
 	struct nvgpu_pmu pmu;
 	struct nvgpu_acr acr;
 	struct nvgpu_ecc ecc;
-	struct clk_pmupstate *clk_pmu;
+	struct nvgpu_clk_pmupstate *clk_pmu;
 	struct perf_pmupstate *perf_pmu;
 	struct pmgr_pmupstate *pmgr_pmu;
 	struct therm_pmupstate *therm_pmu;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk.h
deleted file mode 100644
index bbf549db3..000000000
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * general clock structures & definitions
- *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_PMU_CLK_H
-#define NVGPU_PMU_CLK_H
-
-#include <nvgpu/boardobjgrp_e32.h>
-#include <nvgpu/boardobjgrp_e255.h>
-#include <nvgpu/boardobjgrpmask.h>
-#include <nvgpu/types.h>
-#include <nvgpu/pmuif/ctrlclk.h>
-
-struct clk_domain;
-struct gk20a;
-
-/* clock related defines for GPUs supporting clock control from pmu*/
-struct avfsvinobjs {
-	struct boardobjgrp_e32 super;
-	u8 calibration_rev_vbios;
-	u8 calibration_rev_fused;
-	bool vin_is_disable_allowed;
-};
-
-struct avfsfllobjs {
-	struct boardobjgrp_e32 super;
-	struct boardobjgrpmask_e32 lut_prog_master_mask;
-	u32 lut_step_size_uv;
-	u32 lut_min_voltage_uv;
-	u8 lut_num_entries;
-	u16 max_min_freq_mhz;
-};
-
-typedef int clkproglink(struct gk20a *g, struct clk_pmupstate *pclk,
-			struct clk_domain *pdomain);
-
-typedef int clkvfsearch(struct gk20a *g, struct clk_pmupstate *pclk,
-			struct clk_domain *pdomain, u16 *clkmhz,
-			u32 *voltuv, u8 rail);
-
-typedef int clkgetfpoints(struct gk20a *g, struct clk_pmupstate *pclk,
-			struct clk_domain *pdomain, u32 *pfpointscount,
-			  u16 *pfreqpointsinmhz, u8 rail);
-
-struct clk_domain {
-	struct boardobj super;
-	u32 api_domain;
-	u32 part_mask;
-	u32 domain;
-	u8 perf_domain_index;
-	u8 perf_domain_grp_idx;
-	u8 ratio_domain;
-	u8 usage;
-	clkproglink *clkdomainclkproglink;
-	clkvfsearch *clkdomainclkvfsearch;
-	clkgetfpoints *clkdomainclkgetfpoints;
-};
-
-struct clk_domains {
-	struct boardobjgrp_e32 super;
-	u8 n_num_entries;
-	u8 version;
-	bool b_enforce_vf_monotonicity;
-	bool b_enforce_vf_smoothening;
-	bool b_override_o_v_o_c;
-	bool b_debug_mode;
-	u32 vbios_domains;
-	u16 cntr_sampling_periodms;
-	struct boardobjgrpmask_e32 prog_domains_mask;
-	struct boardobjgrpmask_e32 master_domains_mask;
-	struct ctrl_clk_clk_delta  deltas;
-
-	struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
-
-	struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
-};
-
-struct clk_progs {
-	struct boardobjgrp_e255 super;
-	u8 slave_entry_count;
-	u8 vf_entry_count;
-	u8 vf_sec_entry_count;
-};
-
-struct clk_vf_points {
-	struct boardobjgrp_e255 super;
-};
-
-struct clk_mclk_state {
-	u32 speed;
-	struct nvgpu_mutex mclk_lock;
-	struct nvgpu_mutex data_lock;
-
-	u16 p5_min;
-	u16 p0_min;
-
-	void *vreg_buf;
-	bool init;
-
-	s64 switch_max;
-	s64 switch_min;
-	u64 switch_num;
-	s64 switch_avg;
-	s64 switch_std;
-	bool debugfs_set;
-};
-
-struct clk_freq_controllers {
-	struct boardobjgrp_e32 super;
-	u32 sampling_period_ms;
-	struct boardobjgrpmask_e32 freq_ctrl_load_mask;
-	u8 volt_policy_idx;
-	void *pprereq_load;
-};
-
-struct nvgpu_clk_freq_domain_grp {
-	struct boardobjgrp_e32 super;
-	u32 init_flags;
-};
-
-struct clk_pmupstate {
-	struct avfsvinobjs avfs_vinobjs;
-	struct avfsfllobjs avfs_fllobjs;
-	struct clk_domains clk_domainobjs;
-	struct clk_progs clk_progobjs;
-	struct clk_vf_points clk_vf_pointobjs;
-	struct clk_mclk_state clk_mclk;
-	struct clk_freq_controllers clk_freq_controllers;
-	struct nvgpu_clk_freq_domain_grp freq_domain_grp_objs;
-};
-
-struct set_fll_clk {
-		u32 voltuv;
-		u16 gpc2clkmhz;
-		u8 current_regime_id_gpc;
-		u8 target_regime_id_gpc;
-		u16 sys2clkmhz;
-		u8 current_regime_id_sys;
-		u8 target_regime_id_sys;
-		u16 xbar2clkmhz;
-		u8 current_regime_id_xbar;
-		u8 target_regime_id_xbar;
-		u16 nvdclkmhz;
-		u8 current_regime_id_nvd;
-		u8 target_regime_id_nvd;
-		u16 hostclkmhz;
-		u8 current_regime_id_host;
-		u8 target_regime_id_host;
-};
-
-int clk_init_pmupstate(struct gk20a *g);
-void clk_free_pmupstate(struct gk20a *g);
-int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g);
-int clk_pmu_vin_load(struct gk20a *g);
-int clk_pmu_clk_domains_load(struct gk20a *g);
-u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
-	struct nv_pmu_clk_rpc *rpccall,
-	struct set_fll_clk *setfllclk);
-u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
-	struct nv_pmu_clk_rpc *rpccall,
-	struct set_fll_clk *setfllclk);
-int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
-int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g);
-
-int clk_vin_sw_setup(struct gk20a *g);
-int clk_vin_pmu_setup(struct gk20a *g);
-int clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
-					struct avfsvinobjs *pvinobjs,
-					struct vin_device_v20 *pvindev);
-int clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
-					struct avfsvinobjs *pvinobjs,
-					struct vin_device_v20 *pvindev);
-
-/*data and function definition to talk to driver*/
-int clk_fll_sw_setup(struct gk20a *g);
-int clk_fll_pmu_setup(struct gk20a *g);
-u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain);
-u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain);
-
-/*data and function definition to talk to driver*/
-int clk_domain_sw_setup(struct gk20a *g);
-int clk_domain_pmu_setup(struct gk20a *g);
-
-int clk_vf_point_sw_setup(struct gk20a *g);
-int clk_vf_point_pmu_setup(struct gk20a *g);
-
-int clk_prog_sw_setup(struct gk20a *g);
-int clk_prog_pmu_setup(struct gk20a *g);
-
-int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g);
-int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g);
-
-int clk_freq_controller_sw_setup(struct gk20a *g);
-int clk_freq_controller_pmu_setup(struct gk20a *g);
-
-#endif /* NVGPU_PMU_CLK_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
new file mode 100644
index 000000000..cdb9fa18f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
@@ -0,0 +1,56 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_H
+#define NVGPU_PMU_CLK_H
+
+#include <nvgpu/pmu/clk/clk_vin.h>
+#include <nvgpu/pmu/clk/clk_fll.h>
+#include <nvgpu/pmu/clk/clk_domain.h>
+#include <nvgpu/pmu/clk/clk_prog.h>
+#include <nvgpu/pmu/clk/clk_vf_point.h>
+#include <nvgpu/pmu/clk/clk_mclk.h>
+#include <nvgpu/pmu/clk/clk_freq_controller.h>
+#include <nvgpu/pmu/clk/clk_freq_domain.h>
+
+struct gk20a;
+
+struct nvgpu_clk_pmupstate {
+	struct nvgpu_avfsvinobjs avfs_vinobjs;
+	struct nvgpu_avfsfllobjs avfs_fllobjs;
+	struct nvgpu_clk_domains clk_domainobjs;
+	struct nvgpu_clk_progs clk_progobjs;
+	struct nvgpu_clk_vf_points clk_vf_pointobjs;
+	struct nvgpu_clk_mclk_state clk_mclk;
+	struct nvgpu_clk_freq_controllers clk_freq_controllers;
+	struct nvgpu_clk_freq_domain_grp freq_domain_grp_objs;
+};
+
+int nvgpu_clk_init_pmupstate(struct gk20a *g);
+void nvgpu_clk_free_pmupstate(struct gk20a *g);
+int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g);
+int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
+int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h
new file mode 100644
index 000000000..d9f8ea6a9
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h
@@ -0,0 +1,87 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_DOMAIN_H
+#define NVGPU_PMU_CLK_DOMAIN_H
+
+#include <nvgpu/boardobjgrp_e32.h>
+#include <nvgpu/boardobjgrpmask.h>
+#include <nvgpu/types.h>
+#include <nvgpu/pmuif/ctrlclk.h>
+#include <nvgpu/pmu/clk/clk.h>
+
+struct gk20a;
+struct nvgpu_clk_domain;
+
+typedef int nvgpu_clkproglink(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
+			struct nvgpu_clk_domain *pdomain);
+
+typedef int nvgpu_clkvfsearch(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
+			struct nvgpu_clk_domain *pdomain, u16 *clkmhz,
+			u32 *voltuv, u8 rail);
+
+typedef int nvgpu_clkgetfpoints(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,
+			struct nvgpu_clk_domain *pdomain, u32 *pfpointscount,
+			  u16 *pfreqpointsinmhz, u8 rail);
+
+struct nvgpu_clk_domain {
+	struct boardobj super;
+	u32 api_domain;
+	u32 part_mask;
+	u32 domain;
+	u8 perf_domain_index;
+	u8 perf_domain_grp_idx;
+	u8 ratio_domain;
+	u8 usage;
+	nvgpu_clkproglink *clkdomainclkproglink;
+	nvgpu_clkvfsearch *clkdomainclkvfsearch;
+	nvgpu_clkgetfpoints *clkdomainclkgetfpoints;
+};
+
+struct nvgpu_clk_domains {
+	struct boardobjgrp_e32 super;
+	u8 n_num_entries;
+	u8 version;
+	bool b_enforce_vf_monotonicity;
+	bool b_enforce_vf_smoothening;
+	bool b_override_o_v_o_c;
+	bool b_debug_mode;
+	u32 vbios_domains;
+	u16 cntr_sampling_periodms;
+	struct boardobjgrpmask_e32 prog_domains_mask;
+	struct boardobjgrpmask_e32 master_domains_mask;
+	struct ctrl_clk_clk_delta  deltas;
+
+	struct nvgpu_clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+
+	struct nvgpu_clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+};
+
+int nvgpu_clk_pmu_clk_domains_load(struct gk20a *g);
+u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain);
+u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain);
+int nvgpu_clk_domain_sw_setup(struct gk20a *g);
+int nvgpu_clk_domain_pmu_setup(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_DOMAIN_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h
new file mode 100644
index 000000000..2407b881d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h
@@ -0,0 +1,65 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_FLL_H
+#define NVGPU_PMU_CLK_FLL_H
+
+#include <nvgpu/boardobjgrp_e32.h>
+#include <nvgpu/boardobjgrpmask.h>
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+struct nvgpu_avfsfllobjs {
+	struct boardobjgrp_e32 super;
+	struct boardobjgrpmask_e32 lut_prog_master_mask;
+	u32 lut_step_size_uv;
+	u32 lut_min_voltage_uv;
+	u8 lut_num_entries;
+	u16 max_min_freq_mhz;
+};
+
+struct nvgpu_set_fll_clk {
+	u32 voltuv;
+	u16 gpc2clkmhz;
+	u8 current_regime_id_gpc;
+	u8 target_regime_id_gpc;
+	u16 sys2clkmhz;
+	u8 current_regime_id_sys;
+	u8 target_regime_id_sys;
+	u16 xbar2clkmhz;
+	u8 current_regime_id_xbar;
+	u8 target_regime_id_xbar;
+	u16 nvdclkmhz;
+	u8 current_regime_id_nvd;
+	u8 target_regime_id_nvd;
+	u16 hostclkmhz;
+	u8 current_regime_id_host;
+	u8 target_regime_id_host;
+};
+
+int nvgpu_clk_fll_sw_setup(struct gk20a *g);
+int nvgpu_clk_fll_pmu_setup(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_FLL_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h
new file mode 100644
index 000000000..4603d3952
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h
@@ -0,0 +1,45 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_FREQ_CONTROLLER_H
+#define NVGPU_PMU_CLK_FREQ_CONTROLLER_H
+
+#include <nvgpu/boardobjgrp_e32.h>
+#include <nvgpu/boardobjgrpmask.h>
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+struct nvgpu_clk_freq_controllers {
+	struct boardobjgrp_e32 super;
+	u32 sampling_period_ms;
+	struct boardobjgrpmask_e32 freq_ctrl_load_mask;
+	u8 volt_policy_idx;
+	void *pprereq_load;
+};
+
+int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g);
+int nvgpu_clk_freq_controller_pmu_setup(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_FREQ_CONTROLLER_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h
new file mode 100644
index 000000000..2d8ff5d01
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h
@@ -0,0 +1,39 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_FREQ_DOMAIN_H
+#define NVGPU_PMU_CLK_FREQ_DOMAIN_H
+
+#include <nvgpu/boardobjgrp_e32.h>
+#include <nvgpu/types.h>
+
+struct nvgpu_clk_freq_domain_grp {
+	struct boardobjgrp_e32 super;
+	u32 init_flags;
+};
+
+int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g);
+int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_FREQ_DOMAIN_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_mclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_mclk.h
new file mode 100644
index 000000000..8cf7f63e5
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_mclk.h
@@ -0,0 +1,46 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_MCLK_H_
+#define NVGPU_PMU_CLK_MCLK_H_
+
+#include <nvgpu/lock.h>
+
+struct nvgpu_clk_mclk_state {
+	u32 speed;
+	struct nvgpu_mutex mclk_lock;
+	struct nvgpu_mutex data_lock;
+	u16 p5_min;
+	u16 p0_min;
+	void *vreg_buf;
+	bool init;
+	s64 switch_max;
+	s64 switch_min;
+	u64 switch_num;
+	s64 switch_avg;
+	s64 switch_std;
+	bool debugfs_set;
+};
+
+#endif /* NVGPU_PMU_CLK_MCLK_H_ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_prog.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_prog.h
new file mode 100644
index 000000000..22f55d0fd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_prog.h
@@ -0,0 +1,43 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_PROG_H
+#define NVGPU_PMU_CLK_PROG_H
+
+#include <nvgpu/boardobjgrp_e255.h>
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+struct nvgpu_clk_progs {
+	struct boardobjgrp_e255 super;
+	u8 slave_entry_count;
+	u8 vf_entry_count;
+	u8 vf_sec_entry_count;
+};
+
+int nvgpu_clk_prog_sw_setup(struct gk20a *g);
+int nvgpu_clk_prog_pmu_setup(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_PROG_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h
new file mode 100644
index 000000000..3b2a3ada4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h
@@ -0,0 +1,48 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_VF_POINT_H
+#define NVGPU_PMU_CLK_VF_POINT_H
+
+#include <nvgpu/boardobjgrp_e255.h>
+#include <nvgpu/pmuif/gpmuifclk.h>
+#include <nvgpu/types.h>
+#include <nvgpu/pmu/clk/clk_fll.h>
+
+struct gk20a;
+
+struct nvgpu_clk_vf_points {
+	struct boardobjgrp_e255 super;
+};
+
+u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
+	struct nv_pmu_clk_rpc *rpccall,
+	struct nvgpu_set_fll_clk *setfllclk);
+u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
+	struct nv_pmu_clk_rpc *rpccall,
+	struct nvgpu_set_fll_clk *setfllclk);
+int nvgpu_clk_vf_point_sw_setup(struct gk20a *g);
+int nvgpu_clk_vf_point_pmu_setup(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_VF_POINT_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h
new file mode 100644
index 000000000..0253388e0
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h
@@ -0,0 +1,51 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_PMU_CLK_VIN_H
+#define NVGPU_PMU_CLK_VIN_H
+
+#include <nvgpu/boardobjgrp_e32.h>
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct vin_device_v20;
+
+struct nvgpu_avfsvinobjs {
+	struct boardobjgrp_e32 super;
+	u8 calibration_rev_vbios;
+	u8 calibration_rev_fused;
+	bool vin_is_disable_allowed;
+};
+
+int nvgpu_clk_pmu_vin_load(struct gk20a *g);
+int nvgpu_clk_vin_sw_setup(struct gk20a *g);
+int nvgpu_clk_vin_pmu_setup(struct gk20a *g);
+int nvgpu_clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
+	struct nvgpu_avfsvinobjs *pvinobjs,
+	struct vin_device_v20 *pvindev);
+int nvgpu_clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
+	struct nvgpu_avfsvinobjs *pvinobjs,
+	struct vin_device_v20 *pvindev);
+
+#endif /* NVGPU_PMU_CLK_VIN_H */