From 8ddc70f4f747a3833dd482d6280fadfc3000e793 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 13 Dec 2018 14:46:52 -0800 Subject: [PATCH] gpu: nvgpu: Split lpwr.h into private and public lpwr/lpwr.h and lpwr/rppg.h are used both by lpwr itself, and other units calling lpwr. Move all public dependencies to include/nvgpu/pmu/lpwr.h JIRA NVGPU-961 Change-Id: I033684c3662943758d291e73c4f2642053c35091 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1986068 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk_arb.c | 2 +- drivers/gpu/nvgpu/common/pmu/pmu_gp106.c | 4 +- drivers/gpu/nvgpu/include/nvgpu/clk_arb.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h | 103 +++++++++++++++++++++ drivers/gpu/nvgpu/lpwr/lpwr.h | 81 ++-------------- drivers/gpu/nvgpu/lpwr/rppg.c | 2 +- drivers/gpu/nvgpu/lpwr/rppg.h | 26 ------ drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c | 2 +- drivers/gpu/nvgpu/pmu_perf/pmu_perf.h | 2 +- 9 files changed, 115 insertions(+), 109 deletions(-) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h delete mode 100644 drivers/gpu/nvgpu/lpwr/rppg.h diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index 689be04bb..6a86ba714 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c @@ -35,9 +35,9 @@ #include #include #include +#include #include "clk/clk.h" -#include "lpwr/lpwr.h" int nvgpu_clk_notification_queue_alloc(struct gk20a *g, struct nvgpu_clk_notification_queue *queue, diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c index 536e88e16..6d1f348ee 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "pmu_gk20a.h" #include "acr_gm20b.h" @@ -35,9 +36,6 @@ #include "clk/clk_mclk.h" -#include "lpwr/lpwr.h" -#include "lpwr/rppg.h" - #include #include diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h index e643a2415..0bfb44d17 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h +++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h @@ -37,9 +37,9 @@ struct gk20a; #include #include #include +#include #include "clk/clk.h" -#include "lpwr/lpwr.h" #define MAX_F_POINTS 256 #define DEFAULT_EVENT_NUMBER 32 diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h new file mode 100644 index 000000000..332e1b6b9 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_PMU_LPWR_H +#define NVGPU_PMU_LPWR_H + +#include + +struct gk20a; + +#define LPWR_ENTRY_COUNT_MAX 0x06U + +#define LPWR_VBIOS_IDX_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) + +#define LPWR_VBIOS_IDX_ENTRY_RSVD \ + (LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1U) + +#define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT (500U) + +struct nvgpu_lpwr_bios_idx_entry { + u8 pcie_idx; + u8 gr_idx; + u8 ms_idx; + u8 di_idx; + u8 gc6_idx; +}; + +struct nvgpu_lpwr_bios_idx_data { + u16 base_sampling_period; + struct nvgpu_lpwr_bios_idx_entry entry[LPWR_VBIOS_IDX_ENTRY_COUNT_MAX]; +}; + +#define LPWR_VBIOS_MS_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) + +struct nvgpu_lpwr_bios_ms_entry { + bool ms_enabled; + u32 feature_mask; + u32 asr_efficiency_thresholdl; + u16 dynamic_current_logic; + u16 dynamic_current_sram; +}; + +struct nvgpu_lpwr_bios_ms_data { + u8 default_entry_idx; + u32 idle_threshold_us; + struct nvgpu_lpwr_bios_ms_entry entry[LPWR_VBIOS_MS_ENTRY_COUNT_MAX]; +}; + +#define LPWR_VBIOS_GR_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) + +struct nvgpu_lpwr_bios_gr_entry { + bool gr_enabled; + u32 feature_mask; +}; + +struct nvgpu_lpwr_bios_gr_data { + u8 default_entry_idx; + u32 idle_threshold_us; + u8 adaptive_gr_multiplier; + struct nvgpu_lpwr_bios_gr_entry entry[LPWR_VBIOS_GR_ENTRY_COUNT_MAX]; +}; + +struct nvgpu_lpwr_bios_data { + struct nvgpu_lpwr_bios_idx_data idx; + struct nvgpu_lpwr_bios_ms_data ms; + struct nvgpu_lpwr_bios_gr_data gr; +}; + +struct obj_lwpr { + struct nvgpu_lpwr_bios_data lwpr_bios_data; + u32 mclk_change_cache; +}; + +int nvgpu_lpwr_pg_setup(struct gk20a *g); + +int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate); +int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock); +int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock); +bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num); +bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); +u32 nvgpu_lpwr_post_init(struct gk20a *g); + +int init_rppg(struct gk20a *g); + +#endif /* NVGPU_PMU_LPWR_H */ diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.h b/drivers/gpu/nvgpu/lpwr/lpwr.h index 9c0a123f6..4431d9262 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.h +++ b/drivers/gpu/nvgpu/lpwr/lpwr.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,83 +19,14 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#ifndef NVGPU_LPWR_H -#define NVGPU_LPWR_H +#ifndef NVGPU_LPWR_LPWR_H +#define NVGPU_LPWR_LPWR_H + +#include #define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540U #define NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED BIT32(0x1) #define NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED BIT32(0x3) -#define LPWR_ENTRY_COUNT_MAX 0x06U - -#define LPWR_VBIOS_IDX_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) - -#define LPWR_VBIOS_IDX_ENTRY_RSVD \ - (LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1U) - -#define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT (500U) - -struct nvgpu_lpwr_bios_idx_entry { - u8 pcie_idx; - u8 gr_idx; - u8 ms_idx; - u8 di_idx; - u8 gc6_idx; -}; - -struct nvgpu_lpwr_bios_idx_data { - u16 base_sampling_period; - struct nvgpu_lpwr_bios_idx_entry entry[LPWR_VBIOS_IDX_ENTRY_COUNT_MAX]; -}; - -#define LPWR_VBIOS_MS_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) - -struct nvgpu_lpwr_bios_ms_entry { - bool ms_enabled; - u32 feature_mask; - u32 asr_efficiency_thresholdl; - u16 dynamic_current_logic; - u16 dynamic_current_sram; -}; - -struct nvgpu_lpwr_bios_ms_data { - u8 default_entry_idx; - u32 idle_threshold_us; - struct nvgpu_lpwr_bios_ms_entry entry[LPWR_VBIOS_MS_ENTRY_COUNT_MAX]; -}; - -#define LPWR_VBIOS_GR_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) - -struct nvgpu_lpwr_bios_gr_entry { - bool gr_enabled; - u32 feature_mask; -}; - -struct nvgpu_lpwr_bios_gr_data { - u8 default_entry_idx; - u32 idle_threshold_us; - u8 adaptive_gr_multiplier; - struct nvgpu_lpwr_bios_gr_entry entry[LPWR_VBIOS_GR_ENTRY_COUNT_MAX]; -}; - -struct nvgpu_lpwr_bios_data { - struct nvgpu_lpwr_bios_idx_data idx; - struct nvgpu_lpwr_bios_ms_data ms; - struct nvgpu_lpwr_bios_gr_data gr; -}; - -struct obj_lwpr { - struct nvgpu_lpwr_bios_data lwpr_bios_data; - u32 mclk_change_cache; -}; - -int nvgpu_lpwr_pg_setup(struct gk20a *g); -int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate); -int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock); -int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock); -bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num); -bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); -u32 nvgpu_lpwr_post_init(struct gk20a *g); - -#endif /* NVGPU_LPWR_H */ +#endif /* NVGPU_LPWR_LPWR_H */ diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c index e78d09dea..cef5ad131 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/lpwr/rppg.c @@ -23,9 +23,9 @@ #include #include #include +#include #include "gp106/bios_gp106.h" -#include "lpwr/rppg.h" static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, void *param, u32 handle, u32 status) diff --git a/drivers/gpu/nvgpu/lpwr/rppg.h b/drivers/gpu/nvgpu/lpwr/rppg.h deleted file mode 100644 index 0a0d41518..000000000 --- a/drivers/gpu/nvgpu/lpwr/rppg.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_LPWR_RPPG_H -#define NVGPU_LPWR_RPPG_H - -int init_rppg(struct gk20a *g); -#endif /* NVGPU_LPWR_RPPG_H */ diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c index cb5f74c41..443bf3fe1 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c @@ -39,9 +39,9 @@ #include #include #include +#include #include "clk/clk.h" -#include "lpwr/lpwr.h" #ifdef CONFIG_DEBUG_FS #include "os_linux.h" diff --git a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h index f736c2a2a..07a4a372e 100644 --- a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h +++ b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h @@ -24,11 +24,11 @@ #include #include +#include #include #include "vfe_equ.h" #include "vfe_var.h" -#include "lpwr/lpwr.h" #include "change_seq.h" #define CTRL_PERF_VFE_VAR_TYPE_INVALID 0x00U