diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk index 2c100cc48..0c4bfc06d 100644 --- a/Makefile.umbrella.tmk +++ b/Makefile.umbrella.tmk @@ -51,6 +51,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/interface/bsearch NV_REPOSITORY_COMPONENTS += userspace/units/interface/lock NV_REPOSITORY_COMPONENTS += userspace/units/interface/atomic NV_REPOSITORY_COMPONENTS += userspace/units/interface/rbtree +NV_REPOSITORY_COMPONENTS += userspace/units/bus NV_REPOSITORY_COMPONENTS += userspace/units/pramin NV_REPOSITORY_COMPONENTS += userspace/units/priv_ring NV_REPOSITORY_COMPONENTS += userspace/units/ptimer diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index cf72349f9..a71480a03 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -35,6 +35,8 @@ gk20a_runlist_wait_pending gk20a_runlist_write_state gk20a_userd_entry_size gk20a_vm_release_share +gk20a_bus_init_hw +gk20a_bus_isr gm20b_channel_bind gm20b_channel_force_ctx_reload gm20b_device_info_parse_enum @@ -78,6 +80,7 @@ gm20b_priv_ring_enum_ltc gm20b_priv_ring_get_gpc_count gm20b_priv_ring_get_fbp_count gm20b_gr_falcon_submit_fecs_method_op +gm20b_bus_bar1_bind gp10b_ce_nonstall_isr gp10b_get_max_page_table_levels gp10b_mm_get_default_big_page_size @@ -96,6 +99,7 @@ gp10b_get_device_info gp10b_is_engine_ce gp10b_priv_ring_isr gp10b_priv_ring_decode_error_code +gp10b_bus_bar2_bind gv100_dump_engine_status gv100_read_engine_status_info gv11b_ce_get_num_pce @@ -221,6 +225,7 @@ gv11b_blcg_hshub_gating_prod_size gv11b_blcg_hshub_get_gating_prod gv11b_netlist_is_firmware_defined gv11b_top_get_num_lce +gv11b_bus_configure_debug_bus mc_gp10b_intr_stall_unit_config mc_gp10b_intr_nonstall_unit_config nvgpu_acr_bootstrap_hs_acr diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources index 03f02ade6..b26056671 100644 --- a/userspace/Makefile.sources +++ b/userspace/Makefile.sources @@ -54,6 +54,7 @@ UNITS := \ $(UNIT_SRC)/posix/timers \ $(UNIT_SRC)/posix/kmem \ $(UNIT_SRC)/posix/rwsem \ + $(UNIT_SRC)/bus \ $(UNIT_SRC)/pramin \ $(UNIT_SRC)/ptimer \ $(UNIT_SRC)/priv_ring \ diff --git a/userspace/SWUTS.h b/userspace/SWUTS.h index 98a594cdb..2540ff68e 100644 --- a/userspace/SWUTS.h +++ b/userspace/SWUTS.h @@ -34,6 +34,7 @@ * - @ref SWUTS-interface-bsearch * - @ref SWUTS-interface-lock * - @ref SWUTS-interface-rbtree + * - @ref SWUTS-bus * - @ref SWUTS-falcon * - @ref SWUTS-netlist * - @ref SWUTS-fifo diff --git a/userspace/SWUTS.sources b/userspace/SWUTS.sources index e5562b28b..c140cc0fb 100644 --- a/userspace/SWUTS.sources +++ b/userspace/SWUTS.sources @@ -4,6 +4,7 @@ INPUT += ../../../userspace/units/enabled/nvgpu-enabled.h INPUT += ../../../userspace/units/interface/bsearch/bsearch.h INPUT += ../../../userspace/units/interface/lock/lock.h INPUT += ../../../userspace/units/interface/rbtree/rbtree.h +INPUT += ../../../userspace/units/bus/nvgpu-bus.h INPUT += ../../../userspace/units/falcon/falcon_tests/nvgpu-falcon.h INPUT += ../../../userspace/units/netlist/nvgpu-netlist.h INPUT += ../../../userspace/units/fbp/nvgpu-fbp.h diff --git a/userspace/required_tests.json b/userspace/required_tests.json index d192a5e51..00285ec61 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -353,6 +353,36 @@ "unit": "buddy_allocator", "test_level": 0 }, + { + "test": "test_setup", + "case": "bus_setup", + "unit": "bus", + "test_level": 0 + }, + { + "test": "test_init_hw", + "case": "bus_init_hw", + "unit": "bus", + "test_level": 0 + }, + { + "test": "test_bar_bind", + "case": "bus_bar_bind", + "unit": "bus", + "test_level": 0 + }, + { + "test": "test_isr", + "case": "bus_isr", + "unit": "bus", + "test_level": 0 + }, + { + "test": "test_free_reg_space", + "case": "bus_free_reg_space", + "unit": "bus", + "test_level": 0 + }, { "test": "test_free_env", "case": "ce_free_env", diff --git a/userspace/units/bus/Makefile b/userspace/units/bus/Makefile new file mode 100644 index 000000000..12ac4e5dc --- /dev/null +++ b/userspace/units/bus/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +.SUFFIXES: + +OBJS = nvgpu-bus.o +MODULE = bus + +include ../Makefile.units diff --git a/userspace/units/bus/Makefile.interface.tmk b/userspace/units/bus/Makefile.interface.tmk new file mode 100644 index 000000000..17044c6f6 --- /dev/null +++ b/userspace/units/bus/Makefile.interface.tmk @@ -0,0 +1,23 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved. +# +# NVIDIA CORPORATION and its licensors retain all intellectual property +# and proprietary rights in and to this software, related documentation +# and any modifications thereto. Any use, reproduction, disclosure or +# distribution of this software and related documentation without an express +# license agreement from NVIDIA CORPORATION is strictly prohibited. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=bus + +include $(NV_COMPONENT_DIR)/../Makefile.units.common.interface.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/bus/Makefile.tmk b/userspace/units/bus/Makefile.tmk new file mode 100644 index 000000000..1594b1500 --- /dev/null +++ b/userspace/units/bus/Makefile.tmk @@ -0,0 +1,24 @@ +################################### tell Emacs this is a -*- makefile-gmake -*- +# +# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved. +# +# NVIDIA CORPORATION and its licensors retain all intellectual property +# and proprietary rights in and to this software, related documentation +# and any modifications thereto. Any use, reproduction, disclosure or +# distribution of this software and related documentation without an express +# license agreement from NVIDIA CORPORATION is strictly prohibited. +# +# tmake for SW Mobile component makefile +# +############################################################################### + +NVGPU_UNIT_NAME=bus +NVGPU_UNIT_SRCS=nvgpu-bus.c + +include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk + +# Local Variables: +# indent-tabs-mode: t +# tab-width: 8 +# End: +# vi: set tabstop=8 noexpandtab: diff --git a/userspace/units/bus/nvgpu-bus.c b/userspace/units/bus/nvgpu-bus.c new file mode 100644 index 000000000..546f4c815 --- /dev/null +++ b/userspace/units/bus/nvgpu-bus.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "nvgpu-bus.h" + +#define assert(cond) unit_assert(cond, goto done) +u32 read_bind_status_reg = 0U; +/* + * Write callback. + */ +static void writel_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + nvgpu_posix_io_writel_reg_space(g, access->addr, access->value); +} + +/* + * Read callback. + */ +static void readl_access_reg_fn(struct gk20a *g, + struct nvgpu_reg_access *access) +{ + /* BAR_1 bind status is indicated by value of + * bus_bind_status_bar1_pending = empty(0x0U) and + * bus_bind_status_bar1_outstanding = false(0x0U). + * + * Similarly, for BAR_2 bind status, we check + * bus_bind_status_bar2_pending = empty (0x0U) + * and bus_bind_status_bar2_outstanding = false(0x0U). + * + * During bar1/2_bind HAL, the bus_bind_status_r() register is polled to + * check if its value changed as described above. + * To get complete branch coverage in bus.bar1/2_bind(), after + * "read_bind_status_reg" read attempts, the value of + * bus_bind_status_r() is read as pending field = empty and + * outstanding field = false. + * This maps to bind_status = done after "read_cmd_reg" polling + * attempts. + */ + if (access->addr == bus_bind_status_r()) { + if (read_bind_status_reg == 3U) { + access->value = + (bus_bind_status_bar1_pending_empty_f() | + bus_bind_status_bar1_outstanding_false_f() | + bus_bind_status_bar2_pending_empty_f() | + bus_bind_status_bar2_outstanding_false_f()); + read_bind_status_reg = nvgpu_safe_add_u32( + read_bind_status_reg, 1U); + return; + } + read_bind_status_reg = nvgpu_safe_add_u32(read_bind_status_reg, + 1U); + } + access->value = nvgpu_posix_io_readl_reg_space(g, access->addr); +} + +static struct nvgpu_posix_io_callbacks test_reg_callbacks = { + /* Write APIs all can use the same accessor. */ + .writel = writel_access_reg_fn, + .writel_check = writel_access_reg_fn, + .bar1_writel = writel_access_reg_fn, + .usermode_writel = writel_access_reg_fn, + + /* Likewise for the read APIs. */ + .__readl = readl_access_reg_fn, + .readl = readl_access_reg_fn, + .bar1_readl = readl_access_reg_fn, +}; + +/* NV_PBUS register space */ +#define NV_PBUS_START 0x00001000U +#define NV_PBUS_SIZE 0x00000FFFU + +/* NV_PRIV_GPC register space */ +#define NV_PMC_START 0x00000000U +#define NV_PMC_SIZE 0x00000FFFU + +/* NV_PTIMER register space */ +#define NV_PTIMER_START 0x00009000U +#define NV_PTIMER_SIZE 0x00000FFFU + +int test_setup(struct unit_module *m, struct gk20a *g, void *args) +{ + /* Init HAL */ + g->ops.bus.init_hw = gk20a_bus_init_hw; + g->ops.bus.isr = gk20a_bus_isr; + g->ops.bus.bar1_bind = gm20b_bus_bar1_bind; + g->ops.bus.bar2_bind = gp10b_bus_bar2_bind; + g->ops.bus.configure_debug_bus = gv11b_bus_configure_debug_bus; + g->ops.mc.intr_stall_unit_config = + mc_gp10b_intr_stall_unit_config; + g->ops.ptimer.isr = gk20a_ptimer_isr; + + /* Init register space */ + nvgpu_posix_io_init_reg_space(g); + + /* Map register space NV_PRIV_MASTER */ + if (nvgpu_posix_io_add_reg_space(g, NV_PBUS_START, NV_PBUS_SIZE) != 0) { + unit_err(m, "%s: failed to register space: NV_PBUS\n", + __func__); + return UNIT_FAIL; + } + + /* Map register space NV_PMC */ + if (nvgpu_posix_io_add_reg_space(g, NV_PMC_START, + NV_PMC_SIZE) != 0) { + unit_err(m, "%s: failed to register space: NV_PMC\n", + __func__); + return UNIT_FAIL; + } + + /* Map register space NV_PTIMER */ + if (nvgpu_posix_io_add_reg_space(g, NV_PTIMER_START, + NV_PTIMER_SIZE) != 0) { + unit_err(m, "%s: failed to register space: NV_PTIMER\n", + __func__); + return UNIT_FAIL; + } + + (void)nvgpu_posix_register_io(g, &test_reg_callbacks); + + return UNIT_SUCCESS; +} + +int test_free_reg_space(struct unit_module *m, struct gk20a *g, void *args) +{ + /* Free register space */ + nvgpu_posix_io_delete_reg_space(g, NV_PBUS_START); + nvgpu_posix_io_delete_reg_space(g, NV_PMC_START); + nvgpu_posix_io_delete_reg_space(g, NV_PTIMER_START); + + return UNIT_SUCCESS; +} + +int test_init_hw(struct unit_module *m, struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g); + + nvgpu_writel(g, bus_debug_sel_0_r(), 0xFU); + nvgpu_writel(g, bus_debug_sel_1_r(), 0xFU); + nvgpu_writel(g, bus_debug_sel_2_r(), 0xFU); + nvgpu_writel(g, bus_debug_sel_3_r(), 0xFU); + + p->is_silicon = false; + g->ops.bus.configure_debug_bus = NULL; + ret = g->ops.bus.init_hw(g); + assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0U); + assert(nvgpu_readl(g, bus_debug_sel_0_r()) == 0xFU); + assert(nvgpu_readl(g, bus_debug_sel_1_r()) == 0xFU); + assert(nvgpu_readl(g, bus_debug_sel_2_r()) == 0xFU); + assert(nvgpu_readl(g, bus_debug_sel_3_r()) == 0xFU); + + p->is_silicon = true; + g->ops.bus.configure_debug_bus = gv11b_bus_configure_debug_bus; + ret = g->ops.bus.init_hw(g); + assert(nvgpu_readl(g, bus_intr_en_0_r()) == 0xEU); + assert(nvgpu_readl(g, bus_debug_sel_0_r()) == 0x0U); + assert(nvgpu_readl(g, bus_debug_sel_1_r()) == 0x0U); + assert(nvgpu_readl(g, bus_debug_sel_2_r()) == 0x0U); + assert(nvgpu_readl(g, bus_debug_sel_3_r()) == 0x0U); + + ret = UNIT_SUCCESS; +done: + return ret; +} + +int test_bar_bind(struct unit_module *m, struct gk20a *g, void *args) +{ + int ret = UNIT_FAIL; + struct nvgpu_mem bar_inst; + struct nvgpu_posix_fault_inj *timer_fi = + nvgpu_timers_get_fault_injection(); + + /* Initialize cpu_va to a known value */ + bar_inst.cpu_va = (void *) 0xCE418000U; + bar_inst.aperture = APERTURE_VIDMEM; + /* Set bus_bind_status_r to 0xF that is both bar1 and bar2 status + * pending and outstanding. + */ + nvgpu_posix_io_writel_reg_space(g, bus_bind_status_r(), 0xFU); + + /* Call bus.bar1_bind() HAL */ + ret = g->ops.bus.bar1_bind(g, &bar_inst); + + /* Make sure HAL returns success as bind_status is marked as done in + * third polling attempt. + */ + if (ret != 0U) { + unit_err(m, "bus.bar1_bind HAL failed.\n"); + ret = UNIT_FAIL; + } + + /* Send error if bar1_block register is not set as expected: + * Bit 27:0 - 4k aligned block pointer = bar_inst.cpu_va >> 12 = 0xCE418 + * Bit 29:28- Target = Vidmem = (00)b + * Bit 30 - Debug CYA = (0)b + * Bit 31 - Mode = virtual = (1)b + */ + assert(nvgpu_readl(g, bus_bar1_block_r()) == 0x800CE418U); + + /* Call bus.bar1_bind HAL again and except ret != 0 as the bind status + * will remain pending and outstanding during this call. + */ + nvgpu_posix_io_writel_reg_space(g, bus_bind_status_r(), 0x5U); + ret = g->ops.bus.bar1_bind(g, &bar_inst); + /* The HAL should return error this time as timeout is expected to + * expire. + */ + if (ret != -EINVAL) { + unit_err(m, "bus.bar1_bind did not fail as expected.\n"); + ret = UNIT_FAIL; + } + + /* Enable fault injection for the timer init call for branch coverage */ + nvgpu_posix_enable_fault_injection(timer_fi, true, 0); + ret = g->ops.bus.bar1_bind(g, &bar_inst); + if (ret == 0U) { + unit_err(m, "Error injection for timeout init failed.\n"); + ret = UNIT_FAIL; + } + nvgpu_posix_enable_fault_injection(timer_fi, false, 0); + + bar_inst.cpu_va = (void *) 0x2670C000U; + read_bind_status_reg = 0U; + ret = g->ops.bus.bar2_bind(g, &bar_inst); + if (ret != 0U) { + unit_err(m, "bus.bar2_bind HAL failed.\n"); + ret = UNIT_FAIL; + } + assert(nvgpu_readl(g, bus_bar2_block_r()) == 0x8002670CU); + + /* Call bus.bar2_bind HAL again and except ret != 0 as the bind status + * will remain pending and outstanding during this call. + */ + nvgpu_posix_io_writel_reg_space(g, bus_bind_status_r(), 0xAU); + ret = g->ops.bus.bar2_bind(g, &bar_inst); + if (ret != -EINVAL) { + unit_err(m, "bus.bar2_bind did not fail as expected.\n"); + ret = UNIT_FAIL; + } + + /* Enable fault injection for the timer init call for branch coverage */ + nvgpu_posix_enable_fault_injection(timer_fi, true, 0); + ret = g->ops.bus.bar2_bind(g, &bar_inst); + if (ret == 0U) { + unit_err(m, "Error injection for timeout init failed.\n"); + ret = UNIT_FAIL; + } + nvgpu_posix_enable_fault_injection(timer_fi, false, 0); + + ret = UNIT_SUCCESS; +done: + return ret; +} + +int test_isr(struct unit_module *m, struct gk20a *g, void *args) +{ + int ret = UNIT_SUCCESS; + + nvgpu_writel(g, bus_intr_0_r(), bus_intr_0_pri_squash_m()); + g->ops.bus.isr(g); + + nvgpu_writel(g, bus_intr_0_r(), bus_intr_0_pri_fecserr_m()); + g->ops.bus.isr(g); + + nvgpu_writel(g, bus_intr_0_r(), bus_intr_0_pri_timeout_m()); + g->ops.bus.isr(g); + + nvgpu_writel(g, bus_intr_0_r(), 0x10U); + g->ops.bus.isr(g); + + return ret; +} + +struct unit_module_test bus_tests[] = { + UNIT_TEST(bus_setup, test_setup, NULL, 0), + UNIT_TEST(bus_init_hw, test_init_hw, NULL, 0), + UNIT_TEST(bus_bar_bind, test_bar_bind, NULL, 0), + UNIT_TEST(bus_isr, test_isr, NULL, 0), + UNIT_TEST(bus_free_reg_space, test_free_reg_space, NULL, 0), +}; + +UNIT_MODULE(bus, bus_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/bus/nvgpu-bus.h b/userspace/units/bus/nvgpu-bus.h new file mode 100644 index 000000000..32de7b861 --- /dev/null +++ b/userspace/units/bus/nvgpu-bus.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef UNIT_NVGPU_BUS_H +#define UNIT_NVGPU_BUS_H + +struct gk20a; +struct unit_module; + +/** @addtogroup SWUTS-bus + * @{ + * + * Software Unit Test Specification for nvgpu.common.bus + */ + +/** + * Test specification for: test_setup + * + * Description: Setup prerequisites for tests. + * + * Test Type: Other (setup) + * + * Input: None + * + * Steps: + * - Initialize common.bus and few other necessary HAL function pointers. + * - Map the register space for NV_PBUS, NV_PMC and NV_PTIMER. + * - Register read/write callback functions. + * + * Output: + * - UNIT_FAIL if encounters an error creating reg space + * - UNIT_SUCCESS otherwise + */ +int test_setup(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_free_reg_space + * + * Description: Free resources from test_setup() + * + * Test Type: Other (setup) + * + * Input: test_setup() has been executed. + * + * Steps: + * - Free up NV_PBUS, NV_PMC and NV_PTIMER register space. + * + * Output: + * - UNIT_SUCCESS + */ +int test_free_reg_space(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_init_hw + * + * Description: Verify the bus.init_hw and bus.configure_debug_bus HAL. + * + * Test Type: Feature Based + * + * Targets: gk20a_bus_init_hw, gv11b_bus_configure_debug_bus. + * + * Input: test_setup() has been executed. + * + * Steps: + * - Initialize the Debug bus related registers to non-zero value. + * - Set is_silicon flag to true to get branch coverage. + * - Call init_hw() HAL. + * - Read back the debug bus registers to make sure they are zeroed out. + * pri_ringmaster_command_r = 0x4 + * pri_ringstation_sys_decode_config_r = 0x2 + * + * Output: + * - UNIT_FAIL if above HAL fails to enable interrupts. + * - UNIT_SUCCESS otherwise. + */ +int test_init_hw(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_bar_bind + * + * Description: Verify the bus.bar1_bind and bus.bar2_bind HAL. + * + * Test Type: Feature Based + * + * Targets: gm20b_bus_bar1_bind, gp10b_bus_bar2_bind. + * + * Input: test_setup() has been executed. + * + * Steps: + * - Initialize cpu_va to a known value (say 0xCE418000U). + * - Set bus_bind_status_r to 0xF that is both bar1 and bar2 status + * pending and outstanding. + * - Call bus.bar1_bind() HAL. + * - Make sure HAL returns success as bind_status is marked as done in + * third polling attempt. + * - Send error if bar1_block register is not set as expected: + * - Bit 27:0 - 4k aligned block pointer = bar_inst.cpu_va >> 12 = 0xCE418 + * - Bit 29:28- Target = (11)b + * - Bit 30 - Debug CYA = (0)b + * - Bit 31 - Mode = virtual = (1)b + * - Call bus.bar1_bind HAL again and except ret != 0 as the bind status + * will remain pending and outstanding during this call. + * - The HAL should return error this time as timeout is expected to expire. + * - Enable fault injection for the timer init call for branch coverage. + * - Repeat the above steps for BAR2 but with different cpu_va = 0x2670C000U. + * + * Output: + * - UNIT_FAIL if above HAL fails to bind BAR1/2 + * - UNIT_SUCCESS otherwise. + */ +int test_bar_bind(struct unit_module *m, struct gk20a *g, void *args); + +/** + * Test specification for: test_isr + * + * Description: Verify the bus.isr HAL. + * + * Test Type: Feature Based + * + * Targets: gk20a_bus_isr + * + * Input: test_setup() has been executed. + * + * Steps: + * - Initialize interrupt register bus_intr_0_r() to 0x2(pri_squash) + * - Call isr HAL. + * - Initialize interrupt register bus_intr_0_r() to 0x4(pri_fecserr) + * - Call isr HAL. + * - Initialize interrupt register bus_intr_0_r() to 0x8(pri_timeout) + * - Call isr HAL. + * - Initialize interrupt register bus_intr_0_r() to 0x10(fb_req_timeout) + * - Call isr HAL. + * + * Output: + * - UNIT_SUCCESS. + */ +int test_isr(struct unit_module *m, struct gk20a *g, void *args); +#endif /* UNIT_NVGPU_BUS_H */