From 8e44b3fcd74415c70f6750e16f2f77204d56ceae Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Fri, 15 Feb 2019 12:08:00 +0530 Subject: [PATCH] gpu: nvgpu: use public APIs of pbdma_status unit. nvgpu driver uses the h/w headers for reading pbdma_status registers directly in the common code path. Replace the use of the H/W headers by using the APIs of the pbdma_status unit. Use the HAL ops functions read_pbdma_status_info() to do a read of the pbdma status register. Jira NVGPU-1311 Change-Id: I4b492e675ce2561bb1e132b518023f9933d8c510 Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/2019977 Reviewed-by: Deepak Nibade Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 54 +++++++++++++++------------- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 31 ++++++++-------- 2 files changed, 43 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 8c0ad34a6..23fd72cb5 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -1998,16 +1999,17 @@ static void gk20a_fifo_pbdma_fault_rc(struct gk20a *g, struct fifo_gk20a *f, u32 pbdma_id, u32 error_notifier) { - u32 status; u32 id; + struct nvgpu_pbdma_status_info pbdma_status; nvgpu_log(g, gpu_dbg_info, "pbdma id %d error notifier %d", pbdma_id, error_notifier); - status = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); + + g->ops.pbdma_status.read_pbdma_status_info(g, pbdma_id, + &pbdma_status); /* Remove channel from runlist */ - id = fifo_pbdma_status_id_v(status); - if (fifo_pbdma_status_id_type_v(status) - == fifo_pbdma_status_id_type_chid_v()) { + id = pbdma_status.id; + if (pbdma_status.id_type == PBDMA_STATUS_ID_TYPE_CHID) { struct channel_gk20a *ch = gk20a_channel_from_id(g, id); if (ch != NULL) { @@ -2015,8 +2017,7 @@ static void gk20a_fifo_pbdma_fault_rc(struct gk20a *g, nvgpu_channel_recover(g, ch, true, RC_TYPE_PBDMA_FAULT); gk20a_channel_put(ch); } - } else if (fifo_pbdma_status_id_type_v(status) - == fifo_pbdma_status_id_type_tsgid_v()) { + } else if (pbdma_status.id_type == PBDMA_STATUS_ID_TYPE_TSGID) { struct tsg_gk20a *tsg = &f->tsg[id]; struct channel_gk20a *ch = NULL; @@ -2031,6 +2032,8 @@ static void gk20a_fifo_pbdma_fault_rc(struct gk20a *g, } nvgpu_rwsem_up_read(&tsg->ch_list_lock); nvgpu_tsg_recover(g, tsg, true, RC_TYPE_PBDMA_FAULT); + } else { + nvgpu_err(g, "Invalid pbdma_id"); } } @@ -2380,7 +2383,6 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, struct fifo_engine_info_gk20a *eng_info, bool wait_for_idle) { - u32 pbdma_stat, chan_stat; u32 pbdma_chid = FIFO_INVAL_CHANNEL_ID; u32 engine_chid = FIFO_INVAL_CHANNEL_ID; u32 token = PMU_INVALID_MUTEX_OWNER_ID; @@ -2388,6 +2390,7 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, struct channel_gk20a *ch = NULL; int err = 0; struct nvgpu_engine_status_info engine_status; + struct nvgpu_pbdma_status_info pbdma_status; nvgpu_log_fn(g, " "); @@ -2406,14 +2409,14 @@ int gk20a_fifo_disable_engine_activity(struct gk20a *g, RUNLIST_DISABLED); /* chid from pbdma status */ - pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(eng_info->pbdma_id)); - chan_stat = fifo_pbdma_status_chan_status_v(pbdma_stat); - if (chan_stat == fifo_pbdma_status_chan_status_valid_v() || - chan_stat == fifo_pbdma_status_chan_status_chsw_save_v()) { - pbdma_chid = fifo_pbdma_status_id_v(pbdma_stat); - } else if (chan_stat == fifo_pbdma_status_chan_status_chsw_load_v() || - chan_stat == fifo_pbdma_status_chan_status_chsw_switch_v()) { - pbdma_chid = fifo_pbdma_status_next_id_v(pbdma_stat); + g->ops.pbdma_status.read_pbdma_status_info(g, eng_info->pbdma_id, + &pbdma_status); + if (nvgpu_pbdma_status_is_chsw_valid(&pbdma_status) || + nvgpu_pbdma_status_is_chsw_save(&pbdma_status)) { + pbdma_chid = pbdma_status.id; + } else if (nvgpu_pbdma_status_is_chsw_load(&pbdma_status) || + nvgpu_pbdma_status_is_chsw_switch(&pbdma_status)) { + pbdma_chid = pbdma_status.next_id; } if (pbdma_chid != FIFO_INVAL_CHANNEL_ID) { @@ -2857,6 +2860,7 @@ void gk20a_dump_pbdma_status(struct gk20a *g, struct gk20a_debug_output *o) { u32 i, host_num_pbdma; + struct nvgpu_pbdma_status_info pbdma_status; host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); @@ -2864,21 +2868,21 @@ void gk20a_dump_pbdma_status(struct gk20a *g, gk20a_debug_output(o, "-------------------------"); for (i = 0; i < host_num_pbdma; i++) { - u32 status = gk20a_readl(g, fifo_pbdma_status_r(i)); - u32 chan_status = fifo_pbdma_status_chan_status_v(status); + g->ops.pbdma_status.read_pbdma_status_info(g, i, + &pbdma_status); gk20a_debug_output(o, "pbdma %d:", i); gk20a_debug_output(o, " id: %d - %-9s next_id: - %d %-9s | status: %s", - fifo_pbdma_status_id_v(status), - (fifo_pbdma_status_id_type_v(status) == - fifo_pbdma_status_id_type_tsgid_v()) ? + pbdma_status.id, + nvgpu_pbdma_status_is_id_type_tsg(&pbdma_status) ? "[tsg]" : "[channel]", - fifo_pbdma_status_next_id_v(status), - (fifo_pbdma_status_next_id_type_v(status) == - fifo_pbdma_status_next_id_type_tsgid_v()) ? + pbdma_status.next_id, + nvgpu_pbdma_status_is_next_id_type_tsg( + &pbdma_status) ? "[tsg]" : "[channel]", - gk20a_decode_pbdma_chan_eng_ctx_status(chan_status)); + gk20a_decode_pbdma_chan_eng_ctx_status( + pbdma_status.pbdma_channel_status)); gk20a_debug_output(o, " PBDMA_PUT %016llx PBDMA_GET %016llx", (u64)gk20a_readl(g, pbdma_put_r(i)) + diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 5657ae6f8..b7658bc46 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -46,6 +46,7 @@ #include #include #include +#include #include #include "gk20a/fifo_gk20a.h" @@ -359,10 +360,9 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, { struct nvgpu_timeout timeout; unsigned long delay = GR_IDLE_CHECK_DEFAULT; /* in micro seconds */ - u32 pbdma_stat; - u32 chan_stat; int ret; unsigned int loop_count = 0; + struct nvgpu_pbdma_status_info pbdma_status; /* timeout in milli seconds */ ret = nvgpu_timeout_init(g, &timeout, @@ -403,32 +403,28 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, (void) gk20a_fifo_handle_pbdma_intr(g, &g->fifo, pbdma_id, RC_NO); - pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); - chan_stat = fifo_pbdma_status_chan_status_v(pbdma_stat); + g->ops.pbdma_status.read_pbdma_status_info(g, pbdma_id, + &pbdma_status); - if (chan_stat == - fifo_pbdma_status_chan_status_valid_v() || - chan_stat == - fifo_pbdma_status_chan_status_chsw_save_v()) { + if (nvgpu_pbdma_status_is_chsw_valid(&pbdma_status) || + nvgpu_pbdma_status_is_chsw_save(&pbdma_status)) { - if (id != fifo_pbdma_status_id_v(pbdma_stat)) { + if (id != pbdma_status.id) { ret = 0; break; } - } else if (chan_stat == - fifo_pbdma_status_chan_status_chsw_load_v()) { + } else if (nvgpu_pbdma_status_is_chsw_load(&pbdma_status)) { - if (id != fifo_pbdma_status_next_id_v(pbdma_stat)) { + if (id != pbdma_status.next_id) { ret = 0; break; } - } else if (chan_stat == - fifo_pbdma_status_chan_status_chsw_switch_v()) { + } else if (nvgpu_pbdma_status_is_chsw_switch(&pbdma_status)) { - if ((id != fifo_pbdma_status_next_id_v(pbdma_stat)) && - (id != fifo_pbdma_status_id_v(pbdma_stat))) { + if ((id != pbdma_status.next_id) && + (id != pbdma_status.id)) { ret = 0; break; } @@ -445,7 +441,8 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, if (ret != 0) { nvgpu_err(g, "preempt timeout pbdma: %u pbdma_stat: %u " - "tsgid: %u", pbdma_id, pbdma_stat, id); + "tsgid: %u", pbdma_id, + pbdma_status.pbdma_reg_status, id); } return ret; }