From 8e9ec4f1b74d89d87839b43c3f111c51e1724306 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Tue, 9 Apr 2019 11:30:45 -0400 Subject: [PATCH] gpu: nvgpu: fifo: fix MISRA 10.3 violations MISRA Rule 10.3 prohibits assigning objects of different essential or narrower type. This fixes MISRA 10.3 violations in the fifo unit. JIRA NVGPU-3115 Change-Id: I5a0e1134f731631faa3aa31b5d88781c200306e0 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2094444 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/engines.c | 2 +- drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 895001499..4499a04c4 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -726,7 +726,7 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg) ENGINE_STATUS_CTX_ID_TYPE_TSGID) || (!is_tsg && type == ENGINE_STATUS_CTX_ID_TYPE_CHID)) { - engines |= BIT(active_engine_id); + engines |= BIT32(active_engine_id); } } } diff --git a/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c index b81e8c07f..05bb250c8 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c @@ -59,7 +59,7 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base, nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | - pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); + pbdma_gp_base_hi_limit2_f(U32(ilog2(gpfifo_entries)))); nvgpu_mem_wr32(g, mem, ram_fc_signature_w(), ch->g->ops.pbdma.get_signature(ch->g));