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gpu: nvgpu: Refactor PERF VFE unit

Browse Source 
-Created ucode_perf_vfe_inf.h and moved all VFE
 interface structs and MACROs into this header
-Created nvgpu_clk_fll_get_fmargin_idx to get
 freq margin index
-Created nvgpu_vfe_var_get_s_param to read s_param
-Removed MACROs and header includes which are
 not needed

NVGPU-4448

Change-Id: I89f946d555bcbc7823665d2a5a761049f7a5e963
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260150
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2019-12-11 17:03:31 +05:30
committed by Alex Waterman
parent d0118c297e
commit 8f154fb6eb
20 changed files with 702 additions and 833 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
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@@ -37,6 +37,7 @@ struct gk20a;
#include <nvgpu/cond.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/perf_pstate.h>
#include <nvgpu/pmu/volt.h>

1
drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h
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@@ -73,5 +73,6 @@ int nvgpu_clk_fll_init_pmupstate(struct gk20a *g);
void nvgpu_clk_fll_free_pmupstate(struct gk20a *g);
int nvgpu_clk_fll_sw_setup(struct gk20a *g);
int nvgpu_clk_fll_pmu_setup(struct gk20a *g);
u8 nvgpu_clk_fll_get_fmargin_idx(struct gk20a *g);
#endif /* NVGPU_PMU_CLK_FLL_H */

4
drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h
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@@ -25,12 +25,12 @@
#include <nvgpu/types.h>
#include <nvgpu/cond.h>
#include <nvgpu/thread.h>
#include <nvgpu/pmu/perf_pstate.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/lpwr.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/pmu/perf_pstate.h>
#include <nvgpu/pmu/pmuif/perf.h>
struct gk20a;
@@ -102,7 +102,7 @@ int nvgpu_vfe_equ_pmu_setup(struct gk20a *g);
int nvgpu_vfe_var_sw_setup(struct gk20a *g);
int nvgpu_vfe_var_pmu_setup(struct gk20a *g);
int nvgpu_vfe_var_boardobj_grp_get_status(struct gk20a *g);
int nvgpu_vfe_var_get_s_param(struct gk20a *g, u64 *s_param);
int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv);
int nvgpu_vfe_get_freq_margin_limit(struct gk20a *g, u32 *fmargin_mhz);

67
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlperf.h
View File

@@ -39,73 +39,6 @@ struct ctrl_perf_volt_rail_list {
rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
};
union ctrl_perf_vfe_var_single_sensed_fuse_value_data {
int signed_value;
u32 unsigned_value;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_value {
bool b_signed;
union ctrl_perf_vfe_var_single_sensed_fuse_value_data data;
};
struct ctrl_bios_vfield_register_segment_super {
u8 low_bit;
u8 high_bit;
};
struct ctrl_bios_vfield_register_segment_reg {
struct ctrl_bios_vfield_register_segment_super super;
u32 addr;
};
struct ctrl_bios_vfield_register_segment_index_reg {
struct ctrl_bios_vfield_register_segment_super super;
u32 addr;
u32 reg_index;
u32 index;
};
union ctrl_bios_vfield_register_segment_data {
struct ctrl_bios_vfield_register_segment_reg reg;
struct ctrl_bios_vfield_register_segment_index_reg index_reg;
};
struct ctrl_bios_vfield_register_segment {
u8 type;
union ctrl_bios_vfield_register_segment_data data;
};
#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1U
struct ctrl_perf_vfe_var_single_sensed_fuse_info {
u8 segment_count;
struct ctrl_bios_vfield_register_segment
segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
};
struct ctrl_perf_vfe_var_single_sensed_fuse_override_info {
u32 fuse_val_override;
u8 b_fuse_regkey_override;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info {
struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
u32 fuse_val_default;
u32 hw_correction_scale;
int hw_correction_offset;
u8 v_field_id;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info {
struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
u8 ver_expected;
bool b_ver_check;
bool b_ver_check_ignore;
bool b_use_default_on_ver_check_fail;
u8 v_field_id_ver;
};
/*----------------------------- CHANGES_SEQ --------------------------------*/
/*!

1
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/nvgpu_cmdif.h
View File

@@ -25,7 +25,6 @@
#include "cmn.h"
#include "init.h"
#include "ap.h"
#include "perfvfe.h"
#include "thermsensor.h"
#include "seq.h"

8
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h
View File

@@ -23,7 +23,6 @@
#define NVGPU_PMUIF_PERF_H
#include "volt.h"
#include "perfvfe.h"
#include "perfpstate.h"
#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U)
@@ -142,11 +141,4 @@ struct perf_change_seq_pmu_script {
steps[CTRL_PERF_CHANGE_SEQ_SCRIPT_VF_SWITCH_MAX_STEPS];
};
struct nv_pmu_rpc_struct_perf_vfe_eval {
/*[IN/OUT] Must be first field in RPC structure */
struct nv_pmu_rpc_header hdr;
struct nv_pmu_perf_rpc_vfe_equ_eval data;
u32 scratch[1];
};
#endif /* NVGPU_PMUIF_PERF_H */

248
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perfvfe.h
View File

@@ -1,248 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PMUIF_PERFVFE_H
#define NVGPU_PMUIF_PERFVFE_H
#include "bios.h"
#include "boardobj.h"
#include "ctrlperf.h"
#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03U
#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2U
#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16U
union nv_pmu_perf_vfe_var_type_data {
u8 uid;
u8 clk_domain_idx;
};
struct nv_pmu_perf_vfe_var_value {
u8 var_type;
union nv_pmu_perf_vfe_var_type_data var_type_data;
u8 reserved[2];
u32 var_value;
};
union nv_pmu_perf_vfe_equ_result {
u32 freq_m_hz;
u32 voltu_v;
u32 vf_gain;
int volt_deltau_v;
u32 work_type;
u32 util_ratio;
u32 work_fb_norm;
u32 power_mw;
u32 pwr_over_util_slope;
int vin_code;
};
struct nv_pmu_perf_rpc_vfe_equ_eval {
u8 equ_idx;
u8 var_count;
u8 output_type;
struct nv_pmu_perf_vfe_var_value var_values[
NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX];
union nv_pmu_perf_vfe_equ_result result;
};
struct nv_pmu_perf_rpc_vfe_load {
bool b_load;
};
struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header {
struct nv_pmu_boardobjgrp_e32 super;
};
struct nv_pmu_perf_vfe_var_get_status_super {
struct nv_pmu_boardobj_query board_obj;
};
struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status {
struct nv_pmu_perf_vfe_var_get_status_super super;
struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_integer;
struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_hw_integer;
u8 fuse_version;
bool b_version_check_failed;
};
union nv_pmu_perf_vfe_var_boardobj_get_status_union {
struct nv_pmu_boardobj_query board_obj;
struct nv_pmu_perf_vfe_var_get_status_super super;
struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status;
};
NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var);
struct nv_pmu_perf_vfe_var_boardobj_grp_get_status_pack {
struct nv_pmu_perf_vfe_var_boardobj_grp_get_status pri;
struct nv_pmu_perf_vfe_var_boardobj_grp_get_status rppm;
};
struct nv_pmu_vfe_var {
struct nv_pmu_boardobj super;
u32 out_range_min;
u32 out_range_max;
struct ctrl_boardobjgrp_mask_e32 mask_dependent_vars;
struct ctrl_boardobjgrp_mask_e255 mask_dependent_equs;
};
struct nv_pmu_vfe_var_derived {
struct nv_pmu_vfe_var super;
};
struct nv_pmu_vfe_var_derived_product {
struct nv_pmu_vfe_var_derived super;
u8 var_idx0;
u8 var_idx1;
};
struct nv_pmu_vfe_var_derived_sum {
struct nv_pmu_vfe_var_derived super;
u8 var_idx0;
u8 var_idx1;
};
struct nv_pmu_vfe_var_single {
struct nv_pmu_vfe_var super;
u8 override_type;
u32 override_value;
};
struct nv_pmu_vfe_var_single_frequency {
struct nv_pmu_vfe_var_single super;
u8 clk_domain_idx;
};
struct nv_pmu_vfe_var_single_caller_specified {
struct nv_pmu_vfe_var_single super;
u8 uid;
};
struct nv_pmu_vfe_var_single_sensed {
struct nv_pmu_vfe_var_single super;
};
struct nv_pmu_vfe_var_single_sensed_fuse {
struct nv_pmu_vfe_var_single_sensed super;
struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info;
struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info;
struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info
vfield_ver_info;
struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default;
bool b_fuse_value_signed;
};
struct nv_pmu_vfe_var_single_sensed_temp {
struct nv_pmu_vfe_var_single_sensed super;
u8 therm_channel_index;
int temp_hysteresis_positive;
int temp_hysteresis_negative;
int temp_default;
};
struct nv_pmu_vfe_var_single_voltage {
struct nv_pmu_vfe_var_single super;
};
struct nv_pmu_perf_vfe_var_boardobjgrp_set_header {
struct nv_pmu_boardobjgrp_e32 super;
u8 polling_periodms;
};
union nv_pmu_perf_vfe_var_boardobj_set_union {
struct nv_pmu_boardobj board_obj;
struct nv_pmu_vfe_var var;
struct nv_pmu_vfe_var_derived var_derived;
struct nv_pmu_vfe_var_derived_product var_derived_product;
struct nv_pmu_vfe_var_derived_sum var_derived_sum;
struct nv_pmu_vfe_var_single var_single;
struct nv_pmu_vfe_var_single_frequency var_single_frequiency;
struct nv_pmu_vfe_var_single_sensed var_single_sensed;
struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse;
struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp;
struct nv_pmu_vfe_var_single_voltage var_single_voltage;
struct nv_pmu_vfe_var_single_caller_specified
var_single_caller_specified;
};
NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var);
struct nv_pmu_perf_vfe_var_boardobj_grp_set_pack {
struct nv_pmu_perf_vfe_var_boardobj_grp_set pri;
struct nv_pmu_perf_vfe_var_boardobj_grp_set rppm;
};
struct nv_pmu_vfe_equ {
struct nv_pmu_boardobj super;
u8 var_idx;
u8 equ_idx_next;
u8 output_type;
u32 out_range_min;
u32 out_range_max;
};
struct nv_pmu_vfe_equ_compare {
struct nv_pmu_vfe_equ super;
u8 func_id;
u8 equ_idx_true;
u8 equ_idx_false;
u32 criteria;
};
struct nv_pmu_vfe_equ_minmax {
struct nv_pmu_vfe_equ super;
bool b_max;
u8 equ_idx0;
u8 equ_idx1;
};
struct nv_pmu_vfe_equ_quadratic {
struct nv_pmu_vfe_equ super;
u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT];
};
struct nv_pmu_vfe_equ_scalar {
struct nv_pmu_vfe_equ super;
u8 equ_idx_to_scale;
};
struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header {
struct nv_pmu_boardobjgrp_e255 super;
};
union nv_pmu_perf_vfe_equ_boardobj_set_union {
struct nv_pmu_boardobj board_obj;
struct nv_pmu_vfe_equ equ;
struct nv_pmu_vfe_equ_compare equ_comapre;
struct nv_pmu_vfe_equ_minmax equ_minmax;
struct nv_pmu_vfe_equ_quadratic equ_quadratic;
struct nv_pmu_vfe_equ_scalar equ_scalar;
};
NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ);
struct nv_pmu_perf_vfe_equ_boardobj_grp_set_pack {
struct nv_pmu_perf_vfe_equ_boardobj_grp_set pri;
struct nv_pmu_perf_vfe_var_boardobj_grp_set rppm;
};
#endif /* NVGPU_PMUIF_PERFVFE_H */