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gpu: nvgpu: Refactor PERF VFE unit

Browse Source 
-Created ucode_perf_vfe_inf.h and moved all VFE
 interface structs and MACROs into this header
-Created nvgpu_clk_fll_get_fmargin_idx to get
 freq margin index
-Created nvgpu_vfe_var_get_s_param to read s_param
-Removed MACROs and header includes which are
 not needed

NVGPU-4448

Change-Id: I89f946d555bcbc7823665d2a5a761049f7a5e963
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260150
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2019-12-11 17:03:31 +05:30
committed by Alex Waterman
parent d0118c297e
commit 8f154fb6eb
20 changed files with 702 additions and 833 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/nvgpu-common.yaml
View File

@@ -654,7 +654,6 @@ pmu:
include/nvgpu/pmu/pmuif/boardobj.h,
include/nvgpu/pmu/pmuif/clk.h,
include/nvgpu/pmu/pmuif/perf.h,
include/nvgpu/pmu/pmuif/perfvfe.h,
include/nvgpu/pmu/pmuif/perfpstate.h,
include/nvgpu/pmu/pmuif/pmgr.h,
include/nvgpu/pmu/pmuif/seq.h,
@@ -734,11 +733,11 @@ pmu:
sources: [ common/pmu/perf/change_seq.c,
common/pmu/perf/change_seq.h,
common/pmu/perf/pmu_perf.c,
common/pmu/perf/pmu_perf.h,
common/pmu/perf/vfe_equ.c,
common/pmu/perf/vfe_equ.h,
common/pmu/perf/vfe_var.c,
common/pmu/perf/vfe_var.h,
common/pmu/perf/ucode_perf_vfe_inf.h,
common/pmu/perf/perf_ps35.c,
common/pmu/perf/perf_pstate.c,
common/pmu/perf/perf_pstate.h,

12
drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
View File

@@ -596,6 +596,18 @@ static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid)
return -EINVAL;
}
u8 nvgpu_clk_fll_get_fmargin_idx(struct gk20a *g)
{
struct nvgpu_avfsfllobjs *pfllobjs = g->pmu->clk_pmu->avfs_fllobjs;
u8 fmargin_idx;
fmargin_idx = pfllobjs->freq_margin_vfe_idx;
if (fmargin_idx == 255U) {
return 0;
}
return fmargin_idx;
}
int nvgpu_clk_fll_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */

1
drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
View File

@@ -35,7 +35,6 @@
#include <nvgpu/pmu/pmu_pstate.h>
#include <nvgpu/pmu/perf_pstate.h>
#include "pmu_perf.h"
#include "change_seq.h"
#define SEQ_SCRIPT_CURR 0x0U

2
drivers/gpu/nvgpu/common/pmu/perf/perf_ps35.c
View File

@@ -29,8 +29,6 @@
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/cmd.h>
#include "pmu_perf.h"
static int pmu_set_boot_clk_runcb_fn(void *arg)
{
struct gk20a *g = (struct gk20a *)arg;

2
drivers/gpu/nvgpu/common/pmu/perf/pmu_perf.c
View File

@@ -26,8 +26,6 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/pmu/perf.h>
#include "pmu_perf.h"
int nvgpu_perf_pmu_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */

66
drivers/gpu/nvgpu/common/pmu/perf/pmu_perf.h
View File

@@ -1,66 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PMU_PERF_PERF_H
#define NVGPU_PMU_PERF_PERF_H
#define CTRL_PERF_VFE_VAR_TYPE_INVALID 0x00U
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED 0x01U
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT 0x02U
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM 0x03U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE 0x04U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY 0x05U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED 0x06U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE 0x07U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP 0x08U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE 0x09U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_CALLER_SPECIFIED 0x0AU
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_NONE 0x00U
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_VALUE 0x01U
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_OFFSET 0x02U
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_SCALE 0x03U
#define CTRL_PERF_VFE_EQU_TYPE_INVALID 0x00U
#define CTRL_PERF_VFE_EQU_TYPE_COMPARE 0x01U
#define CTRL_PERF_VFE_EQU_TYPE_MINMAX 0x02U
#define CTRL_PERF_VFE_EQU_TYPE_QUADRATIC 0x03U
#define CTRL_PERF_VFE_EQU_TYPE_SCALAR 0x04U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UNITLESS 0x00U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_FREQ_MHZ 0x01U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_UV 0x02U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VF_GAIN 0x03U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_DELTA_UV 0x04U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_WORK_TYPE 0x06U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UTIL_RATIO 0x07U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_WORK_FB_NORM 0x08U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_POWER_MW 0x09U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_PWR_OVER_UTIL_SLOPE 0x0AU
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VIN_CODE 0x0BU
#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03U
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_EQUAL 0x00U
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER_EQ 0x01U
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER 0x02U
#endif /* NVGPU_PMU_PERF_PERF_H */

118
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perfvfe.h → drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_vfe_inf.h
View File

@@ -22,13 +22,49 @@
#ifndef NVGPU_PMUIF_PERFVFE_H
#define NVGPU_PMUIF_PERFVFE_H
#include "bios.h"
#include "boardobj.h"
#include "ctrlperf.h"
#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2U
#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1U
#define CTRL_PERF_VFE_VAR_TYPE_INVALID 0x00U
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED 0x01U
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT 0x02U
#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM 0x03U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE 0x04U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY 0x05U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED 0x06U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE 0x07U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP 0x08U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE 0x09U
#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_CALLER_SPECIFIED 0x0AU
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_NONE 0x00U
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_VALUE 0x01U
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_OFFSET 0x02U
#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_SCALE 0x03U
#define CTRL_PERF_VFE_EQU_TYPE_INVALID 0x00U
#define CTRL_PERF_VFE_EQU_TYPE_COMPARE 0x01U
#define CTRL_PERF_VFE_EQU_TYPE_MINMAX 0x02U
#define CTRL_PERF_VFE_EQU_TYPE_QUADRATIC 0x03U
#define CTRL_PERF_VFE_EQU_TYPE_SCALAR 0x04U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UNITLESS 0x00U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_FREQ_MHZ 0x01U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_UV 0x02U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VF_GAIN 0x03U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_DELTA_UV 0x04U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_WORK_TYPE 0x06U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UTIL_RATIO 0x07U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_WORK_FB_NORM 0x08U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_POWER_MW 0x09U
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_PWR_OVER_UTIL_SLOPE 0x0AU
#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VIN_CODE 0x0BU
#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03U
#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2U
#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16U
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_EQUAL 0x00U
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER_EQ 0x01U
#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER 0x02U
union nv_pmu_perf_vfe_var_type_data {
u8 uid;
@@ -64,6 +100,13 @@ struct nv_pmu_perf_rpc_vfe_equ_eval {
union nv_pmu_perf_vfe_equ_result result;
};
struct nv_pmu_rpc_struct_perf_vfe_eval {
/*[IN/OUT] Must be first field in RPC structure */
struct nv_pmu_rpc_header hdr;
struct nv_pmu_perf_rpc_vfe_equ_eval data;
u32 scratch[1];
};
struct nv_pmu_perf_rpc_vfe_load {
bool b_load;
};
@@ -76,6 +119,16 @@ struct nv_pmu_perf_vfe_var_get_status_super {
struct nv_pmu_boardobj_query board_obj;
};
union ctrl_perf_vfe_var_single_sensed_fuse_value_data {
int signed_value;
u32 unsigned_value;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_value {
bool b_signed;
union ctrl_perf_vfe_var_single_sensed_fuse_value_data data;
};
struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status {
struct nv_pmu_perf_vfe_var_get_status_super super;
struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_integer;
@@ -141,6 +194,61 @@ struct nv_pmu_vfe_var_single_sensed {
struct nv_pmu_vfe_var_single super;
};
struct ctrl_bios_vfield_register_segment_super {
u8 low_bit;
u8 high_bit;
};
struct ctrl_bios_vfield_register_segment_reg {
struct ctrl_bios_vfield_register_segment_super super;
u32 addr;
};
struct ctrl_bios_vfield_register_segment_index_reg {
struct ctrl_bios_vfield_register_segment_super super;
u32 addr;
u32 reg_index;
u32 index;
};
union ctrl_bios_vfield_register_segment_data {
struct ctrl_bios_vfield_register_segment_reg reg;
struct ctrl_bios_vfield_register_segment_index_reg index_reg;
};
struct ctrl_bios_vfield_register_segment {
u8 type;
union ctrl_bios_vfield_register_segment_data data;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_info {
u8 segment_count;
struct ctrl_bios_vfield_register_segment
segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
};
struct ctrl_perf_vfe_var_single_sensed_fuse_override_info {
u32 fuse_val_override;
u8 b_fuse_regkey_override;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info {
struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
u32 fuse_val_default;
u32 hw_correction_scale;
int hw_correction_offset;
u8 v_field_id;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info {
struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
u8 ver_expected;
bool b_ver_check;
bool b_ver_check_ignore;
bool b_use_default_on_ver_check_fail;
u8 v_field_id_ver;
};
struct nv_pmu_vfe_var_single_sensed_fuse {
struct nv_pmu_vfe_var_single_sensed super;
struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info;

777
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
View File

@@ -25,21 +25,17 @@
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_fll.h>
#include <nvgpu/pmu/cmd.h>
#include "pmu_perf.h"
#include "ucode_perf_vfe_inf.h"
#include "vfe_equ.h"
static struct vfe_equ *construct_vfe_equ(struct gk20a *g, void *pargs);
static int devinit_get_vfe_equ_table(struct gk20a *g,
struct vfe_equs *pvfeequobjs);
#include "vfe_var.h"
static int vfe_equ_node_depending_mask_combine(struct gk20a *g,
struct boardobjgrp *pboardobjgrp, u8 equ_idx,
@@ -246,8 +242,6 @@ static int vfe_equs_pmudata_instget(struct gk20a *g,
struct nv_pmu_perf_vfe_equ_boardobj_grp_set *pgrp_set =
(struct nv_pmu_perf_vfe_equ_boardobj_grp_set *)(void *)pmuboardobjgrp;
nvgpu_log_info(g, " ");
/* check whether pmuboardobjgrp has a valid boardobj in index */
if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) {
return -EINVAL;
@@ -259,74 +253,334 @@ static int vfe_equs_pmudata_instget(struct gk20a *g,
return 0;
}
int nvgpu_vfe_equ_sw_setup(struct gk20a *g)
static int vfe_equ_pmudatainit_super(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
struct vfe_equs *pvfeequobjs;
struct vfe_vars *pvfevarobjs;
int status = 0;
struct vfe_equ *pvfe_equ;
struct nv_pmu_vfe_equ *pset;
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e255(g,
&g->perf_pmu->vfe_equobjs.super);
status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, "
"status - 0x%x", status);
goto done;
}
pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super;
pvfeequobjs = &(g->perf_pmu->vfe_equobjs);
pvfevarobjs = &(g->perf_pmu->vfe_varobjs);
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_EQU);
status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
perf, PERF, vfe_equ, VFE_EQU);
if (status != 0) {
nvgpu_err(g,
"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
status);
goto done;
}
pboardobjgrp->pmudatainit = vfe_equs_pmudatainit;
pboardobjgrp->pmudatainstget = vfe_equs_pmudata_instget;
status = devinit_get_vfe_equ_table(g, pvfeequobjs);
if (status != 0) {
goto done;
}
status = vfe_equ_dependency_mask_build(g, pvfeequobjs, pvfevarobjs);
if (status != 0) {
goto done;
}
done:
nvgpu_log_info(g, " done status %x", status);
return status;
}
int nvgpu_vfe_equ_pmu_setup(struct gk20a *g)
pvfe_equ = (struct vfe_equ *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ *)(void *)
ppmudata;
pset->var_idx = pvfe_equ->var_idx;
pset->equ_idx_next = pvfe_equ->equ_idx_next;
pset->output_type = pvfe_equ->output_type;
pset->out_range_min = pvfe_equ->out_range_min;
pset->out_range_max = pvfe_equ->out_range_max;
return status;
}
static int vfe_equ_construct_super(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
struct vfe_equ *pvfeequ;
struct vfe_equ *ptmpequ = (struct vfe_equ *)pargs;
int status = 0;
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super;
if (!pboardobjgrp->bconstructed) {
status = nvgpu_boardobj_construct_super(g, ppboardobj,
size, pargs);
if (status != 0) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
pvfeequ = (struct vfe_equ *)(void *)*ppboardobj;
status = boardobjgrpmask_e32_init(&pvfeequ->mask_depending_vars, NULL);
pvfeequ->super.pmudatainit =
vfe_equ_pmudatainit_super;
pvfeequ->var_idx = ptmpequ->var_idx;
pvfeequ->equ_idx_next = ptmpequ->equ_idx_next;
pvfeequ->output_type = ptmpequ->output_type;
pvfeequ->out_range_min = ptmpequ->out_range_min;
pvfeequ->out_range_max = ptmpequ->out_range_max;
return status;
}
static int vfe_equ_pmudatainit_compare(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_compare *pvfe_equ_compare;
struct nv_pmu_vfe_equ_compare *pset;
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_compare = (struct vfe_equ_compare *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_compare *)(void *)ppmudata;
pset->func_id = pvfe_equ_compare->func_id;
pset->equ_idx_true = pvfe_equ_compare->equ_idx_true;
pset->equ_idx_false = pvfe_equ_compare->equ_idx_false;
pset->criteria = pvfe_equ_compare->criteria;
return status;
}
static int vfe_equ_construct_compare(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_compare *pvfeequ;
struct vfe_equ_compare *ptmpequ =
(struct vfe_equ_compare *)pargs;
int status = 0;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_COMPARE) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_COMPARE);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_compare *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_compare;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_compare;
pvfeequ->func_id = ptmpequ->func_id;
pvfeequ->equ_idx_true = ptmpequ->equ_idx_true;
pvfeequ->equ_idx_false = ptmpequ->equ_idx_false;
pvfeequ->criteria = ptmpequ->criteria;
return status;
}
static int vfe_equ_pmudatainit_minmax(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_minmax *pvfe_equ_minmax;
struct nv_pmu_vfe_equ_minmax *pset;
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_minmax = (struct vfe_equ_minmax *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_minmax *)(void *)
ppmudata;
pset->b_max = pvfe_equ_minmax->b_max;
pset->equ_idx0 = pvfe_equ_minmax->equ_idx0;
pset->equ_idx1 = pvfe_equ_minmax->equ_idx1;
return status;
}
static int vfe_equ_construct_minmax(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_minmax *pvfeequ;
struct vfe_equ_minmax *ptmpequ =
(struct vfe_equ_minmax *)pargs;
int status = 0;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_MINMAX) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_MINMAX);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_minmax *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_minmax;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_minmax;
pvfeequ->b_max = ptmpequ->b_max;
pvfeequ->equ_idx0 = ptmpequ->equ_idx0;
pvfeequ->equ_idx1 = ptmpequ->equ_idx1;
return status;
}
static int vfe_equ_pmudatainit_quadratic(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_quadratic *pvfe_equ_quadratic;
struct nv_pmu_vfe_equ_quadratic *pset;
u32 i;
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_quadratic = (struct vfe_equ_quadratic *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_quadratic *)(void *)ppmudata;
for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++) {
pset->coeffs[i] = pvfe_equ_quadratic->coeffs[i];
}
return status;
}
static int vfe_equ_construct_quadratic(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_quadratic *pvfeequ;
struct vfe_equ_quadratic *ptmpequ =
(struct vfe_equ_quadratic *)pargs;
int status = 0;
u32 i;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_QUADRATIC) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_QUADRATIC);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_quadratic *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_quad;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_quadratic;
for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++) {
pvfeequ->coeffs[i] = ptmpequ->coeffs[i];
}
return status;
}
static int vfe_equ_pmudatainit_scalar(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_scalar *pvfe_equ_scalar;
struct nv_pmu_vfe_equ_scalar *pset;
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_scalar = (struct vfe_equ_scalar *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_scalar *)(void *)
ppmudata;
pset->equ_idx_to_scale = pvfe_equ_scalar->equ_idx_to_scale;
return status;
}
static int vfe_equ_construct_scalar(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_scalar *pvfeequ;
struct vfe_equ_scalar *ptmpequ =
(struct vfe_equ_scalar *)pargs;
int status = 0;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_SCALAR) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_SCALAR);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_scalar *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_equ_scalar;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_scalar;
pvfeequ->equ_idx_to_scale = ptmpequ->equ_idx_to_scale;
return status;
}
static struct vfe_equ *construct_vfe_equ(struct gk20a *g, void *pargs)
{
struct boardobj *board_obj_ptr = NULL;
int status;
switch (BOARDOBJ_GET_TYPE(pargs)) {
case CTRL_PERF_VFE_EQU_TYPE_COMPARE:
status = vfe_equ_construct_compare(g, &board_obj_ptr,
sizeof(struct vfe_equ_compare), pargs);
break;
case CTRL_PERF_VFE_EQU_TYPE_MINMAX:
status = vfe_equ_construct_minmax(g, &board_obj_ptr,
sizeof(struct vfe_equ_minmax), pargs);
break;
case CTRL_PERF_VFE_EQU_TYPE_QUADRATIC:
status = vfe_equ_construct_quadratic(g, &board_obj_ptr,
sizeof(struct vfe_equ_quadratic), pargs);
break;
case CTRL_PERF_VFE_EQU_TYPE_SCALAR:
status = vfe_equ_construct_scalar(g, &board_obj_ptr,
sizeof(struct vfe_equ_scalar), pargs);
break;
default:
status = -EINVAL;
break;
}
if (status != 0) {
return NULL;
}
nvgpu_log_info(g, " Done");
return status;
return (struct vfe_equ *)board_obj_ptr;
}
static int devinit_get_vfe_equ_table(struct gk20a *g,
@@ -353,8 +607,6 @@ static int devinit_get_vfe_equ_table(struct gk20a *g,
struct vfe_equ_scalar scalar;
} equ_data;
nvgpu_log_info(g, " ");
vfeequs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
CONTINUOUS_VIRTUAL_BINNING_TABLE);
@@ -593,344 +845,70 @@ done:
return status;
}
static int vfe_equ_pmudatainit_super(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
int nvgpu_vfe_equ_sw_setup(struct gk20a *g)
{
int status = 0;
struct vfe_equ *pvfe_equ;
struct nv_pmu_vfe_equ *pset;
nvgpu_log_info(g, " ");
status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ = (struct vfe_equ *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ *)(void *)
ppmudata;
pset->var_idx = pvfe_equ->var_idx;
pset->equ_idx_next = pvfe_equ->equ_idx_next;
pset->output_type = pvfe_equ->output_type;
pset->out_range_min = pvfe_equ->out_range_min;
pset->out_range_max = pvfe_equ->out_range_max;
return status;
}
static int vfe_equ_construct_super(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct vfe_equ *pvfeequ;
struct vfe_equ *ptmpequ = (struct vfe_equ *)pargs;
int status = 0;
status = nvgpu_boardobj_construct_super(g, ppboardobj,
size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ *)(void *)*ppboardobj;
status = boardobjgrpmask_e32_init(&pvfeequ->mask_depending_vars, NULL);
pvfeequ->super.pmudatainit =
vfe_equ_pmudatainit_super;
pvfeequ->var_idx = ptmpequ->var_idx;
pvfeequ->equ_idx_next = ptmpequ->equ_idx_next;
pvfeequ->output_type = ptmpequ->output_type;
pvfeequ->out_range_min = ptmpequ->out_range_min;
pvfeequ->out_range_max = ptmpequ->out_range_max;
return status;
}
static int vfe_equ_pmudatainit_compare(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_compare *pvfe_equ_compare;
struct nv_pmu_vfe_equ_compare *pset;
nvgpu_log_info(g, " ");
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_compare = (struct vfe_equ_compare *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_compare *)(void *)ppmudata;
pset->func_id = pvfe_equ_compare->func_id;
pset->equ_idx_true = pvfe_equ_compare->equ_idx_true;
pset->equ_idx_false = pvfe_equ_compare->equ_idx_false;
pset->criteria = pvfe_equ_compare->criteria;
return status;
}
static int vfe_equ_construct_compare(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_compare *pvfeequ;
struct vfe_equ_compare *ptmpequ =
(struct vfe_equ_compare *)pargs;
int status = 0;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_COMPARE) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_COMPARE);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_compare *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_compare;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_compare;
pvfeequ->func_id = ptmpequ->func_id;
pvfeequ->equ_idx_true = ptmpequ->equ_idx_true;
pvfeequ->equ_idx_false = ptmpequ->equ_idx_false;
pvfeequ->criteria = ptmpequ->criteria;
return status;
}
static int vfe_equ_pmudatainit_minmax(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_minmax *pvfe_equ_minmax;
struct nv_pmu_vfe_equ_minmax *pset;
nvgpu_log_info(g, " ");
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_minmax = (struct vfe_equ_minmax *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_minmax *)(void *)
ppmudata;
pset->b_max = pvfe_equ_minmax->b_max;
pset->equ_idx0 = pvfe_equ_minmax->equ_idx0;
pset->equ_idx1 = pvfe_equ_minmax->equ_idx1;
return status;
}
static int vfe_equ_construct_minmax(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_minmax *pvfeequ;
struct vfe_equ_minmax *ptmpequ =
(struct vfe_equ_minmax *)pargs;
int status = 0;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_MINMAX) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_MINMAX);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_minmax *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_minmax;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_minmax;
pvfeequ->b_max = ptmpequ->b_max;
pvfeequ->equ_idx0 = ptmpequ->equ_idx0;
pvfeequ->equ_idx1 = ptmpequ->equ_idx1;
return status;
}
static int vfe_equ_pmudatainit_quadratic(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_quadratic *pvfe_equ_quadratic;
struct nv_pmu_vfe_equ_quadratic *pset;
u32 i;
nvgpu_log_info(g, " ");
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_quadratic = (struct vfe_equ_quadratic *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_quadratic *)(void *)ppmudata;
for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++) {
pset->coeffs[i] = pvfe_equ_quadratic->coeffs[i];
}
return status;
}
static int vfe_equ_construct_quadratic(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_quadratic *pvfeequ;
struct vfe_equ_quadratic *ptmpequ =
(struct vfe_equ_quadratic *)pargs;
int status = 0;
u32 i;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_QUADRATIC) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_QUADRATIC);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_quadratic *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_quad;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_quadratic;
for (i = 0; i < CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT; i++) {
pvfeequ->coeffs[i] = ptmpequ->coeffs[i];
}
return status;
}
static int vfe_equ_pmudatainit_scalar(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
struct vfe_equ_scalar *pvfe_equ_scalar;
struct nv_pmu_vfe_equ_scalar *pset;
nvgpu_log_info(g, " ");
status = vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
}
pvfe_equ_scalar = (struct vfe_equ_scalar *)(void *)board_obj_ptr;
pset = (struct nv_pmu_vfe_equ_scalar *)(void *)
ppmudata;
pset->equ_idx_to_scale = pvfe_equ_scalar->equ_idx_to_scale;
return status;
}
static int vfe_equ_construct_scalar(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_equ_scalar *pvfeequ;
struct vfe_equ_scalar *ptmpequ =
(struct vfe_equ_scalar *)pargs;
int status = 0;
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_SCALAR) {
return -EINVAL;
}
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_EQU_TYPE_SCALAR);
status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfeequ = (struct vfe_equ_scalar *)(void *)*ppboardobj;
pvfeequ->super.mask_depending_build =
vfe_equ_build_depending_mask_equ_scalar;
pvfeequ->super.super.pmudatainit =
vfe_equ_pmudatainit_scalar;
pvfeequ->equ_idx_to_scale = ptmpequ->equ_idx_to_scale;
return status;
}
static struct vfe_equ *construct_vfe_equ(struct gk20a *g, void *pargs)
{
struct boardobj *board_obj_ptr = NULL;
int status;
struct boardobjgrp *pboardobjgrp = NULL;
struct vfe_equs *pvfeequobjs;
struct vfe_vars *pvfevarobjs;
nvgpu_log_info(g, " ");
switch (BOARDOBJ_GET_TYPE(pargs)) {
case CTRL_PERF_VFE_EQU_TYPE_COMPARE:
status = vfe_equ_construct_compare(g, &board_obj_ptr,
sizeof(struct vfe_equ_compare), pargs);
break;
case CTRL_PERF_VFE_EQU_TYPE_MINMAX:
status = vfe_equ_construct_minmax(g, &board_obj_ptr,
sizeof(struct vfe_equ_minmax), pargs);
break;
case CTRL_PERF_VFE_EQU_TYPE_QUADRATIC:
status = vfe_equ_construct_quadratic(g, &board_obj_ptr,
sizeof(struct vfe_equ_quadratic), pargs);
break;
case CTRL_PERF_VFE_EQU_TYPE_SCALAR:
status = vfe_equ_construct_scalar(g, &board_obj_ptr,
sizeof(struct vfe_equ_scalar), pargs);
break;
default:
status = -EINVAL;
break;
}
status = nvgpu_boardobjgrp_construct_e255(g,
&g->perf_pmu->vfe_equobjs.super);
if (status != 0) {
return NULL;
nvgpu_err(g,
"error creating boardobjgrp for clk domain, "
"status - 0x%x", status);
goto done;
}
pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super;
pvfeequobjs = &(g->perf_pmu->vfe_equobjs);
pvfevarobjs = &(g->perf_pmu->vfe_varobjs);
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_EQU);
status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
perf, PERF, vfe_equ, VFE_EQU);
if (status != 0) {
nvgpu_err(g,
"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
status);
goto done;
}
pboardobjgrp->pmudatainit = vfe_equs_pmudatainit;
pboardobjgrp->pmudatainstget = vfe_equs_pmudata_instget;
status = devinit_get_vfe_equ_table(g, pvfeequobjs);
if (status != 0) {
goto done;
}
status = vfe_equ_dependency_mask_build(g, pvfeequobjs, pvfevarobjs);
if (status != 0) {
goto done;
}
done:
nvgpu_log_info(g, " done status %x", status);
return status;
}
int nvgpu_vfe_equ_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
nvgpu_log_info(g, "Done");
return (struct vfe_equ *)board_obj_ptr;
return status;
}
int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv)
@@ -966,10 +944,9 @@ int nvgpu_vfe_get_freq_margin_limit(struct gk20a *g, u32 *fmargin_mhz)
struct nv_pmu_rpc_struct_perf_vfe_eval rpc;
int status = 0;
u8 fmargin_idx;
struct nvgpu_avfsfllobjs *pfllobjs = g->pmu->clk_pmu->avfs_fllobjs;
fmargin_idx = pfllobjs->freq_margin_vfe_idx;
if (fmargin_idx == 255U) {
fmargin_idx = nvgpu_clk_fll_get_fmargin_idx(g);
if (fmargin_idx == 0U) {
return 0;
}

18
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.h
View File

@@ -24,24 +24,6 @@
#ifndef NVGPU_PERF_VFE_EQU_H
#define NVGPU_PERF_VFE_EQU_H
#include <nvgpu/boardobjgrp.h>
#include "vfe_var.h"
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#define VFE_EQU_GET(_pperf, _idx) \
((struct vfe_equ *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
&((_pperf)->vfe.equs.super.super), (_idx)))
#define VFE_EQU_IDX_IS_VALID(_pperf, _idx) \
boardobjgrp_idxisvalid(&((_pperf)->vfe.equs.super.super), (_idx))
#define VFE_EQU_OUTPUT_TYPE_IS_VALID(_pperf, _idx, _outputtype) \
(VFE_EQU_IDX_IS_VALID((_pperf), (_idx)) && \
((_outputtype) != CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UNITLESS) && \
((VFE_EQU_GET((_pperf), (_idx))->outputtype == (_outputtype)) || \
(VFE_EQU_GET((_pperf), (_idx))->outputtype == \
CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UNITLESS)))
struct vfe_equ {
struct boardobj super;
u8 var_idx;

375
drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c
View File

@@ -26,20 +26,11 @@
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/string.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/pmuif/ctrlvolt.h>
#include <nvgpu/pmu/pmuif/ctrlperf.h>
#include <nvgpu/pmu/perf.h>
#include "pmu_perf.h"
#include "ucode_perf_vfe_inf.h"
#include "vfe_var.h"
static int devinit_get_vfe_var_table(struct gk20a *g,
struct vfe_vars *pvfevarobjs);
static int vfe_var_construct_single(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs);
static int vfe_vars_pmudatainit(struct gk20a *g,
struct boardobjgrp *pboardobjgrp,
struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
@@ -72,8 +63,6 @@ static int vfe_vars_pmudata_instget(struct gk20a *g,
(struct nv_pmu_perf_vfe_var_boardobj_grp_set *)(void *)
pmuboardobjgrp;
nvgpu_log_info(g, " ");
/*check whether pmuboardobjgrp has a valid boardobj in index*/
if (idx >= CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) {
return -EINVAL;
@@ -111,8 +100,6 @@ static int vfe_var_get_s_param_value(struct gk20a *g,
pstatus = (struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status *)
(void *)ppmudata;
nvgpu_log_info(g, " ");
if (pstatus->super.board_obj.type !=
fuse_value->super.super.super.super.type) {
nvgpu_err(g, "pmu data and boardobj type not matching");
@@ -137,52 +124,6 @@ static int vfe_var_get_s_param_value(struct gk20a *g,
return 0;
}
int nvgpu_vfe_var_boardobj_grp_get_status(struct gk20a *g) {
struct boardobjgrp *pboardobjgrp;
struct boardobjgrpmask *pboardobjgrpmask;
struct nv_pmu_boardobjgrp_super *pboardobjgrppmu;
struct boardobj *pboardobj = NULL;
struct nv_pmu_boardobj_query *pboardobjpmustatus = NULL;
struct vfe_var_single_sensed_fuse *single_sensed_fuse = NULL;
int status;
u8 index;
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
pboardobjgrpmask = &g->perf_pmu->vfe_varobjs.super.mask.super;
status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask);
if (status != 0) {
nvgpu_err(g, "err getting boardobjs from pmu");
return status;
}
pboardobjgrppmu = pboardobjgrp->pmu.getstatus.buf;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
single_sensed_fuse = (struct vfe_var_single_sensed_fuse *)
(void *)pboardobj;
status = pboardobjgrp->pmustatusinstget(g,
(struct nv_pmu_boardobjgrp *)(void *)pboardobjgrppmu,
&pboardobjpmustatus, index);
if (status != 0) {
nvgpu_err(g, "could not get status object instance");
return status;
}
/* At present we are updating only s_param,
* in future we can add other fields if required */
if (single_sensed_fuse->vfield_info.v_field_id ==
VFIELD_ID_S_PARAM) {
status = vfe_var_get_s_param_value(g, single_sensed_fuse,
(struct nv_pmu_boardobj *)(void *)pboardobjpmustatus);
if (status != 0) {
nvgpu_err(g, "could not get single sensed fuse value");
return status;
}
break;
}
}
return 0;
}
static int vfe_var_dependency_mask_build(struct gk20a *g,
struct vfe_vars *pvfe_vars)
{
@@ -224,85 +165,6 @@ static int vfe_var_dependency_mask_build(struct gk20a *g,
return status;
}
int nvgpu_vfe_var_sw_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
struct vfe_vars *pvfevarobjs;
nvgpu_log_info(g, " ");
status = nvgpu_boardobjgrp_construct_e32(g,
&g->perf_pmu->vfe_varobjs.super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, "
"status - 0x%x", status);
goto done;
}
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
pvfevarobjs = &g->perf_pmu->vfe_varobjs;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_VAR);
status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
perf, PERF, vfe_var, VFE_VAR);
if (status != 0) {
nvgpu_err(g,
"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
status);
goto done;
}
pboardobjgrp->pmudatainit = vfe_vars_pmudatainit;
pboardobjgrp->pmudatainstget = vfe_vars_pmudata_instget;
pboardobjgrp->pmustatusinstget = vfe_vars_pmustatus_instget;
status = devinit_get_vfe_var_table(g, pvfevarobjs);
if (status != 0) {
goto done;
}
status = vfe_var_dependency_mask_build(g, pvfevarobjs);
if (status != 0) {
goto done;
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->perf_pmu->vfe_varobjs.super.super,
perf, PERF, vfe_var, VFE_VAR);
if (status != 0) {
nvgpu_err(g,
"error constructing PMU_BOARDOBJ_CMD_GRP_GET_STATUS interface - 0x%x",
status);
goto done;
}
done:
nvgpu_log_info(g, " done status %x", status);
return status;
}
int nvgpu_vfe_var_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
nvgpu_log_info(g, " ");
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
nvgpu_log_info(g, "Done");
return status;
}
static int dev_init_get_vfield_info(struct gk20a *g,
struct vfe_var_single_sensed_fuse *pvfevar)
{
@@ -480,8 +342,6 @@ static int vfe_var_construct_super(struct gk20a *g,
struct vfe_var *ptmpvar = (struct vfe_var *)pargs;
int status;
nvgpu_log_info(g, " ");
status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
@@ -518,13 +378,7 @@ static int vfe_var_pmudatainit_derived(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_super(g, board_obj_ptr, ppmudata);
return status;
return vfe_var_pmudatainit_super(g, board_obj_ptr, ppmudata);
}
static int vfe_var_construct_derived(struct gk20a *g,
@@ -650,8 +504,6 @@ static int vfe_var_pmudatainit_derived_sum(struct gk20a *g,
struct vfe_var_derived_sum *pvfe_var_derived_sum;
struct nv_pmu_vfe_var_derived_sum *pset;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_derived(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
@@ -742,8 +594,6 @@ static int vfe_var_pmudatainit_single(struct gk20a *g,
struct vfe_var_single *pvfe_var_single;
struct nv_pmu_vfe_var_single *pset;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_super(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
@@ -767,8 +617,6 @@ static int vfe_var_pmudatainit_single_frequency(struct gk20a *g,
struct vfe_var_single_frequency *pvfe_var_single_frequency;
struct nv_pmu_vfe_var_single_frequency *pset;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_single(g, board_obj_ptr, ppmudata);
pvfe_var_single_frequency = (struct vfe_var_single_frequency *)
@@ -789,6 +637,33 @@ static int vfe_var_build_depending_mask_single(struct gk20a *g,
pvfe_var->super.idx);
}
static int vfe_var_construct_single(struct gk20a *g,
struct boardobj **ppboardobj, size_t size, void *pargs)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_var_single *pvfevar;
int status = 0;
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE);
status = vfe_var_construct_super(g, ppboardobj, size, pargs);
if (status != 0) {
return -EINVAL;
}
pvfevar = (struct vfe_var_single *)(void *)*ppboardobj;
pvfevar->super.mask_depending_build =
vfe_var_build_depending_mask_single;
pvfevar->super.super.pmudatainit =
vfe_var_pmudatainit_single;
pvfevar->override_type =
(u8)CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_NONE;
pvfevar->override_value = 0;
nvgpu_log_info(g, "Done");
return status;
}
static int vfe_var_construct_single_frequency(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
@@ -799,8 +674,6 @@ static int vfe_var_construct_single_frequency(struct gk20a *g,
(struct vfe_var_single_frequency *)pargs;
int status = 0;
nvgpu_log_info(g, " ");
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY) {
return -EINVAL;
}
@@ -834,8 +707,6 @@ static int vfe_var_pmudatainit_single_caller_specified(struct gk20a *g,
*pvfe_var_single_caller_specified;
struct nv_pmu_vfe_var_single_caller_specified *pset;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_single(g, board_obj_ptr, ppmudata);
pvfe_var_single_caller_specified =
@@ -858,8 +729,6 @@ static int vfe_var_construct_single_caller_specified(struct gk20a *g,
(struct vfe_var_single_caller_specified *)pargs;
int status = 0;
nvgpu_log_info(g, " ");
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY) {
return -EINVAL;
}
@@ -887,13 +756,7 @@ static int vfe_var_pmudatainit_single_sensed(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_single(g, board_obj_ptr, ppmudata);
return status;
return vfe_var_pmudatainit_single(g, board_obj_ptr, ppmudata);
}
static int vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g,
@@ -904,8 +767,6 @@ static int vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g,
struct vfe_var_single_sensed_fuse *pvfe_var_single_sensed_fuse;
struct nv_pmu_vfe_var_single_sensed_fuse *pset;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
@@ -939,11 +800,8 @@ static int vfe_var_construct_single_sensed(struct gk20a *g,
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_var_single_sensed *pvfevar;
int status = 0;
nvgpu_log_info(g, " ");
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED);
status = vfe_var_construct_single(g, ppboardobj, size, pargs);
if (status != 0) {
@@ -970,8 +828,6 @@ static int vfe_var_construct_single_sensed_fuse(struct gk20a *g,
(struct vfe_var_single_sensed_fuse *)pargs;
int status = 0;
nvgpu_log_info(g, " ");
if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE) {
return -EINVAL;
}
@@ -1036,8 +892,6 @@ static int vfe_var_pmudatainit_single_sensed_temp(struct gk20a *g,
struct vfe_var_single_sensed_temp *pvfe_var_single_sensed_temp;
struct nv_pmu_vfe_var_single_sensed_temp *pset;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata);
if (status != 0) {
return status;
@@ -1102,13 +956,7 @@ static int vfe_var_pmudatainit_single_voltage(struct gk20a *g,
struct boardobj *board_obj_ptr,
struct nv_pmu_boardobj *ppmudata)
{
int status = 0;
nvgpu_log_info(g, " ");
status = vfe_var_pmudatainit_single(g, board_obj_ptr, ppmudata);
return status;
return vfe_var_pmudatainit_single(g, board_obj_ptr, ppmudata);
}
static int vfe_var_construct_single_voltage(struct gk20a *g,
@@ -1146,7 +994,6 @@ static struct vfe_var *construct_vfe_var(struct gk20a *g, void *pargs)
struct boardobj *board_obj_ptr = NULL;
int status;
nvgpu_log_info(g, " ");
switch (BOARDOBJ_GET_TYPE(pargs)) {
case CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT:
status = vfe_var_construct_derived_product(g, &board_obj_ptr,
@@ -1229,8 +1076,6 @@ static int devinit_get_vfe_var_table(struct gk20a *g,
struct vfe_var_single_caller_specified single_caller_specified;
} var_data;
nvgpu_log_info(g, " ");
vfevars_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
CONTINUOUS_VIRTUAL_BINNING_TABLE);
@@ -1417,31 +1262,155 @@ done:
return status;
}
static int vfe_var_construct_single(struct gk20a *g,
struct boardobj **ppboardobj,
size_t size, void *pargs)
static int vfe_var_boardobj_grp_get_status(struct gk20a *g)
{
struct boardobj *ptmpobj = (struct boardobj *)pargs;
struct vfe_var_single *pvfevar;
int status = 0;
nvgpu_log_info(g, " ");
struct boardobjgrp *pboardobjgrp;
struct boardobjgrpmask *pboardobjgrpmask;
struct nv_pmu_boardobjgrp_super *pboardobjgrppmu;
struct boardobj *pboardobj = NULL;
struct nv_pmu_boardobj_query *pboardobjpmustatus = NULL;
struct vfe_var_single_sensed_fuse *single_sensed_fuse = NULL;
int status;
u8 index;
ptmpobj->type_mask |= (u32)BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE);
status = vfe_var_construct_super(g, ppboardobj, size, pargs);
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
pboardobjgrpmask = &g->perf_pmu->vfe_varobjs.super.mask.super;
status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask);
if (status != 0) {
nvgpu_err(g, "err getting boardobjs from pmu");
return status;
}
pboardobjgrppmu = pboardobjgrp->pmu.getstatus.buf;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
single_sensed_fuse = (struct vfe_var_single_sensed_fuse *)
(void *)pboardobj;
status = pboardobjgrp->pmustatusinstget(g,
(struct nv_pmu_boardobjgrp *)(void *)pboardobjgrppmu,
&pboardobjpmustatus, index);
if (status != 0) {
nvgpu_err(g, "could not get status object instance");
return status;
}
/* At present we are updating only s_param,
* in future we can add other fields if required */
if (single_sensed_fuse->vfield_info.v_field_id ==
VFIELD_ID_S_PARAM) {
status = vfe_var_get_s_param_value(g,
single_sensed_fuse,
(struct nv_pmu_boardobj *)
(void *)pboardobjpmustatus);
if (status != 0) {
nvgpu_err(g,
"could not get single sensed fuse value");
return status;
}
break;
}
}
return 0;
}
int nvgpu_vfe_var_sw_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
struct vfe_vars *pvfevarobjs;
status = nvgpu_boardobjgrp_construct_e32(g,
&g->perf_pmu->vfe_varobjs.super);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for clk domain, "
"status - 0x%x", status);
goto done;
}
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
pvfevarobjs = &g->perf_pmu->vfe_varobjs;
BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_VAR);
status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
perf, PERF, vfe_var, VFE_VAR);
if (status != 0) {
nvgpu_err(g, "error constructing GRP_SET interface - 0x%x",
status);
goto done;
}
pboardobjgrp->pmudatainit = vfe_vars_pmudatainit;
pboardobjgrp->pmudatainstget = vfe_vars_pmudata_instget;
pboardobjgrp->pmustatusinstget = vfe_vars_pmustatus_instget;
status = devinit_get_vfe_var_table(g, pvfevarobjs);
if (status != 0) {
goto done;
}
status = vfe_var_dependency_mask_build(g, pvfevarobjs);
if (status != 0) {
goto done;
}
status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
&g->perf_pmu->vfe_varobjs.super.super,
perf, PERF, vfe_var, VFE_VAR);
if (status != 0) {
nvgpu_err(g,
"error constructing GRP_GET_STATUS interface - 0x%x",
status);
goto done;
}
done:
nvgpu_log_info(g, " done status %x", status);
return status;
}
int nvgpu_vfe_var_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
if (!pboardobjgrp->bconstructed) {
return -EINVAL;
}
pvfevar = (struct vfe_var_single *)(void *)*ppboardobj;
pvfevar->super.mask_depending_build =
vfe_var_build_depending_mask_single;
pvfevar->super.super.pmudatainit =
vfe_var_pmudatainit_single;
pvfevar->override_type = (u8)CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_NONE;
pvfevar->override_value = 0;
status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
nvgpu_log_info(g, "Done");
return status;
}
int nvgpu_vfe_var_get_s_param(struct gk20a *g, u64 *s_param)
{
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
struct vfe_var_single_sensed_fuse *single_sensed_fuse = NULL;
u8 index;
int status;
status = vfe_var_boardobj_grp_get_status(g);
if (status != 0) {
nvgpu_err(g, "Vfe_var get status failed");
return status;
}
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
single_sensed_fuse = (struct vfe_var_single_sensed_fuse *)
(void *)pboardobj;
if (single_sensed_fuse->vfield_info.v_field_id ==
VFIELD_ID_S_PARAM) {
*s_param = single_sensed_fuse->fuse_value_hw_integer;
}
}
return status;
}

12
drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h
View File

@@ -23,18 +23,6 @@
#ifndef NVGPU_PERF_VFE_VAR_H
#define NVGPU_PERF_VFE_VAR_H
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#define VFE_VAR_GET(_pperf, _idx) \
((struct vfe_var)BOARDOBJGRP_OBJ_GET_BY_IDX( \
&((_pperf)->vfe.vars.super.super), (_idx)))
#define VFE_VAR_IDX_IS_VALID(_pperf, _idx) \
boardobjgrp_idxisvalid(&((_pperf)->vfe.vars.super.super), (_idx))
struct vfe_var {
struct boardobj super;
u32 out_range_min;

6
drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h
View File

@@ -139,12 +139,6 @@ struct nv_pmu_super_surface {
clk_vf_point_grp_get_status;
} clk;
struct {
struct nv_pmu_perf_vfe_equ_boardobj_grp_set_pack
vfe_equ_grp_set;
struct nv_pmu_perf_vfe_var_boardobj_grp_set_pack
vfe_var_grp_set;
struct nv_pmu_perf_vfe_var_boardobj_grp_get_status_pack
vfe_var_grp_get_status;
struct nv_pmu_perf_pstate_boardobj_grp_set
pstate_grp_set;
struct nv_pmu_perf_pstate_boardobj_grp_get_status

1
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
View File

@@ -32,6 +32,7 @@
#include "volt_rail.h"
#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16U
static int volt_rail_state_init(struct gk20a *g,
struct voltage_rail *pvolt_rail)

1
drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
View File

@@ -37,6 +37,7 @@ struct gk20a;
#include <nvgpu/cond.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/pmuif/ctrlclk.h>
#include <nvgpu/pmu/perf_pstate.h>
#include <nvgpu/pmu/volt.h>

1
drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h
View File

@@ -73,5 +73,6 @@ int nvgpu_clk_fll_init_pmupstate(struct gk20a *g);
void nvgpu_clk_fll_free_pmupstate(struct gk20a *g);
int nvgpu_clk_fll_sw_setup(struct gk20a *g);
int nvgpu_clk_fll_pmu_setup(struct gk20a *g);
u8 nvgpu_clk_fll_get_fmargin_idx(struct gk20a *g);
#endif /* NVGPU_PMU_CLK_FLL_H */

4
drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h
View File

@@ -25,12 +25,12 @@
#include <nvgpu/types.h>
#include <nvgpu/cond.h>
#include <nvgpu/thread.h>
#include <nvgpu/pmu/perf_pstate.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/lpwr.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/pmu/perf_pstate.h>
#include <nvgpu/pmu/pmuif/perf.h>
struct gk20a;
@@ -102,7 +102,7 @@ int nvgpu_vfe_equ_pmu_setup(struct gk20a *g);
int nvgpu_vfe_var_sw_setup(struct gk20a *g);
int nvgpu_vfe_var_pmu_setup(struct gk20a *g);
int nvgpu_vfe_var_boardobj_grp_get_status(struct gk20a *g);
int nvgpu_vfe_var_get_s_param(struct gk20a *g, u64 *s_param);
int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv);
int nvgpu_vfe_get_freq_margin_limit(struct gk20a *g, u32 *fmargin_mhz);

67
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlperf.h
View File

@@ -39,73 +39,6 @@ struct ctrl_perf_volt_rail_list {
rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
};
union ctrl_perf_vfe_var_single_sensed_fuse_value_data {
int signed_value;
u32 unsigned_value;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_value {
bool b_signed;
union ctrl_perf_vfe_var_single_sensed_fuse_value_data data;
};
struct ctrl_bios_vfield_register_segment_super {
u8 low_bit;
u8 high_bit;
};
struct ctrl_bios_vfield_register_segment_reg {
struct ctrl_bios_vfield_register_segment_super super;
u32 addr;
};
struct ctrl_bios_vfield_register_segment_index_reg {
struct ctrl_bios_vfield_register_segment_super super;
u32 addr;
u32 reg_index;
u32 index;
};
union ctrl_bios_vfield_register_segment_data {
struct ctrl_bios_vfield_register_segment_reg reg;
struct ctrl_bios_vfield_register_segment_index_reg index_reg;
};
struct ctrl_bios_vfield_register_segment {
u8 type;
union ctrl_bios_vfield_register_segment_data data;
};
#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1U
struct ctrl_perf_vfe_var_single_sensed_fuse_info {
u8 segment_count;
struct ctrl_bios_vfield_register_segment
segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX];
};
struct ctrl_perf_vfe_var_single_sensed_fuse_override_info {
u32 fuse_val_override;
u8 b_fuse_regkey_override;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info {
struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
u32 fuse_val_default;
u32 hw_correction_scale;
int hw_correction_offset;
u8 v_field_id;
};
struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info {
struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse;
u8 ver_expected;
bool b_ver_check;
bool b_ver_check_ignore;
bool b_use_default_on_ver_check_fail;
u8 v_field_id_ver;
};
/*----------------------------- CHANGES_SEQ --------------------------------*/
/*!

1
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/nvgpu_cmdif.h
View File

@@ -25,7 +25,6 @@
#include "cmn.h"
#include "init.h"
#include "ap.h"
#include "perfvfe.h"
#include "thermsensor.h"
#include "seq.h"

8
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h
View File

@@ -23,7 +23,6 @@
#define NVGPU_PMUIF_PERF_H
#include "volt.h"
#include "perfvfe.h"
#include "perfpstate.h"
#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U)
@@ -142,11 +141,4 @@ struct perf_change_seq_pmu_script {
steps[CTRL_PERF_CHANGE_SEQ_SCRIPT_VF_SWITCH_MAX_STEPS];
};
struct nv_pmu_rpc_struct_perf_vfe_eval {
/*[IN/OUT] Must be first field in RPC structure */
struct nv_pmu_rpc_header hdr;
struct nv_pmu_perf_rpc_vfe_equ_eval data;
u32 scratch[1];
};
#endif /* NVGPU_PMUIF_PERF_H */

22
drivers/gpu/nvgpu/os/linux/debug_s_param.c
View File

@@ -18,34 +18,18 @@
#include "os_linux.h"
#include "include/nvgpu/bios.h"
#include <common/pmu/perf/vfe_var.h>
#include <nvgpu/pmu/perf.h>
static int get_s_param_info(void *data, u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
struct boardobjgrp *pboardobjgrp;
struct boardobj *pboardobj = NULL;
struct vfe_var_single_sensed_fuse *single_sensed_fuse = NULL;
int status;
u8 index;
int status = 0;
status = nvgpu_vfe_var_boardobj_grp_get_status(g);
status = nvgpu_vfe_var_get_s_param(g, val);
if(status != 0) {
nvgpu_err(g, "Vfe_var get status failed");
nvgpu_err(g, "Vfe_var get s_param failed");
return status;
}
pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct boardobj*, pboardobj, index) {
single_sensed_fuse = (struct vfe_var_single_sensed_fuse *)
(void *)pboardobj;
if(single_sensed_fuse->vfield_info.v_field_id ==
VFIELD_ID_S_PARAM) {
*val = single_sensed_fuse->fuse_value_hw_integer;
}
}
return status;
}
DEFINE_SIMPLE_ATTRIBUTE(s_param_fops, get_s_param_info , NULL, "%llu\n");