From 8f5adab299da546fc0499a31690dedbcd380bc78 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 17 Feb 2023 15:37:40 -0800 Subject: [PATCH] gpu: nvgpu: .preempt_tsg move to use runlist_id/tsgid It's for making .preempt_tsg reusable on server side. Jira GVSCI-15770 Change-Id: Id9f477baa29cb63fb0e1d1650f4b1e6a2fa248c0 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863441 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Ramesh Mylavarapu Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/fifo/preempt.c | 29 ++++++++++--------- drivers/gpu/nvgpu/common/fifo/tsg.c | 11 +++++-- drivers/gpu/nvgpu/common/gr/gr_setup.c | 4 +-- .../gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.c | 9 +++--- .../gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.h | 4 +-- drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c | 17 ++++++----- drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.h | 4 +-- .../gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c | 4 +-- drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c | 2 +- drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c | 6 ++-- drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h | 7 +++-- drivers/gpu/nvgpu/include/nvgpu/preempt.h | 7 +++-- drivers/gpu/nvgpu/include/nvgpu/tsg.h | 13 ++++++++- .../gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 1 + drivers/gpu/nvgpu/os/linux/ioctl_tsg.c | 4 +-- userspace/units/fifo/channel/nvgpu-channel.c | 4 +-- .../fifo/preempt/gv11b/nvgpu-preempt-gv11b.c | 7 +++-- userspace/units/fifo/preempt/nvgpu-preempt.c | 6 ++-- userspace/units/fifo/tsg/nvgpu-tsg.c | 6 ++-- userspace/units/gr/setup/nvgpu-gr-setup.c | 7 ++--- 20 files changed, 90 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/preempt.c b/drivers/gpu/nvgpu/common/fifo/preempt.c index b9adfceed..75fbddad6 100644 --- a/drivers/gpu/nvgpu/common/fifo/preempt.c +++ b/drivers/gpu/nvgpu/common/fifo/preempt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -40,8 +40,9 @@ u32 nvgpu_preempt_get_timeout(struct gk20a *g) return g->ctxsw_timeout_period_ms; } -int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +int nvgpu_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { + struct nvgpu_runlist *runlist; int ret = 0; u32 preempt_retry_count = 10U; u32 preempt_retry_timeout = @@ -51,17 +52,19 @@ int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) int mutex_ret = 0; #endif - nvgpu_log_fn(g, "tsgid: %d", tsg->tsgid); + nvgpu_log_fn(g, "tsgid: %d", tsgid); - if (tsg->runlist == NULL) { + if (runlist_id == INVAL_ID) { return 0; } + runlist = g->fifo.runlists[runlist_id]; + do { - nvgpu_mutex_acquire(&tsg->runlist->runlist_lock); + nvgpu_mutex_acquire(&runlist->runlist_lock); if (nvgpu_is_errata_present(g, NVGPU_ERRATA_2016608)) { - nvgpu_runlist_set_state(g, BIT32(tsg->runlist->id), + nvgpu_runlist_set_state(g, BIT32(runlist_id), RUNLIST_DISABLED); } @@ -69,7 +72,7 @@ int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif - g->ops.fifo.preempt_trigger(g, tsg->tsgid, ID_TYPE_TSG); + g->ops.fifo.preempt_trigger(g, tsgid, ID_TYPE_TSG); /* * Poll for preempt done. if stalling interrupts are pending @@ -80,7 +83,7 @@ int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) * the engines hung and set the runlist reset_eng_bitmask * and mark preemption completion. */ - ret = g->ops.fifo.is_preempt_pending(g, tsg->tsgid, + ret = g->ops.fifo.is_preempt_pending(g, tsgid, ID_TYPE_TSG, preempt_retry_count > 1U); #ifdef CONFIG_NVGPU_LS_PMU @@ -93,11 +96,11 @@ int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) } #endif if (nvgpu_is_errata_present(g, NVGPU_ERRATA_2016608)) { - nvgpu_runlist_set_state(g, BIT32(tsg->runlist->id), + nvgpu_runlist_set_state(g, BIT32(runlist_id), RUNLIST_ENABLED); } - nvgpu_mutex_release(&tsg->runlist->runlist_lock); + nvgpu_mutex_release(&runlist->runlist_lock); if (ret != -EAGAIN) { break; @@ -113,9 +116,9 @@ int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) if (nvgpu_platform_is_silicon(g)) { nvgpu_err(g, "preempt timed out for tsgid: %u, " "ctxsw timeout will trigger recovery if needed", - tsg->tsgid); + tsgid); } else { - nvgpu_rc_preempt_timeout(g, tsg); + nvgpu_rc_preempt_timeout(g, &g->fifo.tsg[tsgid]); } } return ret; @@ -127,7 +130,7 @@ int nvgpu_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch); if (tsg != NULL) { - err = g->ops.fifo.preempt_tsg(ch->g, tsg); + err = nvgpu_tsg_preempt(ch->g, tsg); } else { err = g->ops.fifo.preempt_channel(ch->g, ch); } diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 8882f24f1..87412305d 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -574,7 +574,7 @@ static int nvgpu_tsg_unbind_channel_common(struct nvgpu_tsg *tsg, /* Disable TSG and examine status before unbinding channel */ g->ops.tsg.disable(tsg); - err = g->ops.fifo.preempt_tsg(g, tsg); + err = nvgpu_tsg_preempt(g, tsg); if (err != 0) { goto fail_enable_tsg; } @@ -1604,7 +1604,7 @@ void nvgpu_tsg_abort(struct gk20a *g, struct nvgpu_tsg *tsg, bool preempt) * operation will print the error and ctxsw timeout may trigger * a recovery if needed. */ - (void)g->ops.fifo.preempt_tsg(g, tsg); + (void)nvgpu_tsg_preempt(g, tsg); } nvgpu_rwsem_down_read(&tsg->ch_list_lock); @@ -1741,3 +1741,10 @@ int nvgpu_tsg_set_sched_exit_wait_for_errbar(struct nvgpu_channel *ch, bool enab return err; } #endif + +int nvgpu_tsg_preempt(struct gk20a *g, struct nvgpu_tsg *tsg) +{ + u32 runlist_id = tsg->runlist == NULL ? INVAL_ID : tsg->runlist->id; + + return g->ops.fifo.preempt_tsg(g, runlist_id, tsg->tsgid); +} diff --git a/drivers/gpu/nvgpu/common/gr/gr_setup.c b/drivers/gpu/nvgpu/common/gr/gr_setup.c index f836e70d3..6ce183f48 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_setup.c +++ b/drivers/gpu/nvgpu/common/gr/gr_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -195,7 +195,7 @@ int nvgpu_gr_setup_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num, g->ops.tsg.disable(tsg); - err = g->ops.fifo.preempt_tsg(g, tsg); + err = nvgpu_tsg_preempt(g, tsg); if (err != 0) { nvgpu_err(g, "preempt failed %d", err); goto enable_tsg; diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.c index 03ada501c..21d368ea5 100644 --- a/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -60,7 +60,7 @@ int vgpu_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) return err; } -int vgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_tsg_preempt_params *p = @@ -71,13 +71,14 @@ int vgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) msg.cmd = TEGRA_VGPU_CMD_TSG_PREEMPT; msg.handle = vgpu_get_handle(g); - p->tsg_id = tsg->tsgid; + p->runlist_id = runlist_id; + p->tsg_id = tsgid; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); err = err ? err : msg.ret; if (err) { nvgpu_err(g, - "preempt tsg %u failed", tsg->tsgid); + "preempt tsg %u failed", tsgid); } return err; diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.h index ce142d892..75376d05f 100644 --- a/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.h +++ b/drivers/gpu/nvgpu/common/vgpu/fifo/preempt_vgpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,6 +28,6 @@ struct nvgpu_channel; struct nvgpu_tsg; int vgpu_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch); -int vgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg); +int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid); #endif diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c index 8e8709724..74b62a2e4 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -144,14 +144,17 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) return ret; } -int gk20a_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { int ret = 0; #ifdef CONFIG_NVGPU_LS_PMU u32 token = PMU_INVALID_MUTEX_OWNER_ID; int mutex_ret = 0; #endif - nvgpu_log_fn(g, "tsgid: %d", tsg->tsgid); + + (void)runlist_id; + + nvgpu_log_fn(g, "tsgid: %d", tsgid); /* we have no idea which runlist we are using. lock all */ nvgpu_runlist_lock_active_runlists(g); @@ -159,7 +162,7 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) mutex_ret = nvgpu_pmu_lock_acquire(g, g->pmu, PMU_MUTEX_ID_FIFO, &token); #endif - ret = gk20a_fifo_preempt_locked(g, tsg->tsgid, ID_TYPE_TSG); + ret = gk20a_fifo_preempt_locked(g, tsgid, ID_TYPE_TSG); #ifdef CONFIG_NVGPU_LS_PMU if (mutex_ret == 0) { if (nvgpu_pmu_lock_release(g, g->pmu, @@ -174,10 +177,10 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) if (nvgpu_platform_is_silicon(g)) { nvgpu_err(g, "preempt timed out for tsgid: %u, " "ctxsw timeout will trigger recovery if needed", - tsg->tsgid); + tsgid); } else { - nvgpu_err(g, "preempt TSG %d timeout", tsg->tsgid); - nvgpu_rc_preempt_timeout(g, tsg); + nvgpu_err(g, "preempt TSG %d timeout", tsgid); + nvgpu_rc_preempt_timeout(g, &g->fifo.tsg[tsgid]); } } diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.h b/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.h index 4ff4de918..d5dc77391 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.h +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -30,7 +30,7 @@ struct nvgpu_tsg; void gk20a_fifo_preempt_trigger(struct gk20a *g, u32 id, unsigned int id_type); int gk20a_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch); -int gk20a_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg); +int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid); int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, bool preempt_retries_left); diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c index 7e6891db9..c2eb9f33d 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -376,5 +376,5 @@ int gv11b_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) nvgpu_log_info(g, "chid:%d tsgid:%d", ch->chid, tsg->tsgid); /* Preempt tsg. Channel preempt is NOOP */ - return g->ops.fifo.preempt_tsg(g, tsg); + return nvgpu_tsg_preempt(g, tsg); } diff --git a/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c index 246ec5bb0..6c6aa7739 100644 --- a/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c @@ -323,7 +323,7 @@ int gv11b_tsg_add_subctx_channel_hw(struct nvgpu_channel *ch, bool replayable) nvgpu_mutex_acquire(&tsg->ctx_init_lock); g->ops.tsg.disable(tsg); - err = g->ops.fifo.preempt_tsg(g, tsg); + err = nvgpu_tsg_preempt(g, tsg); if (err != 0) { g->ops.tsg.enable(tsg); nvgpu_mutex_release(&tsg->ctx_init_lock); diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c index 87a3a17e5..3acc92579 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics * - * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -67,7 +67,7 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, g->ops.tsg.disable(tsg); - ret = g->ops.fifo.preempt_tsg(g, tsg); + ret = nvgpu_tsg_preempt(g, tsg); if (ret != 0) { nvgpu_err(g, "failed to preempt TSG"); goto out; @@ -130,7 +130,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, g->ops.tsg.disable(tsg); - ret = g->ops.fifo.preempt_tsg(g, tsg); + ret = nvgpu_tsg_preempt(g, tsg); if (ret != 0) { nvgpu_err(g, "failed to preempt TSG"); goto out; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h index 60187f42c..1d3bc4ef2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -70,7 +70,8 @@ struct gops_fifo { * @brief Preempt TSG. * * @param g [in] Pointer to GPU driver struct. - * @param tsg [in] Pointer to TSG struct. + * @param runlist_id [in] Runlist ID. + * @param tsgid [in] TSG ID. * * - Acquire lock for active runlist. * - Write h/w register to trigger TSG preempt for \a tsg. @@ -90,7 +91,7 @@ struct gops_fifo { * @retval -ETIMEDOUT when preemption was triggered, but did not * complete within preemption poll timeout. */ - int (*preempt_tsg)(struct gk20a *g, struct nvgpu_tsg *tsg); + int (*preempt_tsg)(struct gk20a *g, u32 runlist_id, u32 tsgid); /** * @brief Enable and configure FIFO. diff --git a/drivers/gpu/nvgpu/include/nvgpu/preempt.h b/drivers/gpu/nvgpu/include/nvgpu/preempt.h index b1511a827..ce2068761 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/preempt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/preempt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -94,7 +94,8 @@ void nvgpu_fifo_preempt_runlists_for_rc(struct gk20a *g, u32 runlists_bitmask); * @brief Preempt TSG. * * @param g [in] Pointer to GPU driver struct. - * @param tsg [in] Pointer to TSG struct. + * @param runlist_id [in] Runlist ID. + * @param tsgid [in] TSG ID. * * Preempt TSG: * - Acquire lock for active runlist. @@ -115,5 +116,5 @@ void nvgpu_fifo_preempt_runlists_for_rc(struct gk20a *g, u32 runlists_bitmask); * @retval -ETIMEDOUT when preemption was triggered, but did not * complete within preemption poll timeout. */ -int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg); +int nvgpu_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid); #endif /* NVGPU_PREEMPT_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h index 6f238c7d9..40c4a7ed4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -941,4 +941,15 @@ void nvgpu_tsg_reset_faulted_eng_pbdma(struct gk20a *g, struct nvgpu_tsg *tsg, int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_channel *ch, bool enable); int nvgpu_tsg_set_sched_exit_wait_for_errbar(struct nvgpu_channel *ch, bool enable); #endif + +/** + * @brief Preempt a tsg + * + * @param g [in] The GPU driver struct. + * @param tsg [in] Pointer to TSG struct. + * + * Preempt the tsg. + */ +int nvgpu_tsg_preempt(struct gk20a *g, struct nvgpu_tsg *tsg); + #endif /* NVGPU_TSG_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index ae200c50a..a6be3bd12 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h @@ -385,6 +385,7 @@ struct tegra_vgpu_tsg_bind_unbind_channel_params { }; struct tegra_vgpu_tsg_preempt_params { + u32 runlist_id; u32 tsg_id; }; diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c index 9638794ba..70f281e2d 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1203,7 +1203,7 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, return err; } /* preempt TSG */ - err = g->ops.fifo.preempt_tsg(g, tsg); + err = nvgpu_tsg_preempt(g, tsg); gk20a_idle(g); break; } diff --git a/userspace/units/fifo/channel/nvgpu-channel.c b/userspace/units/fifo/channel/nvgpu-channel.c index c131e6b50..b557a5a6a 100644 --- a/userspace/units/fifo/channel/nvgpu-channel.c +++ b/userspace/units/fifo/channel/nvgpu-channel.c @@ -1536,9 +1536,9 @@ static const char *f_channel_suspend_resume[] = { "work_completion_cancel_sync", }; -static int stub_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +static int stub_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { - stub[0].tsgid = tsg->tsgid; + stub[0].tsgid = tsgid; return 0; } diff --git a/userspace/units/fifo/preempt/gv11b/nvgpu-preempt-gv11b.c b/userspace/units/fifo/preempt/gv11b/nvgpu-preempt-gv11b.c index a3d744589..a6cfe4827 100644 --- a/userspace/units/fifo/preempt/gv11b/nvgpu-preempt-gv11b.c +++ b/userspace/units/fifo/preempt/gv11b/nvgpu-preempt-gv11b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -149,7 +149,7 @@ static int stub_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id, bool recover) return 0; } -static int stub_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +static int stub_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { return 1; } @@ -276,7 +276,8 @@ int test_gv11b_fifo_preempt_tsg(struct unit_module *m, struct gk20a *g, branches & F_PREEMPT_TSG_PLATFORM_SILICON ? true : false; - err = EXPECT_BUG(nvgpu_fifo_preempt_tsg(g, tsg)); + err = EXPECT_BUG(nvgpu_fifo_preempt_tsg(g, + tsg->runlist->id, tsg->tsgid)); if (branches & F_PREEMPT_TSG_PREEMPT_LOCKED_FAIL) { if (branches & F_PREEMPT_TSG_PLATFORM_SILICON) { diff --git a/userspace/units/fifo/preempt/nvgpu-preempt.c b/userspace/units/fifo/preempt/nvgpu-preempt.c index d77df7150..54fa96810 100644 --- a/userspace/units/fifo/preempt/nvgpu-preempt.c +++ b/userspace/units/fifo/preempt/nvgpu-preempt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -106,9 +106,9 @@ static int stub_fifo_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch) return 0; } -static int stub_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +static int stub_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { - stub[0].tsgid = tsg->tsgid; + stub[0].tsgid = tsgid; return 0; } diff --git a/userspace/units/fifo/tsg/nvgpu-tsg.c b/userspace/units/fifo/tsg/nvgpu-tsg.c index 065ac2f60..784767633 100644 --- a/userspace/units/fifo/tsg/nvgpu-tsg.c +++ b/userspace/units/fifo/tsg/nvgpu-tsg.c @@ -418,7 +418,7 @@ done: #define F_TSG_UNBIND_CHANNEL_LAST BIT(9) static int stub_fifo_preempt_tsg_EINVAL( - struct gk20a *g, struct nvgpu_tsg *tsg) + struct gk20a *g, u32 runlist_id, u32 tsgid) { return -EINVAL; } @@ -1305,9 +1305,9 @@ static const char *f_tsg_abort[] = { "non_referenceable" }; -static int stub_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +static int stub_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { - stub[0].tsgid = tsg->tsgid; + stub[0].tsgid = tsgid; return 0; } diff --git a/userspace/units/gr/setup/nvgpu-gr-setup.c b/userspace/units/gr/setup/nvgpu-gr-setup.c index d1a1559ac..d33a23f79 100644 --- a/userspace/units/gr/setup/nvgpu-gr-setup.c +++ b/userspace/units/gr/setup/nvgpu-gr-setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -75,8 +75,7 @@ struct gr_gops_org { int (*wait_idle)(struct gk20a *g); int (*ctrl_ctxsw)(struct gk20a *g, u32 fecs_method, u32 data, u32 *ret_val); - int (*fifo_preempt_tsg)(struct gk20a *g, - struct nvgpu_tsg *tsg); + int (*fifo_preempt_tsg)(struct gk20a *g, u32 runlist_id, u32 tsgid); bool (*is_valid)(u32 class_num); bool (*is_valid_compute)(u32 class_num); }; @@ -129,7 +128,7 @@ static int stub_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method, return 0; } -static int stub_gr_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg) +static int stub_gr_fifo_preempt_tsg(struct gk20a *g, u32 runlist_id, u32 tsgid) { return -1; }