From 8f715117d4c45d17a9ee08559a540a79437371c6 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Thu, 7 May 2020 20:51:55 -0700 Subject: [PATCH] gpu: nvgpu: modify NVGPU_SUPPORT_COMPRESSION bit Update NVGPU_SUPPORT_COMPRESSION bit position within GPU characteristics to keep NVGPU_SUPPORT_COMPRESSION flag same as QNX flag. JIRA NVGPU-4666 Change-Id: Iaf3ea49dbb26b3d7385ef426283a36d2f414b25f Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340989 Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Seema Khowala Reviewed-by: Lakshmanan M Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- include/uapi/linux/nvgpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 9f8ca181d..38c4e8aca 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -174,7 +174,7 @@ struct nvgpu_gpu_zbc_query_table_args { /* Fault recovery is enabled */ #define NVGPU_GPU_FLAGS_SUPPORT_FAULT_RECOVERY (1ULL << 33) /* Compression is enabled */ -#define NVGPU_GPU_FLAGS_SUPPORT_COMPRESSION (1ULL << 34) +#define NVGPU_GPU_FLAGS_SUPPORT_COMPRESSION (1ULL << 36) /* SM LRF ECC is enabled */ #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) /* SM SHM ECC is enabled */