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gpu: nvgpu: fix dGPU clk measurement

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- For dGPU clk measurement, wrap around condition of conuter was
not considered.
- This patch implements retry mechanism for wrap around condition.

Bug 2637525
Bug 200530176

Change-Id: I051cfa6f7721cec76d727e4977fd82b8da9c6243
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152256
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaibhav Kachore
2019-07-12 13:15:49 +05:30
committed by mobile promotions
parent e8c53b4e81
commit 8f99fe87d9
1 changed files with 35 additions and 15 deletions
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40
drivers/gpu/nvgpu/hal/clk/clk_gv100.c
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@@ -175,6 +175,8 @@ u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
u64 cntr_start = 0; u64 cntr_start = 0;
u64 cntr_stop = 0; u64 cntr_stop = 0;
u64 start_time, stop_time; u64 start_time, stop_time;
const int max_iterations = 3;
int i = 0;
struct clk_gk20a *clk = &g->clk; struct clk_gk20a *clk = &g->clk;
@@ -186,22 +188,40 @@ u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
nvgpu_mutex_acquire(&clk->clk_mutex); nvgpu_mutex_acquire(&clk->clk_mutex);
/* Read the counter values */ for (i = 0; i < max_iterations; i++) {
/* Counter is 36bits , 32 bits on addr[0] and 4 lsb on addr[1] others zero*/ /*
cntr_start = (u64)gk20a_readl(g, c->cntr.reg_cntr_addr[0]); * Read the counter values. Counter is 36 bits, 32
cntr_start += ((u64)gk20a_readl(g, c->cntr.reg_cntr_addr[1]) << 32); * bits on addr[0] and 4 lsb on addr[1] others zero.
*/
cntr_start = (u64)nvgpu_readl(g,
c->cntr.reg_cntr_addr[0]);
cntr_start += ((u64)nvgpu_readl(g,
c->cntr.reg_cntr_addr[1]) << 32);
start_time = (u64)nvgpu_hr_timestamp_us(); start_time = (u64)nvgpu_hr_timestamp_us();
nvgpu_udelay(XTAL_CNTR_DELAY); nvgpu_udelay(XTAL_CNTR_DELAY);
stop_time = (u64)nvgpu_hr_timestamp_us(); stop_time = (u64)nvgpu_hr_timestamp_us();
cntr_stop = (u64)gk20a_readl(g, c->cntr.reg_cntr_addr[0]); cntr_stop = (u64)nvgpu_readl(g,
cntr_stop += ((u64)gk20a_readl(g, c->cntr.reg_cntr_addr[1]) << 32); c->cntr.reg_cntr_addr[0]);
/*Calculate the difference with Acutal time and convert to KHz*/ cntr_stop += ((u64)nvgpu_readl(g,
cntr = (u32)(((cntr_stop - cntr_start) * 1000U) / c->cntr.reg_cntr_addr[1]) << 32);
(u32)(stop_time-start_time));
if (cntr_stop > cntr_start) {
/*
* Calculate the difference with Acutal time
* and convert to KHz
*/
cntr = (u32)(((cntr_stop - cntr_start) /
(stop_time - start_time)) * 1000U);
nvgpu_mutex_release(&clk->clk_mutex); nvgpu_mutex_release(&clk->clk_mutex);
return cntr; return cntr;
}
/* Else wrap around detected. Hence, retry. */
}
nvgpu_mutex_release(&clk->clk_mutex);
/* too many iterations, bail out */
nvgpu_err(g, "failed to get clk rate");
return -EBUSY;
} }
int gv100_clk_domain_get_f_points( int gv100_clk_domain_get_f_points(