diff --git a/userspace/units/fifo/engine/nvgpu-engine.c b/userspace/units/fifo/engine/nvgpu-engine.c
index b906c9e48..6575ea6de 100644
--- a/userspace/units/fifo/engine/nvgpu-engine.c
+++ b/userspace/units/fifo/engine/nvgpu-engine.c
@@ -362,7 +362,9 @@ int test_engine_interrupt_mask(struct unit_module *m,
 		struct gk20a *g, void *args)
 {
 	int ret = UNIT_FAIL;
-	u32 intr_mask = nvgpu_engine_interrupt_mask(g);
+	u32 intr_mask =
+		nvgpu_gr_engine_interrupt_mask(g) |
+		nvgpu_ce_engine_interrupt_mask(g);
 	u32 all_mask = 0U;
 	u32 ce_reset_mask;
 	u32 mask;
diff --git a/userspace/units/fifo/engine/nvgpu-engine.h b/userspace/units/fifo/engine/nvgpu-engine.h
index 7ad301dd1..ef2954641 100644
--- a/userspace/units/fifo/engine/nvgpu-engine.h
+++ b/userspace/units/fifo/engine/nvgpu-engine.h
@@ -153,12 +153,13 @@ int test_engine_enum_from_type(struct unit_module *m,
 /**
  * Test specification for: test_engine_interrupt_mask
  *
- * Description: Branch coverage for nvgpu_engine_interrupt_mask,
- *              nvgpu_engine_act_interrupt_mask and
- *              nvgpu_engine_get_all_ce_reset_mask
+ * Description: Engine interrupt masks
  *
  * Test Type: Feature based
  *
+ * Targets: nvgpu_gr_engine_interrupt_mask, nvgpu_ce_engine_interrupt_mask,
+ * nvgpu_engine_act_interrupt_mask, nvgpu_engine_get_all_ce_reset_mask
+ *
  * Input: test_engine_ids must have run.
  *
  * Steps: