From 8fa2fcd9dadec246a3f57b0c09b12d876ad8f7cc Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Wed, 27 Nov 2019 14:30:47 -0500 Subject: [PATCH] gpu: nvgpu: unit: use gr/ce engine interrupt mask nvgpu_engine_interrupt_mask has been split into nvgpu_gr_engine_interrupt_mask and nvgpu_gr_engine_interrupt_mask. Update test_engine_interrupt_mask to combine them. Jira NVGPU-3693 Change-Id: I1e09ff3efd83415120773da75f8b512a481ee14c Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2249913 Reviewed-by: Vedashree Vidwans Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- userspace/units/fifo/engine/nvgpu-engine.c | 4 +++- userspace/units/fifo/engine/nvgpu-engine.h | 7 ++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/userspace/units/fifo/engine/nvgpu-engine.c b/userspace/units/fifo/engine/nvgpu-engine.c index b906c9e48..6575ea6de 100644 --- a/userspace/units/fifo/engine/nvgpu-engine.c +++ b/userspace/units/fifo/engine/nvgpu-engine.c @@ -362,7 +362,9 @@ int test_engine_interrupt_mask(struct unit_module *m, struct gk20a *g, void *args) { int ret = UNIT_FAIL; - u32 intr_mask = nvgpu_engine_interrupt_mask(g); + u32 intr_mask = + nvgpu_gr_engine_interrupt_mask(g) | + nvgpu_ce_engine_interrupt_mask(g); u32 all_mask = 0U; u32 ce_reset_mask; u32 mask; diff --git a/userspace/units/fifo/engine/nvgpu-engine.h b/userspace/units/fifo/engine/nvgpu-engine.h index 7ad301dd1..ef2954641 100644 --- a/userspace/units/fifo/engine/nvgpu-engine.h +++ b/userspace/units/fifo/engine/nvgpu-engine.h @@ -153,12 +153,13 @@ int test_engine_enum_from_type(struct unit_module *m, /** * Test specification for: test_engine_interrupt_mask * - * Description: Branch coverage for nvgpu_engine_interrupt_mask, - * nvgpu_engine_act_interrupt_mask and - * nvgpu_engine_get_all_ce_reset_mask + * Description: Engine interrupt masks * * Test Type: Feature based * + * Targets: nvgpu_gr_engine_interrupt_mask, nvgpu_ce_engine_interrupt_mask, + * nvgpu_engine_act_interrupt_mask, nvgpu_engine_get_all_ce_reset_mask + * * Input: test_engine_ids must have run. * * Steps: